Design question: 3.3v in (3.3v out and 1.8v out) OR 1.8v in (1.8v out and 1.8v)

[Sarcarean]

So I have a design problem that has made me so I thought I would ask in case someone already has a good solution / circuit

I am designing a small board with a SPI header (with GND/VCC) and an Altera MAX V CPLD.

The header will either be connected to a system that is either 3.3v or 1.8v logic and supply (500mA). The CPLD has 3 supply in: IO1 (SPI slave), IO2 (output) and VCCINT (CPLD core).

VCCINT needs to always be 1.8v. IO1 and IO2 need to be the same VCC_IN (either 3.3v or 1.8v according to the system bus VCC). (And yes, the CPLD is pre-programmed with VHDL IO that match the bus VCC).

So this is easy if only one scenario is considered, for example, if VCC_IN is 3.3v, I could connect that to a LDO such as a MIC5356 (1.8v/3.3v reg) and 1V8_OUT to the VCCINT and the 3V_OUT to the IO1 and IO2. But if the bus is 1.8v, the LDO is too low to enable (2.2V is min) and nothing is output.

So does anyone know a simple solution (circuit) to overcome this scenario without using a jumper? Possibly a specific LDO part that would work for this circuit? Or a PNP MOSFET circuit?

[T3sl4co1l]

So, you just need an LDO with a lower enable voltage?

Tim

[Sarcarean]

Hi Tim,

no, I don't think that will solve the problem. Because in the case of VCC=1.8, the IO1 and IO2 will not have 1.8V supply.

This is actually a kind of logic puzzle.

What I am thinking now, is using 2 LDO (a 1.8v, and a combo 1.8v and 3.3v). The 1.8v only LDO powers the VCC_INT. I will connect a supervisory circuit to the input of the 3.3V EN line and to a NOT GATE to the 1.8V EN line of the combo LDO. So that if the VCC_IN > 2.5, it will power IO1 and IO2 with 3.3v or 1.8v if < 2.5v.

But maybe I am over engineering this? Is there a easier way?

[Zero999]

I don't understand the problem.

Use the NCP5662, which has an enable threshold of 1.3V.

http://www.onsemi.com/pub/Collateral/NCP5662-D.PDF

[Sarcarean]

@Hero999 Hi! Well because in the scenario that the SPI port has a 1.8v VCC connected, the LDO (1.8 fixed) to power the VCC_INT (the CPLD) would fall to below an acceptable level. Unless the NCP5662 is better than 1% drop and would allow input of 1.8V and output 1.75V?

[slugrustle]

Power management can be tricky, especially with chips that have complex powerup schemes like FPGAs. They sometimes require the power rails to be sequenced in a certain order, and so on. I'll assume that's not the case in your application.

Simplest I can think of is to keep the MIC5356 you've found for the 3.3V scenario, but add two low Rds_on logic-level P-channel mosfets (like DMP2035U-7) with source tied to VCC_IN, drain of Q1 tied to IO1 & IO2, and drain of Q2 tied to VCCINT. Tie the gates together, pull them up to VCC_IN with a 47k resistor, and drive them with a voltage monitor like BU4220G or NCP301LSN20T1G (2.0V threshold, active low. 1.9V threshold sometimes also available). The voltage monitor will pull the gates low when the input voltage is below 2.0V - (hysteresis and tolerance), bypassing the LDO and connecting IO1, IO2, and VCCINT to VCC_IN.

That's just an idea. No guarantees you won't break a fancy CPLD chip.

I had to make a supply monitor / cutoff circuit for a work project once. I ended up using a window comparator with internal reference (TPS3700, but MIC841 is cheaper) followed by a PIC10LF320. This allowed me to ignore short glitch periods, to check for undervoltage and overvoltage, and to insert custom time delays. The micro controlled the input load switch (P-mosfet) and both the micro and comparator were supplied from a 3.3V regulator with up to 40V input voltage. The load could operate from 10.8V - 16V, but had to be turned off outside that range.

So I'm biased, but a window comparator with internal reference whose output is checked by a tiny microcontroller is quite useful in these situations. The MIC841 runs on 1.5V - 5.5V Vcc, and the ATTiny9 runs on 1.8V - 5.5V Vcc. Pairing these with a MIC5356 and two bypass P-mosfets would let you delay Pmos turn-on until the supply was within your 1.8V range for a solid second, for example.

[Sarcarean]

@slugrustle reading your solution is brilliant! You defiantly nailed the problem originally posted. I actually ended up implementing the logic I had in the CPLD and doing it in a FPGA instead and instead of having SPI to Altera CPLD adapter. The FPGA featured the ability to change bank VCC on the fly for the needed voltage changes.