Author Topic: Designing model train layout I/O and PWM speed control  (Read 39861 times)

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Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #25 on: November 21, 2017, 02:43:08 pm »
Most likely just RCLK and SRCLK, unless you also want to use G for bulk PWM dimming of all the LED loads.

I had thought of being able to dim all LED's on the control panel so that when the room lights are dimmed I could then dim the control panel so that 60 LED's didn't light the room up. PWM on the G pin is a good idea ! I might include this just in case I want to go down this path. I'll look for a quad buffer version of those level translators mentioned above.
 

Offline C

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Re: Designing shift register circuit for SPI bus
« Reply #26 on: November 21, 2017, 03:20:54 pm »
large model railway
drive points solenoids

Some people would like a quiet slow points change for their model.
You could do this with an RC Servo if you want this.
The same circuit could also move crossing gates.


 

Offline ilium007Topic starter

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Designing shift register circuit for SPI bus
« Reply #27 on: November 21, 2017, 03:36:46 pm »
They are Peco points which my father has already purchased the 26 x Peco solenoids for. There are 4 other dual gauge tracks that I have already built slow moving servo actuators for.
 

Online Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #28 on: November 21, 2017, 03:38:20 pm »
For indicator LED driving, you'd be better off with a MAX7219 or MAX7221.  Each can drive a 8x8 matrix of LEDs with 40mA at 1/8 duty cycle, doesn't need current limiting resistors for each LED and has an overall brightness control register.   They can also drive seven segment displays, and you can mix  BCD decoding and raw matrix on the same chip - e.g. four digits + a 4x8 matrix. Cheaper Chinese clones of these chips are usually of acceptable quality.  They are popular in the Arduino community, so you'll easily be able to find libraries for them.
 

Offline ilium007Topic starter

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Designing shift register circuit for SPI bus
« Reply #29 on: November 21, 2017, 03:41:25 pm »
These boards are not just driving LED’s. I’d rather build a generic board that can be used for other things, not just driving leds. The TPIC shift registers are nice because of their current sink limits that mean I can drive leds at 20mA each concurrently as well as drive relays. I don’t want to get in to matrix driving leds.
 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #30 on: November 21, 2017, 10:59:37 pm »
This is all RS Components here in Australia lists for a non-inverting level shifting buffer (same part mentioned in this thread):



And its on backorder until April next year....
 

Online Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #31 on: November 21, 2017, 11:22:34 pm »
As I said earlier, *ANY* 74HCT  simple logic gate will do for upwards translation as long as you can wire it as a non-inverting buffer, and for downwards translation, you can use a potential divider - 1K5 upper resistor, 3K3  lower resistor with about 10pF across the upper resistor should do nicely as long as its close to the 3.3V level input.

It looks like Mouser Australia currently has stock of both 74LVC1T45 and 74LVC2T45.
 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #32 on: November 21, 2017, 11:23:55 pm »
You need to buffer ONLY those signals that would otherwise be wired in parallel to the whole daisychain.  Most likely just RCLK and SRCLK, unless you also want to use G for bulk PWM dimming of all the LED loads.

With PCB area being the dominant cost for prototypes (often 10x of a board is a negligible cost increase over 1x) it doesn't make a lot of sense to put many shift registers on the same board.  The extra cost of right angle M and F headers and PCB mount spade lugs and  4x the number of buffers will almost certainly be cheaper than larger boards.  It *may* make sense to put two shift registers on the same board, depending on the size of the relays, and any steps in cost vs board area.   Its different economics if you are using padboard or stripboard - then you need to pack as many as possible on one standard size board

Understood. I will look at the economics of the board sizes. Only one type of board will be a relay board and 8 relays is all I require for this project so that one is easy. The other boards will be a N-channel MOSFET output board to trigger the 26 solenoids (pulse current is approx 3A !), so maybe a 32 output board (4 x TPIC6C595's and 1 x buffer), and a board just for driving the LED's on a control panel, approx 50 LED's all within close proximity so maybe 2 x 32 output boards just for LED's (similar to the MOSFTE boards just without the 2N7002 output MOSFETS and flyback diodes (the TPIC6C595's will sink enough current for the LED's).

I want to be able to use these designs later on for other projects so I'm trying to build things as generic as possible.

The problem with Mouser is the $24 flat shipping charge on orders under $60 ! RS does free shipping on all orders but has no stock !!

I will look further at the voltage divider, what are the drawbacks vs an IC ? Surely there must be benefits in using the IC.
« Last Edit: November 21, 2017, 11:27:04 pm by ilium007 »
 

Online Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #33 on: November 21, 2017, 11:57:04 pm »
The voltage divider has minimal drive capability - even 2" of track to a single input could be a problem if its too close to the SPI clock output.

It would be worth looking through RS's site for stocked 74LVC1Gxx non inverting gates, then check the datasheet as 5V tolerant inputs (when the gate's Vcc is 3.3V) are common in that logic family.

2N7002 mosfets would be too wimpy for driving the points solenoids. You have two options there - either 74HC595 driving the gates of logic level power MOSFETs, or PNP power transistors as emitter followers to boot the TPIC6C595 output current capability.   If you are clever with your PCB design, you could have one TPIC6C595 board layout that depending on how you populate it could have relays, PNP power transistors ore current limiting resistors for LEDs.

One concern with driving points solenoids is burning out their coils if the output stays on.  There are two ways of mitigating this - either put a large electrolytic capacitor + a resistor across it in series with the coil common so once the capacitor has discharged the resistor limits the remaining current, or add a current sensor in the positive feed to all the solenoids on that interface board, and if the current stays on too long, reset the TPIC6c595.
« Last Edit: November 22, 2017, 12:13:27 am by Ian.M »
 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #34 on: November 22, 2017, 12:29:22 am »
I am using a capacitor discharge unit to drive the output for the solenoids, I think it reduces its output current after activation but these are only ever pulsed on. I’m using a different DPAK2 package MOSFET for the solenoids - NTD5867NLT4G. I’m using the 2N7002 MOSFETs to drive relay coils only.
 

Offline phil from seattle

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Re: Designing shift register circuit for SPI bus
« Reply #35 on: November 22, 2017, 01:44:58 am »

The problem with Mouser is the $24 flat shipping charge on orders under $60 ! RS does free shipping on all orders but has no stock !!

Are you not in the US? I opt for USPS delivery from them for small orders and it's usually like $4. Most of my orders are less than $60.
 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #36 on: November 22, 2017, 01:46:05 am »

The problem with Mouser is the $24 flat shipping charge on orders under $60 ! RS does free shipping on all orders but has no stock !!

Are you not in the US? I opt for USPS delivery from them for small orders and it's usually like $4. Most of my orders are less than $60.

No - I'm in Australia, I think we have the worst postage costs in the world !!
 

Online Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #37 on: November 22, 2017, 02:11:53 am »
I am using a capacitor discharge unit to drive the output for the solenoids, I think it reduces its output current after activation but these are only ever pulsed on. I’m using a different DPAK2 package MOSFET for the solenoids - NTD5867NLT4G. I’m using the 2N7002 MOSFETs to drive relay coils only.
Yes, a capacitor discharge circuit avoids the risk of burnout, if the MCU crashes at the wrong moment or corrupted data is shifted into the solenoid interface and not updated quickly enough. 

Its probably worth updating *ALL* the outputs every time the firmware executes its main loop - SPI is pretty efficient so even with a reasonably low click speed, (e,g a few hundred KHz) it should be possible to update them all in under a millisecond, so the overhead isn't too bad.  That wa any glitches that cause incorrect output states get rectified a small fraction of a second later.

What relays are you using (or what is their coil resistance)?
If you cant drive them direct from a TPIC6C595,  then you can probably do a 74HC595 board with footprints for 2N7002 and your DPAK2 MOSFETs.

 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #38 on: November 22, 2017, 02:16:32 am »
I am using a capacitor discharge unit to drive the output for the solenoids, I think it reduces its output current after activation but these are only ever pulsed on. I’m using a different DPAK2 package MOSFET for the solenoids - NTD5867NLT4G. I’m using the 2N7002 MOSFETs to drive relay coils only.
Yes, a capacitor discharge circuit avoids the risk of burnout, if the MCU crashes at the wrong moment or corrupted data is shifted into the solenoid interface and not updated quickly enough. 

Its probably worth updating *ALL* the outputs every time the firmware executes its main loop - SPI is pretty efficient so even with a reasonably low click speed, (e,g a few hundred KHz) it should be possible to update them all in under a millisecond, so the overhead isn't too bad.  That wa any glitches that cause incorrect output states get rectified a small fraction of a second later.

What relays are you using (or what is their coil resistance)?
If you cant drive them direct from a TPIC6C595,  then you can probably do a 74HC595 board with footprints for 2N7002 and your DPAK2 MOSFETs.

I haven't decided on relays yet. I started looking at data sheets and costs yesterday and some of these get quite expensive per unit. I took advice from the previous thread and will do 12v relays. I am switching PWM current on train tracks so a DPST would work but they were more expensive than DPDT and had the same footprint. The coil resistance was about 300 ohm on all of them so about 40mA - I figured the 2N7002 behind the TPIC6C595 would be overkill - the TPIC6C595 could probably just do it by itself.

This was the relay I was thinking about using - 360 Ohm coil resistance / 33mA current draw:
http://au.rs-online.com/web/p/non-latching-relays/6803830/

The relays will switch the parallel track power to energise a different segment of the track - current draw of a single train on the tracks was measured at about 1A being driven by a 20kHz PWM Pololu MC33926 based driver:
https://www.pololu.com/product/1212

I like the idea of one board design that will accomodate all options. I think I will do 32 channel boards and save space for 8 optional relays on the board controlled off one of the 4 TPIC6C595 ICs that would give the 32 channels.
« Last Edit: November 22, 2017, 02:43:16 am by ilium007 »
 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #39 on: November 22, 2017, 02:27:06 am »
It would be worth looking through RS's site for stocked 74LVC1Gxx non inverting gates, then check the datasheet as 5V tolerant inputs (when the gate's Vcc is 3.3V) are common in that logic family.

You are right - there are a heap that will work for this scenario. Given I am having to level shift the 3.3v I will have to buffer all SPI lines I assume, SCLK, RCLK, SS and MOSI/MISO I will need a quad buffer - this one looks like it will work:

SN74LVC126AD
http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf



On the input cards that have the MISO line I will still need a single buffer IC with Vcc at 3.3v that will accept the 5v input such as the 74LVC1G125DRLR which is in stock at RS:
http://au.rs-online.com/web/p/buffer-line-driver-combinations/6626605/
« Last Edit: November 22, 2017, 02:36:10 am by ilium007 »
 

Online Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #40 on: November 22, 2017, 02:53:03 am »
No. you cant use a SN74LVC126A for the MCU output lines that need to shift up to 5V levels, as its max Vcc is 3.6V.   Use something from the 74HCT family that's non-inverting and not open drain.

For the input lines, you can use 74LVC1G125 powered at 3.3V. 

I recommend putting the level translating buffers on the MCU board.   On the shift register boards, only use 5V buffers.
 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #41 on: November 22, 2017, 02:55:12 am »
No. you cant use a SN74LVC126A for the MCU output lines that need to shift up to 5V levels, as its max Vcc is 3.6V.   Use something from the 74HCT family that's non-inverting and not open drain.

For the input lines, you can use 74LVC1G125 powered at 3.3V. 

I recommend putting the level translating buffers on the MCU board.   On the shift register boards, only use 5V buffers.
Ok understood. I read the data sheet wrong.
 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #42 on: November 22, 2017, 02:57:17 am »
No. you cant use a SN74LVC126A for the MCU output lines that need to shift up to 5V levels, as its max Vcc is 3.6V.   Use something from the 74HCT family that's non-inverting and not open drain.

For the input lines, you can use 74LVC1G125 powered at 3.3V. 

I recommend putting the level translating buffers on the MCU board.   On the shift register boards, only use 5V buffers.
Ok understood. I read the data sheet wrong.
I looked at the data sheet screen shot I posted above and it says Vcc max is 6.5v doesn’t it ? I’m confused now !
 

Online Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #43 on: November 22, 2017, 03:08:58 am »
See section 6.3 Recommended Operating Conditions for the voltage range it will function at.   Section 6.1 Absolute Maximum Ratings only tells you what it will survive without dying, not if it will function at that voltage.
 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #44 on: November 22, 2017, 03:09:38 am »
See section 6.3 Recommended Operating Conditions for the voltage range it will function at.   Section 6.1 Absolute Maximum Ratings only tells you what it will survive without dying, not if it will function at that voltage.
Ahhh ok
 

Offline ilium007Topic starter

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Designing shift register circuit for SPI bus
« Reply #45 on: November 22, 2017, 06:13:00 am »
I have looked at the 74HCT IC’s and the venerable 74HC125 came up and the data sheet also covers the 74HCT125 that was recommended above. I’m not sure why I need the HCT series given the HC will run at 5v and accept min Vin of 0v. It looks to me that the 74HC125 would work for the 3.3v input.



I found this data on another site:

https://electronicsclub.info/74series.htm

Quote
The 74HC family has High-speed CMOS circuitry, combining the speed of TTL with the very low power consumption of the 4000 series. They are CMOS ICs with the same pin arrangements as the older 74LS family. Note that 74HC inputs cannot be reliably driven by 74LS outputs because the voltage ranges used for logic 0 are not quite compatible, use 74HCT instead.

The 74HCT family is a special version of 74HC with 74LS TTL-compatible inputs so 74HCT can be safely mixed with 74LS in the same system. In fact 74HCT can be used as low-power direct replacements for the older 74LS ICs in most circuits. The minor disadvantage of 74HCT is a lower immunity to noise, but this is unlikely to be a problem in most situations.

For most new projects the 74HC family is the best choice. The 74LS and 74HCT families require a 5V supply so they are not convenient for battery operation.

So why do I choose HCT over HC IC’s ?

Sorry for all the questions.
« Last Edit: November 22, 2017, 06:15:15 am by ilium007 »
 

Online Siwastaja

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Re: Designing shift register circuit for SPI bus
« Reply #46 on: November 22, 2017, 06:35:04 am »
HC's have "normal CMOS" input thresholds halfway between GND and VCC, and unambigious range between about 30% and 70% of Vcc (slightly depending on the part, of course). I.e., when powered from 5V, to get "zero", you need to input < 1.5V, and to get "one", you need to input > 3.5V. The latter requirement makes it unusable for level conversion from 3.3V, as you'd need at least 3.5V input signal for reliable "one". So it typically works only by luck on the lab table until you put ten units on the field...

HCT parts, on the other hand, offer so-called TTL levels (one of the most misused terms ever, so now we are talking about the correct definition) on their inputs, which means they guarantee that anything over 2.4V is interpreted as "one", even with a 5V supply. That's why you can use a 74HCT buffer (or any other gate) to do a level conversion from a 3.3V to 5V.

Fancier level conversion parts exist, but if it's just unidirectional 3V3 output to 5V on a logic PCB, a HCT buffer is a good solution.
« Last Edit: November 22, 2017, 06:44:23 am by Siwastaja »
 
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Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #47 on: November 22, 2017, 06:38:05 am »
HC's have input thresholds halfway between GND and VCC, and unambigious range between about 30% and 70% of Vcc (slightly depending on the part, of course). I.e., when powered from 5V, to get "zero", you need to input < 1.5V, and to get "one", you need to input > 3.5V. The latter requirement makes it unusable for level conversion from 3.3V, as you'd need at least 3.5V input signal for reliable "one". So it typically works only by luck on the lab table until you put ten units on the field...

HCT parts, on the other hand, offer so-called TTL levels (one of the most misused terms ever, so now we are talking about the correct definition) on their inputs, which means they guarantee that anything over 2.4V is interpreted as "one", even with a 5V supply. That's why you can use a 74HCT buffer (or any other gate) to do a level conversion from a 3.3V to 5V.

Fancier level conversion parts exist, but if it's just unidirectional 3V3 output to 5V on a logic PCB, a HCT buffer is a good solution.
Great - I get it now. I just re-read the data sheet and found the reference to the threshold 1/2 way between GND and Vcc.

Thanks for your patience guys !
 

Offline ilium007Topic starter

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Re: Designing shift register circuit for SPI bus
« Reply #48 on: November 22, 2017, 12:30:27 pm »
I've just put a breadboard together with 2 x TPIC6C595 and 1 x 74HC125 (I'm testing at 5v as I don't yet have the Teensy 3.6 so the 74HC125 will work).

I have set up the 74HC125 buffer to handle SRCK and RCK and I'm just driving the OE inputs on the buffer with a digital pin off the Teensy++ 2.0 at 5v - so only using two buffers on the IC initially.

It was mentioned previously to do the level shifting on the uC board, which I will do when the time comes, and do buffering at 5v on the IO boards I am building, makes sense also.

This question is around buffering of the OE pins (that I am currently driving direct from the uC). Each IO board I build will have a buffer IC that requires OE pins on its buffer IC to be driven - I don't want to do this from the uC to every IO board in parallel. I wan't to give the SS signal to the first IO board and then buffer it along the chain of IO boards. How does this pin get buffered between boards given the SS signal from the uC will have to trigger the OE on the first IO board's 74HCT125 that is also buffering the very same SS signal - it will be using the SS feed to enable the buffer to buffer itself. I'm not sure if this makes sense, I have drawn a quick schematic to try and explain.



On the left I have SS_IN on pin 12 from the uC board at 5v, this same signal also feeds the OE pin 13 to then buffer itself out on pin 11. The OE on pin 13 will also feed the OE on pins 10 and 1. The buffered SS output on pin 11 is daisy chained to the next boards OE pins and SS buffer and the cycle repeats.

I am trying to avoid fan out issues from the uC board which may occur if I am running SS feeds to many IO boards.
« Last Edit: November 22, 2017, 01:22:18 pm by ilium007 »
 

Online Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #49 on: November 22, 2017, 01:10:29 pm »
For the 74HC125 control line output buffers simply tie all their /OE pins to 0V.   You *NEVER* need or want to tristate the output buffers.

The last input board in the chain (nearest to the MCU) needs tristate control of its data out, driven by /SS, but the others don't.   Put that /OE on a separate pin of the inter-board connector so you can connect it to /SS at the MCU and ground it at the connector for the next board.
 
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