Designing model train layout I/O and PWM speed control

[ilium007]

MRR ? I still want to be able to use these TPIC6C595 devices as they have excellent current capability for what I’m using them for on this project.

DCC is another whole can of worms I’m not getting in to ! It’s my fathers train layout and I’ve looked at DCC in the past and it’s on another level I don’t want to get involved with. I want to continue on the path of large scale basic I/O as I can use these learnings in other projects other than model railways !

[C]

For 74HCT595 in dip package

Pin 9 is serial data output and should connect to next 74HCT595 pin 14 serial data input

You might also want to add better/more labels to make drawing more under standable

[ilium007]

For 74HCT595 in dip package

Pin 9 is serial data output and should connect to next 74HCT595 pin 14 serial data input

You might also want to add better/more labels to make drawing more under standable

Sorry. This was just a quick hack up drawing, I’ll post a proper schematic later. I just wanted to know if I was on the right track for the output boards.

[bson]

MRR ?

MRR = model railroad

[ilium007]

MRR ?

MRR = model railroad

Hahah ok

[ilium007]

This is the updated output board idea with proper TPIC6C595 component in schematic - in the final schematic there will be 4 of the TPIC6C595 IC's per board.





Below is the input board and associated MCU board buffers / level shifter.

Starting at the MCU board:

• 74HCT125 used to shift voltage from 3.3v to 5v
• MOSI is included. I probably didn't have to, I just thought I could put it on the board connector
• I included a LATCH pin (digital I/O on the MCU) to perform the HIGH - LOW - HIGH pulse to load the input registers
• A seperate SS_2 pin is used to trigger OE on buffers and take the MISO input out of high impedance mode
• SCK is buffered out as well

On the input boards:

• Final schematic will show 8 x 74HC165's and 1 x 74HCT125 per board for 32 inputs
• The label numbering may be a bit confusing - I tried to show the number of buffers each signal has gone through
• SS_2_0 feeds the first buffer from the MCU board and outputs SS_2_1 which is used to turn on OE on all other buffers (at the same time as the MISO buffer is taken out of high impedance)
• CLK_1 input produces the CLK output for each 74HC165
• LATCH_1 loads each shift register
• CLK_INH is tied to GND - reading the datasheet I think this is what I am meant to do, with CLK_IHN LOW the data will shift out on the CLK pulses
• The final SER output feeds back into the QH which would then have its SER feed the next QH and so on back to the first 74HC165 before the MCU

Will including the extra digital pin for LATCH (IC U2 pin 12) alongside SS_2 (IC U2 pin 9) avoid the timing issues Ian.M mentioned earlier ?

I got the SER and QH pins mixed up, I’ll update tomorrow

[Ian.M]

When drawing schematics for boards that are going to be daisychained, *PLEASE* put all the host connections on one side and the next board interconnect on the other side.
There is a general convention for schematics that the flow should be left to right, so I would suggest drawing the output boards as if they were in a chain to the right of the MCU board, and the input boards as if they were to the left of the MCU.

It will help understanding to draw as much as possible of the schematic using individual logic symbols rather than IC physical pinout symbols - the schematic is not and should not be the wiring diagram.

[C]

I agree with lan.M
Poor drawings will waste a lot of your time.
Remember that some day you might need to relearn how a circuit works to fix, repair or change it.

On input board
If you enable and disable the parallel load to shift register then that Load pin could be shared between two or more input chains.

[Buriedcode]

I have done something similar with 595's and 165's, started with small boards with 8 in, and 8 out, but expanded to 64 of each (8 shift registers), this used SPI and some basic 'glue logic'.  It used the /SS line as a both a clock enable (when its low) and load (low-high transition).  It could also read in the inputs to the input shift register one  a high-low transition, making it pseudo-SPI compatible, but ended up using a separate IO for that.  I'll have to dig out the schem.

I can see why you'll need 3.3-5V conversion, I was assuming (wrongly) that the TPIC6C595 had TTL inputs, and might as well make them tristate-capable.

I would add some pulldowns (or pull ups) on inputs, because if you're going to have separate boards, you'll have inputs floating, which are protected but still would be best practice to keep them in a known state. 

[ilium007]

I agree with lan.M
Poor drawings will waste a lot of your time.
Remember that some day you might need to relearn how a circuit works to fix, repair or change it.

On input board
If you enable and disable the parallel load to shift register then that Load pin could be shared between two or more input chains.

Ok. Point taken, I’m learning here. I didn’t think they were that bad.

[ilium007]

I have done something similar with 595's and 165's, started with small boards with 8 in, and 8 out, but expanded to 64 of each (8 shift registers), this used SPI and some basic 'glue logic'.  It used the /SS line as a both a clock enable (when its low) and load (low-high transition).  It could also read in the inputs to the input shift register one  a high-low transition, making it pseudo-SPI compatible, but ended up using a separate IO for that.  I'll have to dig out the schem.

I can see why you'll need 3.3-5V conversion, I was assuming (wrongly) that the TPIC6C595 had TTL inputs, and might as well make them tristate-capable.

I would add some pulldowns (or pull ups) on inputs, because if you're going to have separate boards, you'll have inputs floating, which are protected but still would be best practice to keep them in a known state.

Thanks. I’m not sure what’s meant by the term ‘glue logic’ that’s been mentioned a couple of times now in this thread.
I’ll look at getting the pull down resistors in there as well.
If you could find your old schematic that would be appreciated.

[ilium007]

When drawing schematics for boards that are going to be daisychained, *PLEASE* put all the host connections on one side and the next board interconnect on the other side.
There is a general convention for schematics that the flow should be left to right, so I would suggest drawing the output boards as if they were in a chain to the right of the MCU board, and the input boards as if they were to the left of the MCU.

It will help understanding to draw as much as possible of the schematic using individual logic symbols rather than IC physical pinout symbols - the schematic is not and should not be the wiring diagram.

So from what you are saying, in KiCad I have to redraw each component to show its internal logic. The TPIC6C595 will look as follows:



I have not seen a single schematic involving the TPIC6595 on the internet while I have been researching this that shows that detail inside the little schematic box for the shift register. But if that’s what I’m supposed to be doing I will draw up the component in KiCad.

[Ian.M]

No.  That's TOO MUCH detail.  See the ANSI logic symbol on page 1 of the datasheet (though personally I detest ANSI logic symbols when working at gate level - you loose so much 'at a glance' comprehension because everything is a *~*~ing rectangle).

However for ease of drawing I'd use a plain rectangle with pins named according to the datasheet INSIDE it, and  grouped by function.  Put the eight load outputs evenly spaced at the top (as they are open drain^*), data in left edge center, data out right edge center, and control inputs bottom edge on the left.  Where to put the power connections is arguable: I'd use left edge near the top for Vcc and the right edge near the bottom for Gnd.

Use the usual convention of a small circle on the outside of the symbol at all inverting inputs (and inverting outputs), and a small triangle (pointing inwards, base on the edge) to indicate edge triggered strobes or clocks.  On its own, that indicates rising edge triggered.  With an external circle for inversion, its falling edge triggered.   

If you want to wire from the schematic, bracket the physical pin number at the end of the pin name, separated by a space.

You should also look at page 5 of the Philips 74HC595 datasheet for inspiration, (especially fig.5 for how to indicate internal function if you need to), though it doesn't use inversion circles and edge trigger triangles consistently.

* The usual convention is the 'flow' is down and right.  That doesn't mix well with  component level schematics with the +V rail at the top and Gno or -V rail at the bottom.  As the TPIC6C595 outputs are open drain, it makes for a neater schematic if they are belw the loads they are driving.

[ilium007]

No.  That's TOO MUCH detail.  See the ANSI logic symbol on page 1 of the datasheet (though personally I detest ANSI logic symbols when working at gate level - you loose so much 'at a glance' comprehension because everything is a *~*~ing rectangle).

However for ease of drawing I'd use a plain rectangle with pins named according to the datasheet INSIDE it, and  grouped by function.  Put the eight load outputs evenly spaced at the top (as they are open drain^*), data in left edge center, data out right edge center, and control inputs bottom edge on the left.  Where to put the power connections is arguable: I'd use left edge near the top for Vcc and the right edge near the bottom for Gnd.

Use the usual convention of a small circle on the outside of the symbol at all inverting inputs (and inverting outputs), and a small triangle (pointing inwards, base on the edge) to indicate edge triggered strobes or clocks.  On its own, that indicates rising edge triggered.  With an external circle for inversion, its falling edge triggered.   

If you want to wire from the schematic, bracket the physical pin number at the end of the pin name, separated by a space.

You should also look at page 5 of the Philips 74HC595 datasheet for inspiration, (especially fig.5 for how to indicate internal function if you need to), though it doesn't use inversion circles and edge trigger triangles consistently.

* The usual convention is the 'flow' is down and right.  That doesn't mix well with  component level schematics with the +V rail at the top and Gno or -V rail at the bottom.  As the TPIC6C595 outputs are open drain, it makes for a neater schematic if they are belw the loads they are driving.

Ok thanks - I will take a look at it all.

What about my messy circuit design, does each board reflect what we have spoken about in this thread ? Will the input board with the LATCH and SS pins overcome the timing issue (I still don't fully understand the requirement for the strobing mentioned earlier in the thread) ?

I found this page past night that explains, I think, the RC circuit to supply the pulse to the parallel load pin on the shift register. I can avoid having to implement this if I consume an additional pin from the MCU to do the parallel load can't I ? Although I do like the simplicity of the RC derived pulse, I just don't know how to calculate the time decay and how the tolerances of the components affect the timing.



http://www.openmusiclabs.com/learning/digital/input-matrix-scanning/hacks/

[Ian.M]

I'd have to pick through the logic in detail to comment on it properly.  At the moment I'd have to print them out and go through it with a pencil and the datasheets open to check - If you redraw the symbols by function rather than physical pinout, one can usually trace he signals without reference to the datasheet, unless the pin names are particularly cryptic, or you have no idea of that chip's function .

One thing to note - I wouldn't use 74HCT logic for anything except the first level-shifting buffer as it has much worse noise immunity than 74HC logic @5V Vcc and logic levels.

[ilium007]

I'd have to pick through the logic in detail to comment on it properly.  At the moment I'd have to print them out and go through it with a pencil and the datasheets open to check - If you redraw the symbols by function rather than physical pinout, one can usually trace he signals without reference to the datasheet, unless the pin names are particularly cryptic, or you have no idea of that chip's function .

One thing to note - I wouldn't use 74HCT logic for anything except the first level-shifting buffer as it has much worse noise immunity than 74HC logic @5V Vcc and logic levels.

OK - I'm redrawing it all now.

[ilium007]

Put the eight load outputs evenly spaced at the top (as they are open drain^*), data in left edge center, data out right edge center, and control inputs bottom edge on the left.  Where to put the power connections is arguable: I'd use left edge near the top for Vcc and the right edge near the bottom for Gnd.

Use the usual convention of a small circle on the outside of the symbol at all inverting inputs (and inverting outputs), and a small triangle (pointing inwards, base on the edge) to indicate edge triggered strobes or clocks.  On its own, that indicates rising edge triggered.  With an external circle for inversion, its falling edge triggered.

Is this acceptable ?

[Ian.M]

Yes. that's a lot easier to follow.   I'd move the name to the middle and add some descriptive text:

TPIC6C595
Open Drain Power SIPO

One may have to look up the pin names, so if you really want to make your schematics self-explanatory, for non-standard symbols, include the pin function tables from the datasheets *somewhere*on the schematic, maybe on an extra page, each with the symbol you have drawn for it.

That parallel load circuit from openmusiclabs.com looks very hacky.  Here's what I was proposing, using 3/4 of a 74HC132.

[ilium007]

I think I get it now ! Would you implement the three extra components vs using one extra digital I/O on the MCU ? Thats assuming my diagram that uses a seperate SS and SH/LD input would even work.

[Ian.M]

The strobe generator circuit leaves you with a clean SPI interface at the cost of three parts and a little board area.  If you are trying to squeeze costs, only populate it on the input board nearest the MCU.   On the other boards a PCB jumper (cut on the first board) would select the pass-through strobe from the first board, and you would not populate the three parts. 

The alternative of a MCU pin to drive the strobe costs you an extra gate on the level shifting buffers and an extra pin on the SPI  expansion board connector.

It all depends on how tight you are for MCU pins and whether or not you want the MCU board's expansion board connectors to be fully interchangeable, and whether you are happy for the first board in each SPI peripheral chain to be special.

Both options need support in the code.  The circuit needs a delay between /SS going low and the start of the SPI transfer to be, say 2us for safety or longer if you increase the time constant.   The MCU pin needs you to pulsed low for a suitable time, returning high before /SS is taken low.

N.B. *DON'T* use non-Schmitt gates with RC delays - you can get some *very* nasty glitches on the output if it doesn't get through the transition region quickly enough.  If you need long(ish) delays, the circuit above can be excessively vulnerable to noise so use a proper monostable chip e.g 74HC221 Dual Monostable (non-retriggerable).

[ilium007]

I've just grabbed a 74HC132 to do some testing with. I like the idea of making a 'standard' SPI interface so that the board connectors can be used with 'standard' SPI header connections. I'd rather all boards be identical so will just populate the parts on each board.

[ilium007]

This mess is a working input shift register board prototype. In there I’ve got 2 x 74HC125 (all I had and this is 5v) emulating the buffer on the MCU board and a buffer on the input board, the 74HC132 / RC circuit doing the SS -> SH/LD trickery and 2 x 74HC165’s cascaded for 16bits of input. I have verified in a serial console that the button presses are detected and sent out on the MISO line.



I just need to work out where the pull-ups / pull downs need to go - I’m not sure if they go on the MCU board SPI output headers or on the output headers on each expansion board (assuming the latter).

Thanks for all your help so far ! I think I’m ready to start designing boards !

[Ian.M]

Only the MCU board level shifting buffers can tristate so only their outputs need pullups or pulldowns.   The only expansion board pin you have to worry about is Data_In on the input board as you need to jumper it to ground on the far end board of the chain.  Make sure its next to a ground pin on the inter-board connector so that's easy to do.

[ilium007]

Only the MCU board level shifting buffers can tristate so only their outputs need pullups or pulldowns.   The only expansion board pin you have to worry about is Data_In on the input board as you need to jumper it to ground on the far end board of the chain.  Make sure its next to a ground pin on the inter-board connector so that's easy to do.

I'm assuming thats the MOSI pin on the input board chain ? Why does the cascaded MOSI need to go to GND ?

[Ian.M]

Because otherwise the far end  board's Data_In is flapping in the breeze, and floating CMOS inputs are a *BAD* *THING*.    The input boards don't use MOSI at all and you may not even connect that pin unless you decide to wire it straight through so you can mix input and output boards in the same daisychain, e.g. to scan a key matrix, (although if you do that in a long chain, beware of timing skew between MISO or MOSI and SCLK).

Have you considered what input protection circuit to use for the input board's parallel input pins?   While 'raw' CMOS logic level inputs can be appropriate in the control panel they would be very risky on the layout.  You'll probably want 12V inout levels for the layout.