Digital signal overshoot 1.8V

[rakeshm55]

Hi,
I am working on LVCMOS 1.8V digital logic.... My clock signal has a rise time of 2.5ns..... I observe a 11% overshoot while probing....
clock frequency is 1MHz....

I have already place a 33ohms series resistor.... Please let me know whether this amount of overshoot is ok....What is the tolerable limit for overshoot??.... How to know this??....

Please advice...

[John_ITIC]

Yes, it is ok. Inputs normally have protection diodes, which limits overshoot to 0.7V over the power rail. The datasheet for your receiver should state the maximum input voltage. 11% is actually very low overshoot. Many designs, which are completely unterminated, can have overshoot of several volts!

[ve7xen]

Also a very good chance the overshoot is an artifact of your probing...