Discrete frequency-to-voltage converter, linear to 100+ KHz

[DrGonzoDK]

Edited with new linearity test of the circuit, as well as a computer drawing of the circuit instead of my pen-paper abomination: see below

So, I recently designed a prototype board - which is an entirely different story; basically I was tired of prototype boards being either very expensive ($10+ a pop) or very, very poor. So I got the first delivery - the family of THT boards - and thought it would be cool to make some demo circuits with them.

The first circuit is a frequency/voltage converter, which outputs a voltage proportional to the input frequency (1V/10KHz, but is settable). Basically, the input is converted to a square wave, then differentiated through a very-high frequency high pass filter. The positive-going pulses (i.e. the square wave sloping upwards) is then accumulated into a capacitor, which is buffered and output to a separate holding stage, and finally conveyed to the output stage. Therefore, the concept is a transfer of charges. The two first capacitor sections have clocked emptying-to-ground through nMOSFETs, and the last section (the "hold" capacitor) gets set in a very short burst of transfer from the 2nd cap (<10µs), by again high-pass filtering its clock to ensure a very short pulse duration.

Finally, the content of the hold capacitors (two Mylar caps in parallel) is amplified to provide the desired output level. A practical measure is 1V/10KHz, but can also be set at 10mV/KHz or similar.
The circuit - See full resolution


 Obviously, you should consider the voltage rails - the LMC6482, which is the buffer/amplifier dual opamp due to its RRI/O capabilities and low offset voltage, can only handle a relatively limited supply voltage range.

Anyway - I've tested it from 10Hz to 120KHz, and it has remained fully linear over this entire span! So, as far as I am concerned, this is a success - linearity over more than 4 decades/orders of magnitude!

And for those board fanatics - the actual prototype board,
The board - See full resolution


EDIT: Linearity measurement, 0 to 200 KHz - including the optional RC filter from the schematic with R=5K6, C=4.7µF


Input is taken from a BNC plug - output on a pair of leads (single-ended output plus Gnd). Apart from the actual F/V converter, the board also has a discrete LDO regulator (for the 3.3V rail) not included in the schematic. This uses a TS27L2 op amp and a TIP32 high-gain PNP power transistor.

Anyway - feedback is more than welcome, both on this circuit and the actual prototype board. The prototype board has two sections that are similar to solderless breadboards - that's why the DIP chip section of the board is quite neat compared to the freeform stuff underneath. Additionally, there are three global buses (two interleaved on the sides, and one in the middle), that helps reduce clutter somewhat. In this case, the outer two buses are CLK and -CLK and the central bus is just GND for convenience.

[DrGonzoDK]

Also - a few details that may be interesting/relevant -

Clock - frequency etc.
The clock frequency is 150Hz, 95% positive duty cycle, generated with the LM555.
The inverted clock (–CLK) is generated with the comparator, with CLK being fed into an inverting input.

LDO details
There is, at functional load, less than 100µV of ripple in the output. The pass PNP transistor is bypassed with a 15µF Tantalum cap on its output (collector), and has a 2K7 resistor to ground to provide a basic load for stability. The controlling op amp, TS27L2, is quite slow (~100KHz GBWP), but is a dual CMOS part.
The front end/voltage reference is a LM385Z-1.2 (1.2V band gap reference). The first half of the TS27L2 amplifies this to 3.33V, which is then used in the LDO control feedback loop of the second op amp. Thus, the control loop operates at unity gain.

Reading with a µC
When CLK goes high, the output can be read at the output terminal. This can be detected by any microcontroller, and the board can therefore be used as part of a ADC/DAC (with the value being represented by frequency - a rare and somewhat old type of D/A interfacing)

Increasing the clock
If the clock is increased, the size of caps Cacc and Ccm should be decreased. Otherwise, the period peak voltage will be so low to make the offset voltage of the op amp, as well as noise, a considerable source of inaccuracy.

The input - protection & conditioning
To avoid the input going below Gnd (which interferes with the functioning of the LM339 quad comparator) as well as avoid excursions above Vcc, the input is protected first by a Zener diode shunt (DZ1), which caps the positive voltage to about 4.2V. Additionally, this Zener caps the negative cycle of the waveform to -800mV.

The following signal diode, D1 (1N4148) caps the negative excursion to about ~-30mV (which is safe with the LM339, which can handle below-Gnd voltages of down to -300mV), and reduces the positive peak to about 3.4V. At this point, the input waveform is converted into a rectangular/pulse wave by the comparator, to ensure a uniform slope rate to the differentiation filter. A rather beefy 520 ohm pullup to +3.3V ensures that the 9.1Kohm Rdiff does not reduce the signal peak voltage by much.

Schottky diodes?
Generally, the silicon signal diodes (1N4148s) - D1 and D2 - should not be replaced by Schottky diodes, especially D2. This is because of the generally higher leakage current of the Schottky diodes, which will cause charge to leak from Cacc at a much higher rate than the pn-junction diodes used in the circuit.

Pulse width and linearity
The pulse width of the input does not affect the result or linearity. Even with a 99/1 duty cycle at 100KHz, the output is no different from a 50/50 duty cycle square wave.

A tiny overlay

Just to show which blocks are which... (Click for full res)

[T3sl4co1l]

Three JFETs?  Rather old fashioned.

Tim

[DrGonzoDK]

Three JFETs?  Rather old fashioned.

Tim

I think you'll find those are nMOSFETs - as drawn in the diagram, the gate is spaced from the channel (and the current "arrow" is on the source, no directional arrow at the gate as a JFET would have). But yeah, drawing the bulk portion is a hassle, so I use the bulkless symbol. Sorry for the confusion.

The BS170 is, by the way, similar to the 2N7000, for reference.

EDIT:
Enh. NMOS


nJFET

[danadak]

An interesting article on F/V from Pease, might be of interest.


http://www.electronicdesign.com/digital-ics/whats-all-frequency-voltage-converter-stuff-anyhow



Also his note on capacitors -


https://www.edn.com/electronics-blogs/anablog/4310008/Bob-Pease-on-capacitor-leakage


http://www.electronicdesign.com/analog/whats-all-capacitor-leakage-stuff-anyhow



Regards, Dana.

[DrGonzoDK]

An interesting article on F/V from Pease, might be of interest.


http://www.electronicdesign.com/digital-ics/whats-all-frequency-voltage-converter-stuff-anyhow



Also his note on capacitors -


https://www.edn.com/electronics-blogs/anablog/4310008/Bob-Pease-on-capacitor-leakage


http://www.electronicdesign.com/analog/whats-all-capacitor-leakage-stuff-anyhow



Regards, Dana.

Yeah! That /is/ a good article. I actually thought of this after remembering reading the V/F (the other way round indeed) article he wrote in his ED column.

There are similarities and differences. Leakage is also a lesser problem, since the main storage capacitors are much larger than in his circuit. The two 2.2µF are general purpose low-leakage capacitors in this case; the final hold stage uses metalized film caps. Mylar is the cheap option; styroflex is the preferred option for the best results.

In any case, I cannot measure any droop in the voltage, neither in the output hold capacitors or in the front or intermediate capacitors. Incidentally, I'd be somewhat more worried about the leakage current of the MOSFETs. And leakage is the very reason why Schottky diodes wouldn't work well for D1 and D2.

While I am sure that Pease's circuit is fantastically precise, I do prefer the single-supply nature of this. And I think it benefits from slightly more modern op amps than the µA741 ;-)

Anyhow, thanks for making me remember that column. I love his writing!

[Zero999]

Hardly discrete. I was thinking of lots of BJTs and FETs.

How about using the 74HC123? All that's needed is the pulse setting to the correct length, then you have PWM on the output, proportional to the input frequency, which can be filtered to provide a DC voltage.

[DrGonzoDK]

Hardly discrete. I was thinking of lots of BJTs and FETs.

How about using the 74HC123? All that's needed is the pulse setting to the correct length, then you have PWM on the output, proportional to the input frequency, which can be filtered to provide a DC voltage.

Well, I was thinking of doing the comparator discretely. But, in this case, since it was Also a demo of the Protoboard’s practicality with DIPs, that never took off. I do have a 3-PNP, 2-NPN, 1-NMOS discrete comparator design (good to say 2MHz with jellybean 2N3904/6 and BS170s) waiting to be built. Maybe I’ll build it on a tiny board and drop it in instead of the 339... a fun idea, but I digress!

I suppose it is discrete in that each IC is used as a simple function -  but yeah, it’s somewhere in between.

I am a bit leery about the filtered-PWM. When has the filter converged to the correct value? How many RC (or RLC) time constants?

That’s why this circuit holds the output of each accumulation cycle - the output is near-perfectly constant between CLK ticks. Sure, if your signal changes frequency often, you’ll end up with an intermediate value, but at least you know how often your results are ready.

I like the idea though!

/D.

[Yansi]

Regarding the schematic from #1 post: I don't think the input series resistor followed by a shunt zener is helping the linearity here very much.

[DrGonzoDK]

Regarding the schematic from #1 post: I don't think the input series resistor followed by a shunt zener is helping the linearity here very much.

In what respect? It is part of input protection, and it is more than fast enough for the range this was made for. The waveform gets conditioned by the comparator; the Zener only acts as input clamping.

The linearity is as measured - less than .5% deviation from 200Hz to 120KHz. I will measure it with better instruments than was immediately than was available!

Anyway - please elaborate!

[Yansi]

In that respect that if the zener voltage becomes even slightly close to the control voltage, the current flowing through the input resistor will give you an error.

I'd suggest using a matched pair of diodes (BAV99 for example) as a protection for precision analog instrumentation.

[danadak]

Not to complicate things but another approach would be to
use PSOC, use its resources to implement a F cntr, and then
pass that onto a PWM DAC. Advantage virtually all onboard
except PWM filter.

With standard components 16 bits, with Verilog could extend
that much higher. Accuracy dependent on External Xtal, and
bit depth of PWM, and the Power supply. With 20 bit A/D that
could be used to remove some of the power supply in accuracy,
limited to onboard ref of +/- .1%.


Regards, Dana.

[DrGonzoDK]

In that respect that if the zener voltage becomes even slightly close to the control voltage, the current flowing through the input resistor will give you an error.

I'd suggest using a matched pair of diodes (BAV99 for example) as a protection for precision analog instrumentation.

As in the voltage at the negative terminal of the comparator? That is always less (max 3.3V) than the Zener voltage (4.3).

I would expect the term control voltage in a V-to-F, not an F-to-V (which this circuit is), so excuse my confusion!

[Yansi]

Ok, my bad then. I thought the input is analog input.  I would still question the use of D1 though! Is it in line with the comparator's bias current direction? If not, the diode is wrong and should not be there. (shouldn't be there anyway, as the zener already acts as a negative voltage protection!)

[DrGonzoDK]

Ok, my bad then. I thought the input is analog input.  I would still question the use of D1 though! Is it in line with the comparator's bias current direction? If not, the diode is wrong and should not be there. (shouldn't be there anyway, as the zener already acts as a negative voltage protection!)

It is. Also, the Zener does not protect enough. As specified in the post, it will allow about -800mV through.

-300mV below the negative rail, and the LM339 acts very funny. Hence, the dual protection. Also, I’ll post some test waveforms tomorrow to elaborate this a bit.

The Zener protects against overvoltage, D1 against reverse biasing the LM339 input, either of which will cause faulty operation of the comparator due to limited input protection inside the IC.

To quote myself -

To avoid the input going below Gnd (which interferes with the functioning of the LM339 quad comparator) as well as avoid excursions above Vcc, the input is protected first by a Zener diode shunt (DZ1), which caps the positive voltage to about 4.2V. Additionally, this Zener caps the negative cycle of the waveform to -800mV.

The following signal diode, D1 (1N4148) caps the negative excursion to about ~-30mV (which is safe with the LM339, which can handle below-Gnd voltages of down to -300mV), and reduces the positive peak to about 3.4V.

Also, there is a 10k resustor to ground after D1 missing from that drawing - that may have confused you! Damn, I’ll draw that in!

[Yansi]

If the D1 blocks the bias current of the comparator (which in this case does, as the 393 has a PNP input stage), it will certainly act weird. D1 wrong and should not be there. Or just fix it adding a 100k res. down to ground right from the noninverting input of the comparator.

Remeber that opamps (and comparators too!) should always have a dc path to establish a correct biasing. The diode there is same as connecting a cap directly to opamps input. That won't work as expected either.

The diode also makes the comparator unable to work with small voltages.

I think the zener does protect well enough. The comaparator input already provides a diode junction against ground, while the input resistor providing current limiting when negative voltage applied. 

[David Hess]

A simple charge pumped frequency to voltage converter using a precision CMOS switch can get 20,000 counts of linearity so the bar is pretty high for more complex designs.  This is better than the LTC6482's common mode rejection will support; they are pretty horrible operational amplifiers but that applies to practically all rail-to-rail in designs.  That single diode in the charge pump and the saturation of the LM339 are going to clobber the temperature coefficient if not compensated.

National and I think Burr-Brown had some application notes which discussed designs which use sample and holds for low output ripple and fast settling time.

[T3sl4co1l]

I think you'll find those are nMOSFETs - as drawn in the diagram, the gate is spaced from the channel (and the current "arrow" is on the source, no directional arrow at the gate as a JFET would have). But yeah, drawing the bulk portion is a hassle, so I use the bulkless symbol. Sorry for the confusion.

Oh, you used the bad symbol. No wonder it looked wrong at a glance.

Tim

[DrGonzoDK]

I think you'll find those are nMOSFETs - as drawn in the diagram, the gate is spaced from the channel (and the current "arrow" is on the source, no directional arrow at the gate as a JFET would have). But yeah, drawing the bulk portion is a hassle, so I use the bulkless symbol. Sorry for the confusion.

Oh, you used the bad symbol. No wonder it looked wrong at a glance.

Tim

It may be bad, but it's certainly used aplenty - but yeah, if you're used to the substrate being there and shorted to source, then it looks wrong I suppose...

[DrGonzoDK]

If the D1 blocks the bias current of the comparator (which in this case does, as the 393 has a PNP input stage), it will certainly act weird. D1 wrong and should not be there. Or just fix it adding a 100k res. down to ground right from the noninverting input of the comparator.

Remeber that opamps (and comparators too!) should always have a dc path to establish a correct biasing. The diode there is same as connecting a cap directly to opamps input. That won't work as expected either.

The diode also makes the comparator unable to work with small voltages.

I think the zener does protect well enough. The comaparator input already provides a diode junction against ground, while the input resistor providing current limiting when negative voltage applied.

As I wrote in the earlier post, the drawing is missing a 10K resistor to ground after D1. So we are in perfect agreement  I've updated the schematic drawing for good measure, so that this diode (Rdl) is included. And yes, the input requires a certain minimal voltage swing - but that is a fair enough prerequisite that is not unique to this design - similar to that of Bob Pease listed earlier

And here are some waveforms. The input is a 10Vpp 10KHz sine wave with no DC offset (i.e. a swing from +5 to -5V).

After the Zener diode (notice Vmin being ~-800mV)


After D1 (at the junction of D1, 10K to Gnd, and + input of LM339) - notice Vmin now is -80mV, which is OK for the '339. Also a voltage drop of ~500mV.


After comparator, with pullup to +3.33V (closer to 3.45 in this case, but, ah)


Also - re the LM339. Even with current limiting resistors, there is no reverse biasing protection, and even a small amount of current at a negative voltage will cause all four comparators in the package to behave strangely. It doesn't cause latch-up, but it does cause wrong functioning until the offending voltage is removed. You can try it yourself - even with a 100K limiting resistor, at -800mV.

[DrGonzoDK]

Also, I just measured the response from 0 to 200 KHz, using a standard DDS signal generator-frequency counter. It's within 10ppm of the target frequency, so it is not a big source of error.

As you can see from this graph, the linearity is excellent. The "slope" in the beginning is simple filter response from the LP filter I was experimenting with adding to the output:
Linearity measurement, 0 to 200 KHz - including the optional RC output filter shown on the schematic, with R=5K6, C=4u7


That is one capture. I am currently collecting a large number of captures to CSV, then it's number crunching time. But, as you can see, the response is very linear across the 0-200KHz spectrum. You can see the beginning of flattening of the response up at the top. And that is why I am not claiming linearity above around 100KHz.

The upper frequency response can be linearized by decreasing the size of the differentiating capacitor (Cdiff) - but at the cost of additional noise and gain requirements on the LMC6482. So that is a trade-off.

[ELS122]

Edited with new linearity test of the circuit, as well as a computer drawing of the circuit instead of my pen-paper abomination: see below

So, I recently designed a prototype board - which is an entirely different story; basically I was tired of prototype boards being either very expensive ($10+ a pop) or very, very poor. So I got the first delivery - the family of THT boards - and thought it would be cool to make some demo circuits with them.

The first circuit is a frequency/voltage converter, which outputs a voltage proportional to the input frequency (1V/10KHz, but is settable). Basically, the input is converted to a square wave, then differentiated through a very-high frequency high pass filter. The positive-going pulses (i.e. the square wave sloping upwards) is then accumulated into a capacitor, which is buffered and output to a separate holding stage, and finally conveyed to the output stage. Therefore, the concept is a transfer of charges. The two first capacitor sections have clocked emptying-to-ground through nMOSFETs, and the last section (the "hold" capacitor) gets set in a very short burst of transfer from the 2nd cap (<10µs), by again high-pass filtering its clock to ensure a very short pulse duration.

Finally, the content of the hold capacitors (two Mylar caps in parallel) is amplified to provide the desired output level. A practical measure is 1V/10KHz, but can also be set at 10mV/KHz or similar.
The circuit - See full resolution


 Obviously, you should consider the voltage rails - the LMC6482, which is the buffer/amplifier dual opamp due to its RRI/O capabilities and low offset voltage, can only handle a relatively limited supply voltage range.

Anyway - I've tested it from 10Hz to 120KHz, and it has remained fully linear over this entire span! So, as far as I am concerned, this is a success - linearity over more than 4 decades/orders of magnitude!

And for those board fanatics - the actual prototype board,
The board - See full resolution


EDIT: Linearity measurement, 0 to 200 KHz - including the optional RC filter from the schematic with R=5K6, C=4.7µF


Input is taken from a BNC plug - output on a pair of leads (single-ended output plus Gnd). Apart from the actual F/V converter, the board also has a discrete LDO regulator (for the 3.3V rail) not included in the schematic. This uses a TS27L2 op amp and a TIP32 high-gain PNP power transistor.

Anyway - feedback is more than welcome, both on this circuit and the actual prototype board. The prototype board has two sections that are similar to solderless breadboards - that's why the DIP chip section of the board is quite neat compared to the freeform stuff underneath. Additionally, there are three global buses (two interleaved on the sides, and one in the middle), that helps reduce clutter somewhat. In this case, the outer two buses are CLK and -CLK and the central bus is just GND for convenience.

Sorry for the bump, but could you please reupload the schematic? the link is down