Also - a few details that may be interesting/relevant -
Clock - frequency etc.The clock frequency is 150Hz, 95% positive duty cycle, generated with the LM555.
The inverted clock (–CLK) is generated with the comparator, with CLK being fed into an inverting input.
LDO detailsThere is, at functional load, less than 100µV of ripple in the output. The pass PNP transistor is bypassed with a 15µF Tantalum cap on its output (collector), and has a 2K7 resistor to ground to provide a basic load for stability. The controlling op amp, TS27L2, is quite slow (~100KHz GBWP), but is a dual CMOS part.
The front end/voltage reference is a LM385Z-1.2 (1.2V band gap reference). The first half of the TS27L2 amplifies this to 3.33V, which is then used in the LDO control feedback loop of the second op amp. Thus, the control loop operates at unity gain.
Reading with a µCWhen CLK goes high, the output can be read at the output terminal. This can be detected by any microcontroller, and the board can therefore be used as part of a ADC/DAC (with the value being represented by frequency - a rare and somewhat old type of D/A interfacing)
Increasing the clockIf the clock is increased, the size of caps Cacc and Ccm should be decreased. Otherwise, the period peak voltage will be so low to make the offset voltage of the op amp, as well as noise, a considerable source of inaccuracy.
The input - protection & conditioningTo avoid the input going below Gnd (which interferes with the functioning of the LM339 quad comparator) as well as avoid excursions above Vcc, the input is protected first by a Zener diode shunt (DZ1), which caps the positive voltage to about 4.2V. Additionally, this Zener caps the negative cycle of the waveform to -800mV.
The following signal diode, D1 (1N4148) caps the negative excursion to about ~-30mV (which is safe with the LM339, which can handle below-Gnd voltages of down to -300mV), and reduces the positive peak to about 3.4V. At this point, the input waveform is converted into a rectangular/pulse wave by the comparator, to ensure a uniform slope rate to the differentiation filter. A rather beefy 520 ohm pullup to +3.3V ensures that the 9.1Kohm Rdiff does not reduce the signal peak voltage by much.
Schottky diodes?Generally, the silicon signal diodes (1N4148s) - D1 and D2 - should not be replaced by Schottky diodes,
especially D2. This is because of the generally higher leakage current of the Schottky diodes, which will cause charge to leak from Cacc at a much higher rate than the pn-junction diodes used in the circuit.
Pulse width and linearityThe pulse width of the input does not affect the result or linearity. Even with a 99/1 duty cycle at 100KHz, the output is no different from a 50/50 duty cycle square wave.
A tiny overlayJust to show which blocks are which... (Click for full res)