EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: FrankBuss on December 26, 2013, 09:53:54 pm
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I got ten A3255-Q48 chips for bitcoin mining cheap from eBay. I guess there are companies who can build an end-user device for it, but would be fun to create my own miner with it. I already found the datasheet:
http://downloads.canaan-creative.com/hardware/A3255/datasheet/ (http://downloads.canaan-creative.com/hardware/A3255/datasheet/)
and a prototype:
http://downloads.canaan-creative.com/hardware/A3255/prototype/ (http://downloads.canaan-creative.com/hardware/A3255/prototype/)
Looks like my old Altium account doesn't work anymore, still waiting until someone at Altium verifies my new registration, then I can download the viewer, because the prototype uses Altium Designer.
But the schematic shouldn't be too difficult, because it is a simple serial protocol for each chip and they can be chained. But looks like there is not much documentation for the project. Is there any other open source project for this chip?
I plan to use Eagle to do my own version. The controller part will be the controller board for my Crazy Cartridge ( http://www.crazycartridge.org (http://www.crazycartridge.org) ). It has a small FPGA, if the serial communication is timing critical and for the 25 MHz clock generation, and a microcontroller with USB (the SRAM on the board might not be needed). This can be connected to any Linux computer, like a Rasperry Pi, where a miner is running and which has a web interface to setup the miner (IIRC there is already a SD card image for the Raspberry Pi for such a system).
One A3255-Q48 chip can do 1 GH/s (@2.05 W / GHash). This will be $0.34 per day, if used in a mining pool, so it is really just for fun, until I can get some next generation ASICs :)
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Looks very interesting, I've been looking into GPU mining some Scrypt currencies, but it's sadly quite unprofitable for me :--
How much did you pay for them?
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I paid EUR 12 per chip, which means maybe I'll get the hardware cost back over the lifetime of the system, if the bitcoin difficulty doesn't rise too fast. But looks like there are some offers for this chip on alibaba.com and aliexpress.com as well, maybe I can even sell some of my devices. There are some old 5 GH/s Butterfly Jalapeno miners with EUR 200 and higher bids at eBay :palm:
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Ah screw it, bitcoin's not going to earn you anything whichever way you do it. It's a shame, because if it was worth it, it could've been quite fun.
I'd say just try and sell what you've got!
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Yeah, I don't expect to make a profit. By the time when my hardware is finished, prices might be too low for the old competitor miners to sell my hardware. But could be still a fun project. And I will learn anything, down to the metal with the hashing chips, and all the layers in between, up to the mining software.
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Yeah, I don't expect to make a profit. By the time when my hardware is finished, prices might be too low for the old competitor miners to sell my hardware. But could be still a fun project. And I will learn anything, down to the metal with the hashing chips, and all the layers in between, up to the mining software.
Unfortunately for you, you are facing the dual hurdles of time lost in design as you've mentioned, and also the costs of local power. With energiewende I don't think your situation will improve in the near future unless you can steal power from your neighbours >:D.
I have been looking at bitcoin because the theoretical computer sciencey aspect as well as the social aspect fascinates. One thing that mystifies, why hasn't a semi-manufacturer quietly stepped in with their own chips and started a mining operation themselves. They can afford the development costs and they could locate the installation to someplace cold with fast internet and cheap hydro, like Norway or Quebec. Or maybe one of them is already doing it, in which case all the little miners are in a truly hopeless lost cause.
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There is a company mining in Iceland:
http://dealbook.nytimes.com/2013/12/21/into-the-bitcoin-mines/ (http://dealbook.nytimes.com/2013/12/21/into-the-bitcoin-mines/)
Their plans are not profitable for the end customers, but I guess they do get quite some money, and unlike mining on your own, no bitcoin difficulty or exchange rate risk >:D
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The Jalapeno 5.5 GH/s miner (http://cgi.ebay.de/ws/eBayISAPI.dll?ViewItem&item=161180252162) was sold for EUR 436 :-DD
Still no answer so far from Altium regarding my registration, I guess all people are on holiday. But meanwhile I found a link to the viewer (http://downloads.altium.com/altiumdesigner/AltiumDesignerViewerBuild9.3.0.19153.zip). Silly to block it with a login-wall, the viewer is free anyway.
The schematic is as simple as expected. The hashunit is one PCB, which needs only four data lines (and the power lines) to control as many Avalon chips as I want. The two control lines are chained for all chips, and the two report lines are all connected together (there are two pullups, so it is an open collector signal). Looks like the power supply with a TPS40193 and some MOSFETs is on another PCB. I'll integrate this all on one PCB.
For controlling it, one FPGA should be sufficient, which I then connect to a Raspberry Pi.
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Yeah, I don't expect to make a profit. By the time when my hardware is finished, prices might be too low for the old competitor miners to sell my hardware. But could be still a fun project. And I will learn anything, down to the metal with the hashing chips, and all the layers in between, up to the mining software.
I'd love to see what the final design looks like, I've always been interested in buying the chips individually and putting a miner together. Please do post it if you get it finished :-+
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I got the chips and soldered one on a breakout board. First I fried one by trying this with a heatgun, but manually soldering all pins of the QFN chip worked (it is possible with a microscope to solder the pins at the sides of the QFN chip). I even drilled a hole in the breakout board to solder the big ground pad on the underside. But for the final PCB it should be no problem with my reflow oven and a solder paste stencil. This is the test setup, with a DE0 nano and a RS232 serial port adapter:
(http://i.imgur.com/SLYIY6y.jpg)
When powering up the chip it looks like it starts in highest speed configuration, with 2A on the 0.9V supply line. There is a debug clock output for the core clock, which says 10MHz. The datasheet says max clock is 1GHz, so I guess the debug output is divided by 100.
I can configure the PLL of the Avalon chip to 625kHz (by judging from the debug output port, for me the datasheet is not very clear and I expected half of it as the core frequency) and then it draws 160mA. This looks linear: when configuring it to 1.25MHz I can measure 300mA. The chip is cold at 160mA, good for testing. Of course, it gets really hot at 2A without a heat sink.
The communication interface uses two lines: config_p and config_n. There is an "idle" state, when config_p and config_n are both high. Sending a bit starts by setting both lines to 0, then waiting for 125ns, then setting config_p to high, if you want to send a 1 bit, or setting config_n to high, if you want to send a 0 bit, and then waiting another 125ns. There was no detailed timing description in the datasheet, but looks like there is no timeout, so after this cycle you can wait as long as you want, and then send a 1 or 0 bit again, or go to idle. Unlike other serial protocols, this is easy to read on a scope.
Chips can be chained. The datasheet didn't explain it in detail (it is still version 0.5, and I guess written in a rush because of the competitors and exponentially rising bitcoin difficulty per day), so I tested it: My FPGA has a receive module for the report_p/report_n lines (I guess the same protocol) and I connected it to the config_p/n chain output instead. When I send 18 words (32 bit per word), all words are forwarded to the output. But when I send more words, one word less is forwarded. The scope shows that it delays one word after the 18th word. This makes sense, because the first words are the same for all chips, and then each chip is initialized with a different nounce start. This first chip uses the last sent nounce, and doesn't forward it, the second chip uses the next to last nounce and so on.
Next step will be to create some test data for the chip and let it calculate the nounce for it. The datasheet is not very clear about the data format. There is some pseudo code how to initialize some words, but even the length of the expected data is not documented (but I expect 16 words, because of the 18 words from the chaining experiments, minus two words for the clock config).
I created a Github project for the current Quartus VHDL project, Eagle files and Python scripts with the communication test:
https://github.com/FrankBuss/gandalf-minder (https://github.com/FrankBuss/gandalf-minder)
I chose the name Gandalf, because he knows how to get something from Avalon :)
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Awesome work, it'd be great to see it mining :-+ Which board are you using to communicate with it?
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It is a DE0-Nano: http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593 (http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593)
For the final PCB I will replace it with a smaller (and cheaper) Lattice MachXO2 FPGA, and a Raspberry Pi will communicate with it over the serial port instead of a PC.
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I see, well good luck! Keep us updated :)
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Hello Frank,
I already built a mining system with FPGA board DE0-nano and Raspberry Pi as
host just for fun. It is running stable for a month with ca. 10MH/s.
I found this tread while searching for purchasing the avalon chips to make my own avalon board.
So i'm very interested in your project and would like to work with you to develop such a mining
system. I cannot program FPGAs but i can build a hardware proffessionally (with altium).
Maybe we can help each other... :-+
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Ok, some progress, the chip generates a nonce. But it is not the expected nonce, because I guess something is still wrong with my calculations for the hash initialization, but I wrote an eMail to the support at avalon-asic.com, hopefully they can explain it in more detail.
The same nonce is generated each 68.7 seconds, which means it is working at 2^32/68.7=62.5 MH/s. I was wrong in my last posting, the debug clock output was 625 kHz, so the core is 62.5 MHz. Which means the chip can do one hash test in one clock cycle and which allows it to run at 1 GH/s for the maximum allowed frequency. All source code is in the github repository.
@GND: Sounds like a good idea. I'm good with FPGAs, but only mediocre with PCB design. Of course, if you have already Altium, you could simply use the project here: http://downloads.canaan-creative.com/hardware/A3255/prototype/ (http://downloads.canaan-creative.com/hardware/A3255/prototype/) at least for the board with the ASICs. I will try to do it in Eagle anyway, but would be useful if you could review it before I send it to the PCB manufacturer and I can help with the FPGA programming.
@mobicek: not bad for low quantities. But if it really takes off, there are cheaper offers for larger quantities. The http://avalon-asics.com (http://avalon-asics.com) shop even claims it is in-stock and they don't do pre-orders anymore (says the FAQ), but would be really expensive, because of the minimum quantity of 2,500 pieces.
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Pretty sure you don't mean nonce.
Moderator removed reference to deleted post.
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Pretty sure you don't mean nonce.
Sorry, English is not my native language, looks like it has more than one meaning, and some awful slang meaning, but I mean this: https://en.bitcoin.it/wiki/Nonce
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Pretty sure you don't mean nonce.
Yes, he does; it has a slightly different meaning in the Bitcoin world than in more general crypto, AFAIK, but it is an established term of art in the latter world. Does rather make a Brit blink at first, though!
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Ok, some progress, the chip generates a nonce. But it is not the expected nonce, because I guess something is still wrong with my calculations for the hash initialization, but I wrote an eMail to the support at avalon-asic.com, hopefully they can explain it in more detail.
Hi, I'm also developing system based on A3255-Q48, with 32 chips per board, from scratch schematics, with goal of maximum performance, thus using individual config for each chip (to set max. clock for each chip), and using separate power supply for each chip and Altera FPGA (Cyclone-II) controller in PQFP package, since my experience with BGA soldering quality is not too positive. Using FTDI 245R for USB I/O, and designed for ATX-24 power supply connector, with fan control circuits and temperature sensor included, mini-ITX formfactor.
PCB design and FPGA configuration don't stress me too much, but sketchy docs for A3255 do...
Same as you, I can't figure out the exact data format that goes to the chip - the "midstate" part in particular. Were you able to get further with deducing that data format or some word from Avalon tech support?
Now, let me try to sum it up, what's known about that data format at this point.
When I send 18 words (32 bit per word), all words are forwarded to the output. But when I send more words, one word less is forwarded.
Per datasheet, words are:
# clock
w[0] <= clock setup
w[1] <= clock setup reserved (0x0)
# hash data
w[2]..w[i-1] <= ? "data" ?
w[i] <= a1
w[i+1] <= a0
w[i+2]<= e2
w[i+3]<= e1
w[i+4]<= e0
w[i+5]..w[j-1] <= ? "midstate" ?
w[j] <= a2
# nonce
w[j+1] <= nonce
So, of 18 words you observed, we have only 8 (!) documented to some extent, and 10 words are unknown (assuming that 18 words that go through do not include the nonce word)
From discussion at bitcoin.org forum: (https://bitcointalk.org/index.php?topic=218193.80):
LSB (first bit, byte, word) [8B - Clock Config] , [12B - data], [4B a1],[4B a0],[4B e2],[4B e1],[4B e0], [32B midstate], [4B a2], [4B nonce - 0x00000000 - 1 Avalon chip]
so, there they have 20 words! And, supposedly that worked after all, but I'm not quite certain it's the same chip - A3255, seems it's the earlier one.
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No answer from the Avalon support so far. Maybe they are too busy with spending their money they got from all the crazy miners :)
I assumed the "midstate" is what a "getwork" response sends. And that's what my script should calculate. To verify: Start the Bitcoin Qt client, then a command prompt, "cd" to "C:\Program Files (x86)\Bitcoin\daemon" (or wherever it is on Mac or Linux), then start "bitcoind getwork". You should get something like this:
{
"midstate" : "c878d422538a82a39135ba83195e80b3d392ca399d80b567e7ea971962f56533",
"data" : "0000000262a0a8264e478e0e8e91444300e3f55705de236e6a6b34ca000000010000000001b90de5e2895cc42e0390996589417cb02b9e0636aa5297bb98469c8d9fa50152d39feb1902666600000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000",
"hash1" : "00000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000010000",
"target" : "0000000000000000000000000000000000000000000066660200000000000000"
}
Then start a Python 3.3 shell, load my script https://github.com/FrankBuss/gandalf-minder/blob/master/scripts/avalonHashData.py and you can try it like this:
from avalonHashData import calculateAvalonHashData
from binascii import hexlify
datastr="0000000262a0a8264e478e0e8e91444300e3f55705de236e6a6b34ca000000010000000001b90de5e2895cc42e0390996589417cb02b9e0636aa5297bb98469c8d9fa50152d39feb1902666600000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000"
for word in calculateAvalonHashData(datastr): print("%08x" % word)
It shows this output:
01a59f8d
eb9fd352
66660219
a009b2fb
fe08884d
a7867d3e
c2a21279
9ac7e2a2
22d478c8
a3828a53
83ba3591
b3805e19
39ca92d3
67b5809d
1997eae7
3365f562
2f3cf39b
As you can see, there are the midstate words (the getwork-data is in little endian, so the last midstate word 0x3365f562 are encoded as 62f56533 in the midstate array).
I guess the "data" in the A3255 datasheet are the first words of the second SHA256 block. Mining means hashing this block:
bitcoin block struct:
int nVersion;
uint256 hashPrevBlock;
uint256 hashMerkleRoot;
unsigned int nTime;
unsigned int nBits;
unsigned int nNonce;
and testing it for all nNonce, so that the resulting hash has a high number of leading zeros, better than specified in the "target". SHA256 hashes the input in 512 bit chunks = 64 bytes. For the first chunk that would be 4 bytes for the version, 32 bytes for hashPrevBlcok and 28 bytes of hashMerkleRoot. This chunk doesn't change, which is the reason you have to calculate it only once for testing all nNonce values. The SHA256 state for this chunk is called "midstate".
The second chunk is filled with zeros, so only 4 bytes of hashMerkleRoot, 4 bytes for nTime and 4 bytes for nBits needs to be transfered. I guess this is the "data" part of the datasheet. Would make sense, because it would fit 3 words length. Now the chip can use the "midstate" of the first chunk to initialize the SHA256 state, and then calculate the hash for the second chunk for all nNonce values.
Well, at least that's what I think how it works. I tried any combinations of little/big endian for the data (because bitcoin tends to change this at will at various steps), but no luck. :-//
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Hi there,
maybe it is possible to port the mining design from DE0-nano to the avalon chips...
That can do someone who is familiar with VHDL design - i don't know about how
simple or difficult it is to port.
I already built a mining system with FPGA board DE0-nano and Raspberry Pi as
host just for fun. It is running stable for a month with ca. 10MH/s.
I followed this guide for FPGA mining (open source) on DE0-nano and it works.
http://www.designspark.com/blog/bitcoin-mining-with-a-raspberry-pi-and-de0-nano (http://www.designspark.com/blog/bitcoin-mining-with-a-raspberry-pi-and-de0-nano)
I inserted a correction into this guide to run it with RPi and a mining pool such a BTCguild.
Just notice the comment from sparkerdesign (its me) to make it run with RPi.
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bfgminer (git clone https://github.com/luke-jr/bfgminer.git) code has quite a few references to Avalon, and actual code supporting it. I did not comprehend it all yet (but would be working on it), 'midstate' and 'data' are mentioned here:
./driver-avalon.c:138
static inline void avalon_create_task(struct avalon_task *at,
struct work *work)
{
memcpy(at->midstate, work->midstate, 32);
memcpy(at->data, work->data + 64, 12);
}
at least size of data is clear now (3 words) and midstate confirmed at 8 words.
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Since Bitcoin is based on SHA256, could obsolete Bitcoin ASICs be repurposed for other uses like high speed generation of random numbers?
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BFGminer is mostly a fork of cgminer (there are even some "cg*" function names in the source code, he didn't care to rename it to "BFG*"). The cgminer source code for the avalon driver is more recent:
https://github.com/ckolivas/cgminer/blob/master/driver-avalon.c
Compared to the BFGminer source code, it has some additional #ifdefs for AVALON_A3255, for example for the nonce offset. I wonder if this works, because the datasheet says the offset is 0x180 and not 0xc0. And looks like it doesn't send the A0-A2 and E0-E2 words as mentioned in the datasheet. I wonder how this could work, or maybe the datasheet is wrong? Of course, the miner doesn't send it to directly the ASIC, but it is some USB device in between, maybe this does some more calculations and data conversions.
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Since Bitcoin is based on SHA256, could obsolete Bitcoin ASICs be repurposed for other uses like high speed generation of random numbers?
No, because the only output of the ASIC is the nonce, which generates some leading zeros when SHA256 hashed with some more data. You don't get the hashes itself from the chip.
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shop even claims it is in-stock and they don't do pre-orders anymore (says the FAQ), but would be really expensive, because of the minimum quantity of 2,500 pieces.
If I see it correctly, you can buy a reel for 15 bitcoin, which has the potential to generate the same amount of bitcoin in 22 days. Maybe I should investigate this more closely.
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... The cgminer source code for the avalon driver is more recent:
https://github.com/ckolivas/cgminer/blob/master/driver-avalon.c
Compared to the BFGminer source code, it has some additional #ifdefs for AVALON_A3255, for example for the nonce offset. I wonder if this works, because the datasheet says the offset is 0x180 and not 0xc0. And looks like it doesn't send the A0-A2 and E0-E2 words as mentioned in the datasheet. I wonder how this could work, or maybe the datasheet is wrong? Of course, the miner doesn't send it to directly the ASIC, but it is some USB device in between, maybe this does some more calculations and data conversions.
Thank you for the cgminer ref.
Not sure about the offset, but 0xC0 << 1 is 0x180 i.e. 1 bit shift... Now, in above mentioned thread about A3255 protocol, it's confirmed that:
"Received nonce is shifted about 0xC0"
The reference design schematics has only USB <-> serial port there, connected to FPGA. I hope they are not using FPGA for a0-a2,e0-e2 calculation. but in 15K LEs that could be done of course.
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I got a word from a developer of A3255-q48 based system (link above):
LSB (first bit, byte, word) [8B - Clock Config] , [12B - data], [4B a1],[4B a0],[4B e2],[4B e1],[4B e0], [32B midstate], [4B a2], [4B nonce - 0x00000000 - 1 Avalon chip]
"yes its correct for a3255-q48 each."
"Golden nonce for a3255 is received nonce - 0x180 , tested, work fine for me."
I think he will answer couple more meaningful questions if need be.
I still don't have a prototype board, doing the big board layout, will get to prototype (single chip test) after big one goes to manufacturing. I'm pretty sure A3255-q48 works fine, only have to figure out how :-)
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If I see it correctly, you can buy a reel for 15 bitcoin, which has the potential to generate the same amount of bitcoin in 22 days. Maybe I should investigate this more closely.
By the time you get them and build some hardware that will likely be months or even years. The difficulty is rising fast now.
We need Litecoin ASICs.
Well, years is a bit excessive. I mean the hardware is not complicated, it is basically 4 pins+pwer. Connect all 4 to an FPGA, conenct the FPGA to a serial-USB module, put a (some) POL module on the PCB, manufacture it on a four layer board. As I see, one chip only consumes 3-4W, so cooling with a 25K/W heatsink is easyliy done. I'm not sure about the leadtime of the ASIC, but everything else is doable in 1-2 month. If the FPGA development is concurrently made, you can mine in 2 months.
The bigger problem is that it requires full time commitment, and indeed, you can only mine so much bitcoin before it is not worth it anymore.
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I think he will answer couple more meaningful questions if need be.
This would be helpful. Not much more information so far than what is written in the datasheet. He says he has tested it. A full example would be very useful: "getwork" input, the calculated byte array which were sent to the chip and the returned nonce as a byte array. This would help to bugfix my source code. And with a known working byte array and expected nonce I could test the chip as well, maybe it is just broken.
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This would be helpful. Not much more information so far than what is written in the datasheet. He says he has tested it. A full example would be very useful: "getwork" input, the calculated byte array which were sent to the chip and the returned nonce as a byte array. This would help to bugfix my source code. And with a known working byte array and expected nonce I could test the chip as well, maybe it is just broken.
It seems that it would be better to present that getwork input, code that transforms it into the byte array sent, and then the byte array received with code that shows why it's incorrect and ask which stage input-output is incorrect.
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Ok, I found the problem, the new code is in the Github repository. The problem was that the sample code in the datasheet to calculate a0-a2 and e0-e2 needed the second SHA256 chunk, which of course you can only calculate, if you have already calculated the first chunk, which is needed for the midstate anyway. So this is a test vector, to check if an Avalon chip works, clock settings included, for 0.3 A:
22600017, 00000000, f1fc122b, c7f5d74d, f2b9441a, 2eb9cc59, ddc34729, db8ae7e1, 6cb85659, 9a431c20, 9524c593, 05c56713, 16e669ba, 2d2810a0, 07e86e37, 2f56a9da, cd5bce69, 7a78da2d, 41bda849, 42a14495
Each 32 bit word is sent lowest byte and lowest bit first. This was calculated from the following getwork "data":
00000001ab02cd818b9e567ee21793cddef299feb29ad444a41b85b8000008a300000000c2b620e3758dfcff8bdb2304ae42b91e1e950e71aff797d7b09288fc2b12fcf14dd7f5c71a44b9f200000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000
The Avalon chip should respond immediately with 0x42a14815 (and after 3 seconds and 17 seconds with two other values). You have to subtract 0x180 and then do a little-endian/big-endian swap to get the expected right nonce 0x9546A142.
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According to that many ASIC miners are already worthless, incapable of ever breaking even if difficulty continues to rise at the predicted rate.
As mentioned, free electricity makes it profitable.
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This is an interesting project, I've been watching bitcoin since end of 2011, I have a small amount from then. I used a de0-nano and a modified version of this https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner. I recall I had overheat problems and had to tweak the VHDL but it was much more interesting than blinking lights on and off.
Thanks for sharing your work and process.
Maybe you can provide heat for your home from the bitcoin miner and if so it might be not as big of a losing proposition.
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Where do these chips come on this chart?
http://bitcoinwisdom.com/bitcoin/calculator (http://bitcoinwisdom.com/bitcoin/calculator)
A miner with 25 Avalon chips would be like the "BitFury Starter Kit Oct", because of the 1 GH/s for one Avalon chip, but @2W per chip, so change the Watts field to maybe 60, and if you manage to produce it for EUR 170, it would be profitable in just 140 days, according to the table on the bottom right.
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Mining works! I ported the example Python bitcoin miner (https://github.com/bitcoin/bitcoin/blob/master/contrib/pyminer/pyminer.py) to Python 3 and simplified and modified it a bit to use with the Avalon chip. The new source code is in the Github repository. I increased the clock to 250 MHz and added a small heatsink. Then I tried it with a mining pool:
(http://i.imgur.com/e76dIIU.png)
It didn't generate the 0.001 BTC, this was from my CPU mining experiments years ago. At this rate I'll get 0.0001 BTC per day, or 0.05 EUR :)
Next step will be to finish the Eagle schematic, to use more chips in parallel at max. speed with a bigger heatsink and fan. Then maybe enhancing the miner for getblocktemplate, or just implementing a driver for cgminer.
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The latest estimate for change in difficulty is Sept. 2016, so call it a space heater that makes "0.0001 BTC per day, or 0.05 EUR" and Bob's yer uncle.
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According to that many ASIC miners are already worthless, incapable of ever breaking even if difficulty continues to rise at the predicted rate.
As mentioned, free electricity makes it profitable.
Who gets free electricity?
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Who gets free electricity?
Most college dorms and a few apartments do. It's not "free" per se but rather "fixed cost". There are also a few utility plans where electricity is free at night. And of course, those who have alternative energy at home.
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Most college dorms and a few apartments do. It's not "free" per se but rather "fixed cost". There are also a few utility plans where electricity is free at night. And of course, those who have alternative energy at home.
I guess if you draw constantly 2 kW for a modern bitcoin miner, the landlord might not like it and show you some fine print for fair use.
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I guess if you draw constantly 2 kW for a modern bitcoin miner, the landlord might not like it and show you some fine print for fair use.
That's no different than leaving the A/C or heater running. That would indeed be problematic in dorms that generally do not allow such items, so you can't do it on too big of a scale. And if heating is electric (very common in apartments), there would be basically no change in winter time electricity use. Those who live in cold climates and are stuck with electric heat would always benefit from Bitcoin mining. (i.e. the value of the Bitcoins mined "subsidizes" the electricity used.)
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there would be basically no change in winter time electricity use. Those who live in cold climates and are stuck with electric heat would always benefit from Bitcoin mining. (i.e. the value of the Bitcoins mined "subsidizes" the electricity used.)
Heaters work with thermostats, when desired temperature is reached heating is turned off. Computers doing calculations produce more or less the same heat all the time. 2kW in fairly winter insulated house will get toasty really quick.
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Who gets free electricity?
People that ask nicely.
Think geothermal.
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2kW in fairly winter insulated house will get toasty really quick
Open the window? Heat the basement, the greenhouse, pipe it to your neighbor's place (but charge them half of utility rates). Maybe bake bread.
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Heaters work with thermostats, when desired temperature is reached heating is turned off. Computers doing calculations produce more or less the same heat all the time. 2kW in fairly winter insulated house will get toasty really quick.
Apartments usually aren't very well insulated. A single mining unit is going to be 1.5kW or less, since that's the (sustained) limit of a common 15A circuit.
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Ok, back on-topic. I'm planning the schematic. My idea would be to use modules of 10 Avalon chips and one controller board. Each module has its own 0.9V and 3.3V power supply regulator and a 12V Molex connector to connect a standard PC power supply. I think each Avalon module should have a small microcontroller (maybe a PIC) with a SPI interface. So there will be a data connector for each module with CS/MISO/MOSI/CLK for the microcontroller, the 25 MHz clock signal, CONFIG_PI/NI (should do the FPGA on the controller board for exact timing, not the PIC) and the open collector REPORT_NI/PI signals. An Avalon board will have the following components:
- up to 10 Avalon chips
- MCP41HVX1 digital potentiometer to adjust the 0.9V core voltage for overclocking
- TC74 temperature sensor in TO220-5, for mounting on the heatsink
- Molex connector for 12V input
- 0.9V/20A voltage regulator (maybe a bit more ampere for overclocking)
- 3.3V voltage regulator
- microcontroller to read the temperature sensor, control the digital potentiometer, power enable of the core voltage, and controlling the RSTN line of the Avalon chips
The CS is for the SPI interface with the microcontroller, but it will gate the CONFIG_PI/NI signals as well. Then the controller board just needs to provide all signals once, and only different CS signals for each connected Avalon module. I plan to use the LCMXO2-4000HC TQFP 144 FPGA, which has 115 usable IO lines. There are 8 common lines required for all Avalon module (maybe buffered for each board) and 4 lines for a SPI interface to the Raspberry Pi. This means 103 lines are left. Maybe a good idea to leave 3 spare lines, so we have 100 chip selects for up to 100 Avalon modules. This would allow to build a 1000 GH/s bitcoin miner with one controller board and one Raspberry Pi.
With this many chips, the REPORT_N/I signals could be a problem, because the chances are higher, that two chips send reports in parallel. And maybe there could be a problem with 100 open collector connections. Maybe the local microcontroller is fast enough to receive the reports and to send the config data. Then there would be no need for an FPGA on the controller board. The Raspberry Pi would control all Avalon modules with SPI, and chip select could be generated with a few 7490 decade counters, or a smaller CPLD. I think I should try to implement the CONFIG/REPORT protocol for a PIC to test it.
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I think it would be easier to write a 'company' screensaver which performs the calculations in the background. As per Seti At Home and role it out...
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This wouldn't make sense. The average company PC has a low end graphics card, maybe 100 MH/s if you are lucky, for cheap on-board cards or CPU mining maybe 10 MH/s (see https://en.bitcoin.it/wiki/Mining_hardware_comparison ). One Avalon chip with 2 W would be 10 to 100 times faster. And if someone would try to hide it in a screensaver, it would be classified as malware fast.
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Ok, back on-topic. I'm planning the schematic.
You're over my head but I'm enjoying watching along. With 10 avalon chips per module, what's the plan if one chip fails? Will the chip be replaced or the entire module? How easy will it be to swap modules?
Here's my very high-level understanding of your rig so far:
1,000 avalon chips, with 10 chips per module for 100 modules.
Will it be stacked, spread out flat or side-by-side or ?
What about fire supression?
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With 10 avalon chips per module, what's the plan if one chip fails? Will the chip be replaced or the entire module? How easy will it be to swap modules?
Replacing a chip could be difficult, because you have to desolder the QFN48 package, clean it and then solder a new chip. Maybe I should add some jumpers or 0-ohm resistors, then a broken chip could be disconnected easier. And some more non-populated 0-ohm bridges to skip the CONFIG_IN/CONFIG_OUT chain for a broken chip. It should be possible to detect a faulty chip by software, at least the first one in a chain, if multiple are broken.
Here's my very high-level understanding of your rig so far:
1,000 avalon chips, with 10 chips per module for 100 modules.
Will it be stacked, spread out flat or side-by-side or ?
What about fire supression?
Good questions, I have no idea :) I'm a programmer and can do some electronics, but no mechanics. I guess it would end up looking like this:
(https://images.indiegogo.com/file_attachments/245153/files/20131205234255-54e1321abc15ea6e1e0cfd80c17eefe0.jpg)
Meanwhile I've done some more tests. When I run my test setup with 1 GH/s, the report signal has a frequency of 4 MHz. This would be difficult to sample with a microcontroller, especially if I want to do something more in parallel, like measuring the temperature and communicating with the controller board. But I developed a circuit to convert the Avalon REPORT_N/REPORT_P signal to a SPI signal:
(http://i.imgur.com/LoNEyPK.png)
And this is how it looks like with real signals:
(http://i.imgur.com/G5aU8cN.png)
As you can see, the OR_DELAY signal can be used as the SPI clock (configured to sample MOSI at rising edge) and RPT_N_I as MOSI. Two 30 cent chips replaces the whole FPGA! And I tested the configure signals as well: there is no lower limit how slow it can be, so no need for the 125 ns signal generating part of the FPGA either.
This would allow a cheap PIC for each Avalon module. But I think I'll use a more expensive ARM microcontroller with USB (4 EUR instead of 2 EUR). Then I can design the 10 chip Avalon module to run in standalone mode with USB, or connected over SPI to the Raspberry Pi controller board. And the microcontroller can be programmed over USB as well, no need for a programmer, which makes it easier for others to rebuild it.
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Replacing a chip could be difficult, because you have to desolder the QFN48 package, clean it and then solder a new chip.
This would work but wow they are expensive.
http://www.mouser.com/access/?pn=945-IC550-0484-004-G (http://www.mouser.com/access/?pn=945-IC550-0484-004-G)
As you can see, the OR_DELAY signal can be used as the SPI clock (configured to sample MOSI at rising edge) and RPT_N_I as MOSI. Two 30 cent chips replaces the whole FPGA! And I tested the configure signals as well: there is no lower limit how slow it can be, so no need for the 125 ns signal generating part of the FPGA either.
Since I have to look up what MOSI is you can guess I have nothing to say about this.
This would allow a cheap PIC for each Avalon module. But I think I'll use a more expensive ARM microcontroller with USB (4 EUR instead of 2 EUR). Then I can design the 10 chip Avalon module to run in standalone mode with USB, or connected over SPI to the Raspberry Pi controller board. And the microcontroller can be programmed over USB as well, no need for a programmer, which makes it easier for others to rebuild it.
After looking at the pic with all the wires maybe instead of usb go wireless? Bluetooth or wifi? But I'm curious about the ARM microcontroller w/ USB. What part is that?
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Why not bury your server in the permafrost and use a Peltier plate to generate power from the surplus heat from the server? Then, power the fans with it.
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Since I have to look up what MOSI is you can guess I have nothing to say about this.
It's one of the SPI data signals, "Master Out, Slave In."
-a
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This would work but wow they are expensive.
http://www.mouser.com/access/?pn=945-IC550-0484-004-G (http://www.mouser.com/access/?pn=945-IC550-0484-004-G)
Yes, such sockets are expensive. Usually it is used for programming or testing chips. And if I would use it, there would be a problem with the exposed center pad, which has to be soldered for best heat transfer. But could be used for a Avalon chip tester. Maybe a good idea to test all chips before soldering.
After looking at the pic with all the wires maybe instead of usb go wireless? Bluetooth or wifi? But I'm curious about the ARM microcontroller w/ USB. What part is that?
My idea was a LPC11U2X controller, as I used for my Crazy Cartridge (http://crazycartridge.org). But unfortunately the fine print in the datasheet says the maximum SPI clock is 1/12 system clock. For the 4 MHz SPI clock I would need a system clock of 48 MHz. This is exactly the frequency with which it is running, so there would be no safety margin and if I overclock the Avalon, it could fail. And the SPI slave implementation on the LPC chip is not really usable: it needs a CS signal to start the receiving, and max word size is 16 bit. I would need to use another pin as an output pin to simulate CS and I would need to implement some interrupts to read two words.
So back to a PIC. The PIC32MX220F032B looks perfect. The SPI slave implementation allows a SPI clock up to 20 MHz, it can be configured for 32 bit word size and it receives without the need for a CS signal (but which can be enabled). And it is cheap.
I think for the communication from the controller to the Avalon modules I would use a much simpler concept, a chained UART line: The controller board has an UART tx line, connected to RX of the PIC on the first board. The PIC has a TX line, connected to the RX line on the second board etc. and the tx line of the last board connected back to the RX line of the controller board. This would solve the cable mess, and it could be connected to a (TTL) serial port of a PC as well, without any controller board, which could be simply a Raspberry Pi, without any custom PCB.
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And if I would use it, there would be a problem with the exposed center pad, which has to be soldered for best heat transfer. But could be used for a Avalon chip tester. Maybe a good idea to test all chips before soldering.
I didn't think about the center pad, but yes it would be good for pre-solder test.
So back to a PIC. The PIC32MX220F032B looks perfect. The SPI slave implementation allows a SPI clock up to 20 MHz, it can be configured for 32 bit word size and it receives without the need for a CS signal (but which can be enabled). And it is cheap.
I think for the communication from the controller to the Avalon modules I would use a much simpler concept, a chained UART line: The controller board has an UART tx line, connected to RX of the PIC on the first board. The PIC has a TX line, connected to the RX line on the second board etc. and the tx line of the last board connected back to the RX line of the controller board. This would solve the cable mess, and it could be connected to a (TTL) serial port of a PC as well, without any controller board, which could be simply a Raspberry Pi, without any custom PCB.
I have never done any work with a PIC. I'm going to look into that. I need to take the cheapest route though.
Here's my understanding, each Avalon work's on it's own sha256(sha256()) and will return data at a rate distinct from every other Avalon. So the data rates from 1000 Avalons should be expected to be small. Or am I missing something? i.e. the Avalon spends more time working than talking.
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Shouldn't be too expensive. A PICKit 3 programmer clone for the PIC32 parts costs EUR 20 at eBay and one PIC32MX220F032B costs EUR 2.43.
You are right with the low data rate. From my tests I see 0 to 3 nonces for 4*10^9 tests. At the highest rated speed of 1 GH/s this would result in maybe one nonce per chip, so for the full version with 1,000 chips it would be 1,000 nonces per second. It needs 32 bits to transfer it, and maybe another byte to tell the serial chain that it is a nonce report, which would result in 40 kHz. Should be possible with a 115,200 baud serial port.
But the PICs have to do some more calculation to keep the Avalons running, because 1,000 Avalons can't be updated fast enough over the serial line. If I implement the getblocktemplate concept in the PIC, they can mine a long time for one getblocktemplate response from a pool, without the need to be configured from the main controller all the time. The PIC32 is powerful enough for this algorithm.
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Shouldn't be too expensive. A PICKit 3 programmer clone for the PIC32 parts costs EUR 20 at eBay and one PIC32MX220F032B costs EUR 2.43.
I did find them, they are cheap.
You are right with the low data rate. From my tests I see 0 to 3 nonces for 4*10^9 tests. At the highest rated speed of 1 GH/s this would result in maybe one nonce per chip, so for the full version with 1,000 chips it would be 1,000 nonces per second. It needs 32 bits to transfer it, and maybe another byte to tell the serial chain that it is a nonce report, which would result in 40 kHz. Should be possible with a 115,200 baud serial port.
Ok 1000*5 bytes = 5000 bytes/sec but I didn't follow you on the 40 kHz.
But the PICs have to do some more calculation to keep the Avalons running, because 1,000 Avalons can't be updated fast enough over the serial line. If I implement the getblocktemplate concept in the PIC, they can mine a long time for one getblocktemplate response from a pool, without the need to be configured from the main controller all the time. The PIC32 is powerful enough for this algorithm.
There's one PIC per module (or one PIC for every 10 Avalons)? Or can you spread out the PIC to handle more than one module?
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5,000 bytes per second means 40,000 bits per second, so it would need a transfer bandwidth of 40 kHz (ignoring start and stop bits). That's lower than 115,200 baud of a standard serial port, so it should work, even with a PC as the controller. Might need some buffering on the PICs in the chain, but they have plenty of RAM.
I was planning one PIC per module. The Avalon datasheet doesn't say how many Avalons can be chained, the signal may deteriorate with too chips. And it makes the design easier: one PIC for one module, with one temperature sensor per PIC and one Avalon chain.
I think there are boards with 20 Avalons in chain, but there might be other problems, because it would need 0.9 V @ 40 A, which requires big traces. With 10 Avalons probably I can use a cheaper 2 layer board per module.
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5,000 bytes per second means 40,000 bits per second, so it would need a transfer bandwidth of 40 kHz (ignoring start and stop bits). That's lower than 115,200 baud of a standard serial port, so it should work, even with a PC as the controller. Might need some buffering on the PICs in the chain, but they have plenty of RAM.
Doesn't seem like an unrealistic setup. Those rigs with all the USB cables were way over-engineered. But were those ASICs or FPGA miners?
I was planning one PIC per module. The Avalon datasheet doesn't say how many Avalons can be chained, the signal may deteriorate with too chips. And it makes the design easier: one PIC for one module, with one temperature sensor per PIC and one Avalon chain.
I think there are boards with 20 Avalons in chain, but there might be other problems, because it would need 0.9 V @ 40 A, which requires big traces. With 10 Avalons probably I can use a cheaper 2 layer board per module.
Did you already say what temp. sensor? What's cost per module at now?
I see
1 avalon * $12 = 10 per module = $120
1 PIC = $3
Temp sensors = ?
2-layer PCB = ?
serial connectors = ?
incidentals = solder,flux,etc. = nex to nil
labor = fun = free = ?
ebay international lists lots of avalon chips but most in the U.S. seem to be plug-n-play mining rigs. I did see single lot of chips but they were much more expensive compared to the international listings. $5-6 per compared to $18 per.
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This is a first version of the schematic with the new PIC: https://github.com/FrankBuss/gandalf-minder/raw/master/eagle/miner.pdf (https://github.com/FrankBuss/gandalf-minder/raw/master/eagle/miner.pdf)
Some planned parts with Digikey part numbers:
CPU: PIC32MX220F032B-I/SO-ND
OR gate: 74LVC1G14SE-7CT-ND
hex schmitt trigger: 74LCX14MXCT-ND
25 MHz oscillator: 336-2942-ND
temperature sensor: TCN75AVUA-ND
But the most expensive part might be the 0.9 V voltage regulator with at least 20 A output (and a digital potentiometer to adjust the voltage). I found a nice module (http://www.digikey.de/product-detail/de/ATS030A0X3-SRZ/555-1252-1-ND/2665523), but it costs EUR 17.84. I have no experience with designing power supplies, so I might use this module for a first version, and in a later version I can try to integrate the individual parts on the board.
The serial connector from board to board and to the Raspberry Pi could be just pin headers and jumper wires.
And it would need a good heatsink. I can't find a good one at Digikey, but this one looks good:
http://de.farnell.com/jsp/search/productdetail.jsp?SKU=4621980 (http://de.farnell.com/jsp/search/productdetail.jsp?SKU=4621980)
EUR 16.34 for a nice big 20 cm x 10 cm heatsink.
And finally one PCB with 25 cm x 10 cm costs $13.60 at Iteadstudio (10 cm x 20 cm for the Avalon area and 5 cm x 10 cm for the PIC and the rest).
In sum it might cost EUR 50 for one module, without the Avalons. This is half the price of for example this board:
http://www.burninmining.com/product-category/boards/ (http://www.burninmining.com/product-category/boards/)
It has 20 Avalons, maybe this would be a good idea for my board as well.
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Toploser on this forum still has some nice heatsinks AFAIK (look in the buy/sell/wanted section). You could mount several modules on them. These heatsinks need a fan to be effective though.
Looking at the bitburner I'm not sure whether the heatsink should be placed on the solder side of the PCB. It seems more logical to place the heatsink on top of the chips (with heat conductive rubber in between). Perhaps others can chime in on this subject.
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Good idea with the heatsinks, bigger than what I found and cheaper. I'll ask him if he still has some left for sale.
Placing the heatsink on the back is better for QFN parts with exposed center pads, because the combined thermal resistance is lower than placing the heatsink on top of the chips (see for example this table: http://cds.linear.com/docs/en/packaging/Linear_Technology_Thermal_Resistance_Table.pdf (http://cds.linear.com/docs/en/packaging/Linear_Technology_Thermal_Resistance_Table.pdf) ). Of course, needs good heat conduction to the back side with some vias in the center pad.
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You are using a linear regulator for 0.9V core voltage?
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In sum it might cost EUR 50 for one module, without the Avalons. This is half the price of for example this board:
http://www.burninmining.com/product-category/boards/ (http://www.burninmining.com/product-category/boards/)
It has 20 Avalons, maybe this would be a good idea for my board as well.
That board says 5.6GH/s per board. They are using different chips?
Would there be any advantage to keeping the avalon board separate from the PIC and the rest? I was thinking that having a 10-avalon board with just the serial and power. Then have the PIC and the rest on another board. This may make it possible to swap out the 10-avalon board easily and possibly give an upgrade path for the next-gen avalon. Maybe make it more expensive but possibly offer reuse or repurpose even.
I'm not clear on the temp. control. We know they're going to run hot 0.9V@2A. is temp control for overclocking? Or as nice-to-have for monitoring?
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You are using a linear regulator for 0.9V core voltage?
No, this would be too much energy waste. As written in my last message, I plan to use this module:
http://www.digikey.de/product-detail/de/ATS030A0X3-SRZ/555-1252-1-ND/2665523 (http://www.digikey.de/product-detail/de/ATS030A0X3-SRZ/555-1252-1-ND/2665523)
That board says 5.6GH/s per board. They are using different chips?
They are using the previous generation of the Avalon chips, the A3256. But should be not very different, only less fast hash calculation.
Would there be any advantage to keeping the avalon board separate from the PIC and the rest? I was thinking that having a 10-avalon board with just the serial and power. Then have the PIC and the rest on another board. This may make it possible to swap out the 10-avalon board easily and possibly give an upgrade path for the next-gen avalon. Maybe make it more expensive but possibly offer reuse or repurpose even.
Good idea. And if I screw up the microcontroller part or if it doesn't work (I always forget some connections or something doesn't work as expected), it is easier to fix.
I'm not clear on the temp. control. We know they're going to run hot 0.9V@2A. is temp control for overclocking? Or as nice-to-have for monitoring?
It is for monitoring. I think with a big heatsink, and if I use only 10 Avalons per board, no fan may be needed. But if the ambient temperature rises to high, it might need to shut down, if it gets too hot. If it gets really hot really fast, it can send you a SMS, informing you that your house is on fire :)
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How many actual BTC do you typically get per GH?
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How many actual BTC do you typically get per GH?
This depends on how long you mine, see http://www.bitcoinx.com/profit/ (http://www.bitcoinx.com/profit/)
Currently it is 0.0002 BTC per GH per day.
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Wouldn't you get more $ if you mined Dogecoins instead? According to that link, your setup is going to be unprofitable for a very long time.
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You are right, it will need some months. As I wrote earlier, it is a just for fun project, and I can learn a bit from it.
For Dogecoins you'll need more powerful hardware, because of the required RAM for the algorithm. The Avalon chip can't mine it.
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That power supply part seems like the cheapest solution. Is it possible to find a part that will meet the specs for 15A? I guess that might add more complexity to the design too. My idea was to have two PS per module. But that may be more work than it's worth. However if you consider repurposing wouldn't a 15A supply be more useful than a 30A in other projects?
Another thought after looking at some of those PS parts and noticing that there's not that much to them. Maybe you could design one that exactly meets your requirement and save money. But than they become a one-off and may not be reusable for much else.
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You are right, I'll use the power supply module, and don't build one myself. Someone wrote me a part which I could use, but the full circuit would cost EUR 13, not much less than the EUR 18 and it would not be as perfect as one of these modules.
There are lots of these modules, no need to design my own, see here (http://www.digikey.com/product-search/en?pv16=732&FV=fff40042%2Cfff800df%2C2dc19ed&mnonly=0&newproducts=0&ColumnSort=0&page=1&quantity=0&ptm=0&fid=0&pageSize=25).
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There are lots of these modules, no need to design my own
Definitely a lot simpler to buy the complete part.
As for the heat dissipation I see the options as:
1. heat sinks and fans to warm the house
2. heat sinks and fans to create waste heat
3. utilize the Seebeck effect to generate power to feed back into mining
4. utilize the Seebeck effect to generate power to charge batteries, cell phones, etc.
5. utilize the Peltier effect to cool the incoming are to the fans to reduce fan speed and noise
6. utilize the Peltier effect to cool your temperate zone saltwater or freshwater aquarium
For a nice example of the Seebeck effect in a consumer product look at the BioLite stove. I really love that thing and I hope Dave buys one and does a teardown.
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Meanwhile I have one of those power supply modules and tested it with a stripe of copper of an old PCB, because at 30 A the resistance of the copper gets interesting, and I have never done this before. It is 12 cm long and 1.4 cm wide, this is the test setup. The load resistance was just some 2 mm^2 flexible wire, cut until I got 46 milliohms, for 22 A at 1 V:
(http://i.imgur.com/s8lj2QV.jpg)
I measured 7.6 milliohm for the copper stripe. With 20 A this would result in a voltage drop of 0.152 V and a power dissipation of 3 W. The power supply module gets very hot, too, needed a fan.
The temperature of the copper stripe, shot with my new Fluke VT02:
(http://i.imgur.com/bL1h61r.png)
Maybe I can use some wider traces and 70 um instead of 35 um copper. And the sense-pin of the power module helps a bit, but still a problem if one Avalon chip is up to 20 cm apart the other chip, which is important because of the low core voltage of 0.9 V. But this could be solved with soldering some silver wires on top of the traces. Just in case I'll remove the solder stop mask for it when creating the PCB. Maybe this is one reason that many other mining boards are using 4 layers?
Next week I'll get the PIC (it is available in SMD and DIP) to do some tests on a breadboard before I finish the Eagle schematic.
I don't think that the Seebeck effect would produce much more power than needed to light a LED, the efficiency is only 1-2%. Would be better to power some Stirling motor with the waste heat :)
BTW: the "SmartView" software for the VT02 is crap. First it didn't install on my PC and I had to search the temporary files to start the installation program manually. And when exporting an image, it doesn't export the scale on the right side properly (missing temperature numbers) and there are no useful features in the software at all. For example I would like to click with the mouse in the image and get the temperature, or adjust the image transparency overlay, as it is possible on the device. I wonder why the installation package needs 200 MB. But the device itself is nice, now they should hire some better programmers.
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I measured 7.6 milliohm for the copper stripe. With 20 A this would result in a voltage drop of 0.152 V and a power dissipation of 3 W. The power supply module gets very hot, too, needed a fan.
You are modeling the current/temperature profile of the PCB, right?
Maybe this is one reason that many other mining boards are using 4 layers?
I think you said 4-layer PCB is much more expensive. And you're saying that a 4-layer PCB allows multiple paths and therefore lower temperature and current per path?
Next week I'll get the PIC (it is available in SMD and DIP) to do some tests on a breadboard before I finish the Eagle schematic.
What hardware device do you use to program the PIC? I think I am going to go the atmel route to learn some mC programming.
I don't think that the Seebeck effect would produce much more power than needed to light a LED, the efficiency is only 1-2%. Would be better to power some Stirling motor with the waste heat :)
I thought an LED was super low power but the biolite (I haven't checked) must generate 5V 0.5A, I think, for charging.
BTW: the "SmartView" software for the VT02 is crap.
I guess you are on windows? Some of the dev. env. on windows seem to allow (encourage?) bloaty code. But really not limited to windows. I switched to linux (lots of bloaty dog code here too) but way more choices. I would be surprised if there weren't some alternatives for the VT02 for linux, maybe some for windows too. Check github.
Reminds me of "What Intel giveth Microsoft taketh away."
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The Biolite uses a much higher temperature difference.
For programming the PIC, I'll use the PICkit 3 (unfortunately the PICkit 2 doesn't support this PIC).
Looks like there is an alternative for the SmartView program: Someone reverse engineered the proprietary is2 file format and wrote a viewer script for Matlab (http://www.mathworks.com/matlabcentral/fileexchange/32352-readis2-import-is2-files-fluke-infrared-camera). I don't have Matlab, but this might be a good starting point to write a better standalone program for it, maybe with Qt.
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The Biolite uses a much higher temperature difference.
That's true and I also found that it has a battery that must be charged first before you can USB charge. So it probably trickle charges its own battery.
For programming the PIC, I'll use the PICkit 3 (unfortunately the PICkit 2 doesn't support this PIC).
I decided against the pickit3 because I feel it locks you in too much.
I don't have Matlab, but this might be a good starting point to write a better standalone program for it, maybe with Qt.
Qt is good. Pretty good portability if I recall.
Back to the topic of the miner, I saw a water-cooled solution for the BFL miners on kickstarter. Unfortunately I didn't find good pictures of the implementation.
Water cooling seems a bit overly complicated and messy and conventional cooling is cheapest and simplest.
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Hello, your project seems very interesting to me. I noticed you had some successful test, but i didn't found anything about the firmware used for these tests. Can you please advise on that subject? Thank's and regards!
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Hello, your project seems very interesting to me. I noticed you had some successful test, but i didn't found anything about the firmware used for these tests. Can you please advise on that subject? Thank's and regards!
:palm:
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Hello, your project seems very interesting to me. I noticed you had some successful test, but i didn't found anything about the firmware used for these tests. Can you please advise on that subject? Thank's and regards!
The tests are in the script directory. But it needed the DE0_NANO FPGA project as well, until today. This weekend I had some time and started with the PIC firmware implementation. Currently it does the same as the FPGA implementation, just a thin wrapper to translate the Python script commands over serial port to CONFIG_P/N signals and report back the REPORT_P/N word. The Eagle schematic is updated as well, it works on my breadboard. See the Github repository: https://github.com/FrankBuss/gandalf-minder
And with pic32prog it works even with my old PICkit 2 programmer, which is faster than my PICkit 3 programmer, which is the only programmer supported by MPLAB X for this microcontroller, which is silly, because pic32prog demonstrates that it works without problems with the old programmer.
It was not easy to write the firmware for the PIC, because the "PIC32 Peripheral Libraries" documentation is missing (the link in the start menu after installing MPLAB X is dead) and the version I found on Google is missing some functions as well. It doesn't help that there is some legacy library code, which is mixed with the new library and you have to implement some functions with low-level register access anyway. E.g. I couldn't find a library function to clear the UART overrun flag, and if it is not cleared when it happens, the UART stops receiving data. This is not consistent with the SPI module, which has a nice function for this purpose, with the obvious name SpiChnGetRov :-// . So if you want to use the Microchip library, you have to read the header files and sometimes the C implementation as well to see which registers are changed, and if you are lucky, you find something with Google or in the examples folder |O
Next step will be to test the analog inputs for the temperature sensor, and maybe for measuring some voltage levels as well, testing the digital potentiometer to set the core voltage with the power supply, testing a PWM output and tacho input for a regulated fan and then routing the PCB. Might need some time again, because I don't have much spare time at the moment.
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Thanks! This Github update seems to be what i was needed.
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Hello Frank,
did you try Arduino instead of PIC?
Did you play with Avalon A3222-Q56 chip?
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I lost interest in the project, because it would never generate any substantial money with the high hash rates at the moment. Would be still fun to do it when I have some more time and feel like I want to finish it.
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It's still a fun project to try - i made an FPGA miner a few months ago, and while it can't generate any money, it is fast enough to make coins on the testnet, which can be handy if you do Bitcoin development stuff.
(https://i.imgur.com/E6XH9KI.jpg)
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Frank, will it be intresting to you to play with Antminer's BM1387 chips?
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Frank, will it be intresting to you to play with Antminer's BM1387 chips?
No, I'm too busy now with my Vectrex Kickstarter project for the next months in my spare time.