DIY bitcoin miner for Avalon A3255-Q48 chips

[FrankBuss]

I got ten A3255-Q48 chips for bitcoin mining cheap from eBay. I guess there are companies who can build an end-user device for it, but would be fun to create my own miner with it. I already found the datasheet:

http://downloads.canaan-creative.com/hardware/A3255/datasheet/

and a prototype:

http://downloads.canaan-creative.com/hardware/A3255/prototype/

Looks like my old Altium account doesn't work anymore, still waiting until someone at Altium verifies my new registration, then I can download the viewer, because the prototype uses Altium Designer.

But the schematic shouldn't be too difficult, because it is a simple serial protocol for each chip and they can be chained. But looks like there is not much documentation for the project. Is there any other open source project for this chip?

I plan to use Eagle to do my own version. The controller part will be the controller board for my Crazy Cartridge ( http://www.crazycartridge.org ). It has a small FPGA, if the serial communication is timing critical and for the 25 MHz clock generation, and a microcontroller with USB (the SRAM on the board might not be needed). This can be connected to any Linux computer, like a Rasperry Pi, where a miner is running and which has a web interface to setup the miner (IIRC there is already a SD card image for the Raspberry Pi for such a system).

One A3255-Q48 chip can do 1 GH/s (@2.05 W / GHash). This will be $0.34 per day, if used in a mining pool, so it is really just for fun, until I can get some next generation ASICs

[Jon86]

Looks very interesting, I've been looking into GPU mining some Scrypt currencies, but it's sadly quite unprofitable for me 
How much did you pay for them?

[FrankBuss]

I paid EUR 12 per chip, which means maybe I'll get the hardware cost back over the lifetime of the system, if the bitcoin difficulty doesn't rise too fast. But looks like there are some offers for this chip on alibaba.com and aliexpress.com as well, maybe I can even sell some of my devices. There are some old 5 GH/s Butterfly Jalapeno miners with EUR 200 and higher bids at eBay

[Jon86]

Ah screw it, bitcoin's not going to earn you anything whichever way you do it. It's a shame, because if it was worth it, it could've been quite fun.
I'd say just try and sell what you've got!

[FrankBuss]

Yeah, I don't expect to make a profit. By the time when my hardware is finished, prices might be too low for the old competitor miners to sell my hardware. But could be still a fun project. And I will learn anything, down to the metal with the hashing chips, and all the layers in between, up to the mining software.

[chickenHeadKnob]

Yeah, I don't expect to make a profit. By the time when my hardware is finished, prices might be too low for the old competitor miners to sell my hardware. But could be still a fun project. And I will learn anything, down to the metal with the hashing chips, and all the layers in between, up to the mining software.

Unfortunately for you, you are facing the dual hurdles of time lost in design as you've mentioned, and also the costs of local power. With energiewende I don't think your situation will improve in the near future unless you can steal power from your neighbours  .

I have been looking at bitcoin because the theoretical computer sciencey aspect as well as the social aspect fascinates. One thing that mystifies, why hasn't a semi-manufacturer quietly stepped in with their own chips and started a mining operation themselves. They can afford the development costs and they could locate the installation to someplace cold with fast internet and cheap hydro, like Norway or Quebec. Or maybe one of them is already doing it, in which case all the little miners are in a truly hopeless lost cause.

[FrankBuss]

There is a company mining in Iceland:

http://dealbook.nytimes.com/2013/12/21/into-the-bitcoin-mines/

Their plans are not profitable for the end customers, but I guess they do get quite some money, and unlike mining on your own, no bitcoin difficulty or exchange rate risk

[FrankBuss]

The Jalapeno 5.5 GH/s miner was sold for EUR 436

Still no answer so far from Altium regarding my registration, I guess all people are on holiday. But meanwhile I found a link to the viewer. Silly to block it with a login-wall, the viewer is free anyway.

The schematic is as simple as expected. The hashunit is one PCB, which needs only four data lines (and the power lines) to control as many Avalon chips as I want. The two control lines are chained for all chips, and the two report lines are all connected together (there are two pullups, so it is an open collector signal). Looks like the power supply with a TPS40193 and some MOSFETs is on another PCB. I'll integrate this all on one PCB.

For controlling it, one FPGA should be sufficient, which I then connect to a Raspberry Pi.

[Jon86]

Yeah, I don't expect to make a profit. By the time when my hardware is finished, prices might be too low for the old competitor miners to sell my hardware. But could be still a fun project. And I will learn anything, down to the metal with the hashing chips, and all the layers in between, up to the mining software.

I'd love to see what the final design looks like, I've always been interested in buying the chips individually and putting a miner together. Please do post it if you get it finished 

[FrankBuss]

I got the chips and soldered one on a breakout board. First I fried one by trying this with a heatgun, but manually soldering all pins of the QFN chip worked (it is possible with a microscope to solder the pins at the sides of the QFN chip). I even drilled a hole in the breakout board to solder the big ground pad on the underside. But for the final PCB it should be no problem with my reflow oven and a solder paste stencil. This is the test setup, with a DE0 nano and a RS232 serial port adapter:



When powering up the chip it looks like it starts in highest speed configuration, with 2A on the 0.9V supply line. There is a debug clock output for the core clock, which says 10MHz. The datasheet says max clock is 1GHz, so I guess the debug output is divided by 100.

I can configure the PLL of the Avalon chip to 625kHz (by judging from the debug output port, for me the datasheet is not very clear and I expected half of it as the core frequency) and then it draws 160mA. This looks linear: when configuring it to 1.25MHz I can measure 300mA. The chip is cold at 160mA, good for testing. Of course, it gets really hot at 2A without a heat sink.

The communication interface uses two lines: config_p and config_n. There is an "idle" state, when config_p and config_n are both high. Sending a bit starts by setting both lines to 0, then waiting for 125ns, then setting config_p to high, if you want to send a 1 bit, or setting config_n to high, if you want to send a 0 bit, and then waiting another 125ns. There was no detailed timing description in the datasheet, but looks like there is no timeout, so after this cycle you can wait as long as you want, and then send a 1 or 0 bit again, or go to idle. Unlike other serial protocols, this is easy to read on a scope.

Chips can be chained. The datasheet didn't explain it in detail (it is still version 0.5, and I guess written in a rush because of the competitors and exponentially rising bitcoin difficulty per day), so I tested it: My FPGA has a receive module for the report_p/report_n lines (I guess the same protocol) and I connected it to the config_p/n chain output instead. When I send 18 words (32 bit per word), all words are forwarded to the output. But when I send more words, one word less is forwarded. The scope shows that it delays one word after the 18th word. This makes sense, because the first words are the same for all chips, and then each chip is initialized with a different nounce start. This first chip uses the last sent nounce, and doesn't forward it, the second chip uses the next to last nounce and so on.

Next step will be to create some test data for the chip and let it calculate the nounce for it. The datasheet is not very clear about the data format. There is some pseudo code how to initialize some words, but even the length of the expected data is not documented (but I expect 16 words, because of the 18 words from the chaining experiments, minus two words for the clock config).

I created a Github project for the current Quartus VHDL project, Eagle files and Python scripts with the communication test:

https://github.com/FrankBuss/gandalf-minder

I chose the name Gandalf, because he knows how to get something from Avalon

[Jon86]

Awesome work, it'd be great to see it mining  Which board are you using to communicate with it?

[FrankBuss]

It is a DE0-Nano: http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593
For the final PCB I will replace it with a smaller (and cheaper) Lattice MachXO2 FPGA, and a Raspberry Pi will communicate with it over the serial port instead of a PC.

[Jon86]

I see, well good luck! Keep us updated

[GND]

Hello Frank,
I already built a mining system with FPGA board DE0-nano and Raspberry Pi as
host just for fun. It is running stable for a month with ca. 10MH/s.
I found this tread while searching for purchasing the avalon chips to make my own avalon board.
So i'm very interested in your project and would like to work with you to develop such a mining
system. I cannot program FPGAs but i can build a hardware proffessionally (with altium).
Maybe we can help each other... 

[FrankBuss]

Ok, some progress, the chip generates a nonce. But it is not the expected nonce, because I guess something is still wrong with my calculations for the hash initialization, but I wrote an eMail to the support at avalon-asic.com, hopefully they can explain it in more detail.

The same nonce is generated each 68.7 seconds, which means it is working at 2^32/68.7=62.5 MH/s. I was wrong in my last posting, the debug clock output was 625 kHz, so the core is 62.5 MHz. Which means the chip can do one hash test in one clock cycle and which allows it to run at 1 GH/s for the maximum allowed frequency. All source code is in the github repository.

@GND: Sounds like a good idea. I'm good with FPGAs, but only mediocre with PCB design. Of course, if you have already Altium, you could simply use the project here: http://downloads.canaan-creative.com/hardware/A3255/prototype/ at least for the board with the ASICs. I will try to do it in Eagle anyway, but would be useful if you could review it before I send it to the PCB manufacturer and I can help with the FPGA programming.

@mobicek: not bad for low quantities. But if it really takes off, there are cheaper offers for larger quantities. The http://avalon-asics.com shop even claims it is in-stock and they don't do pre-orders anymore (says the FAQ), but would be really expensive, because of the minimum quantity of 2,500 pieces.

[Lurch]

Pretty sure you don't mean nonce.

Moderator removed reference to deleted post.

[FrankBuss]

Pretty sure you don't mean nonce.

Sorry, English is not my native language, looks like it has more than one meaning, and some awful slang meaning, but I mean this: https://en.bitcoin.it/wiki/Nonce

[baljemmett]

Pretty sure you don't mean nonce.

Yes, he does; it has a slightly different meaning in the Bitcoin world than in more general crypto, AFAIK, but it is an established term of art in the latter world.  Does rather make a Brit blink at first, though!

[vleo]

Ok, some progress, the chip generates a nonce. But it is not the expected nonce, because I guess something is still wrong with my calculations for the hash initialization, but I wrote an eMail to the support at avalon-asic.com, hopefully they can explain it in more detail.

Hi, I'm also developing system based on A3255-Q48, with 32 chips per board, from scratch schematics, with goal of maximum performance, thus using individual config for each chip (to set max. clock for each chip), and using separate power supply for each chip and Altera FPGA (Cyclone-II) controller in PQFP package, since my experience with BGA soldering quality is not too positive. Using FTDI 245R for USB I/O, and designed for ATX-24 power supply connector, with fan control circuits and temperature sensor included, mini-ITX formfactor.

PCB design and FPGA configuration don't  stress me too much, but sketchy docs for A3255 do...

Same as you, I can't figure out  the exact data format that goes to the chip - the "midstate" part in particular. Were you able to get further with deducing that data format or some word from Avalon tech support?

Now, let me try to sum it up, what's known about that data format at this point.

When I send 18 words (32 bit per word), all words are forwarded to the output. But when I send more words, one word less is forwarded.

Per datasheet, words are:

Code: [Select]

# clock
w[0]  <= clock setup
w[1]  <= clock setup reserved (0x0)

# hash data
w[2]..w[i-1]  <= ? "data" ?
w[i]      <= a1
w[i+1] <= a0
w[i+2]<= e2
w[i+3]<= e1
w[i+4]<= e0
w[i+5]..w[j-1] <= ? "midstate" ?
w[j] <= a2

# nonce
w[j+1] <= nonce

So, of 18 words you observed, we have only 8 (!) documented to some extent, and 10 words are unknown (assuming that 18 words that go through do not include the nonce word)

From discussion at bitcoin.org forum: (https://bitcointalk.org/index.php?topic=218193.80):

LSB (first bit, byte, word) [8B - Clock Config] , [12B - data], [4B a1],[4B a0],[4B e2],[4B e1],[4B e0], [32B midstate], [4B a2], [4B nonce - 0x00000000 - 1 Avalon chip]

so, there they have 20 words! And, supposedly that worked after all, but I'm not quite certain it's the same chip - A3255, seems it's the earlier one.

[FrankBuss]

No answer from the Avalon support so far. Maybe they are too busy with spending their money they got from all the crazy miners

I assumed the "midstate" is what a "getwork" response sends. And that's what my script should calculate. To verify: Start the Bitcoin Qt client, then a command prompt, "cd" to "C:\Program Files (x86)\Bitcoin\daemon" (or wherever it is on Mac or Linux), then start "bitcoind getwork". You should get something like this:

Code: [Select]

{
    "midstate" : "c878d422538a82a39135ba83195e80b3d392ca399d80b567e7ea971962f56533",
    "data" : "0000000262a0a8264e478e0e8e91444300e3f55705de236e6a6b34ca000000010000000001b90de5e2895cc42e0390996589417cb02b9e0636aa5297bb98469c8d9fa50152d39feb1902666600000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000",
    "hash1" : "00000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000010000",
    "target" : "0000000000000000000000000000000000000000000066660200000000000000"
}

Then start a Python 3.3 shell, load my script https://github.com/FrankBuss/gandalf-minder/blob/master/scripts/avalonHashData.py and you can try it like this:

Code: [Select]

from avalonHashData import calculateAvalonHashData
from binascii import hexlify
datastr="0000000262a0a8264e478e0e8e91444300e3f55705de236e6a6b34ca000000010000000001b90de5e2895cc42e0390996589417cb02b9e0636aa5297bb98469c8d9fa50152d39feb1902666600000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000"
for word in calculateAvalonHashData(datastr): print("%08x" % word)

It shows this output:

Code: [Select]

01a59f8d
eb9fd352
66660219
a009b2fb
fe08884d
a7867d3e
c2a21279
9ac7e2a2
22d478c8
a3828a53
83ba3591
b3805e19
39ca92d3
67b5809d
1997eae7
3365f562
2f3cf39b

As you can see, there are the midstate words (the getwork-data is in little endian, so the last midstate word 0x3365f562 are encoded as 62f56533 in the midstate array).

I guess the "data" in the A3255 datasheet are the first words of the second SHA256 block. Mining means hashing this block:

Code: [Select]

bitcoin block struct:
  int nVersion;
  uint256 hashPrevBlock;
  uint256 hashMerkleRoot;
  unsigned int nTime;
  unsigned int nBits;
  unsigned int nNonce;

and testing it for all nNonce, so that the resulting hash has a high number of leading zeros, better than specified in the "target". SHA256 hashes the input in 512 bit chunks = 64 bytes. For the first chunk that would be 4 bytes for the version, 32 bytes for hashPrevBlcok and 28 bytes of hashMerkleRoot. This chunk doesn't change, which is the reason you have to calculate it only once for testing all nNonce values. The SHA256 state for this chunk is called "midstate".

The second chunk is filled with zeros, so only 4 bytes of hashMerkleRoot, 4 bytes for nTime and 4 bytes for nBits needs to be transfered. I guess this is the "data" part of the datasheet. Would make sense, because it would fit 3 words length. Now the chip can use the "midstate" of the first chunk to initialize the SHA256 state, and then calculate the hash for the second chunk for all nNonce values.

Well, at least that's what I think how it works. I tried any combinations of little/big endian for the data (because bitcoin tends to change this at will at various steps), but no luck.

[GND]

Hi there,
maybe it is possible to port the mining design from DE0-nano to the avalon chips...
That can do someone who is familiar with VHDL design - i don't know about how
simple or difficult it is to port.

I already built a mining system with FPGA board DE0-nano and Raspberry Pi as
host just for fun. It is running stable for a month with ca. 10MH/s.

I followed this guide for FPGA mining (open source) on DE0-nano and it works.
http://www.designspark.com/blog/bitcoin-mining-with-a-raspberry-pi-and-de0-nano
I inserted a correction into this guide to run it with RPi and a mining pool such a BTCguild.
Just notice the comment from sparkerdesign (its me) to make it run with RPi.

[vleo]

bfgminer (git clone https://github.com/luke-jr/bfgminer.git) code has quite a few references to Avalon, and actual code supporting it. I did not comprehend it all yet (but would be working on it), 'midstate' and 'data' are mentioned here:

./driver-avalon.c:138

Code: [Select]

static inline void avalon_create_task(struct avalon_task *at,
      struct work *work)
{
memcpy(at->midstate, work->midstate, 32);
memcpy(at->data, work->data + 64, 12);
}

at least size of data is clear now (3 words) and midstate confirmed at 8 words.

[NiHaoMike]

Since Bitcoin is based on SHA256, could obsolete Bitcoin ASICs be repurposed for other uses like high speed generation of random numbers?

[FrankBuss]

BFGminer is mostly a fork of cgminer (there are even some "cg*" function names in the source code, he didn't care to rename it to "BFG*"). The cgminer source code for the avalon driver is more recent:

https://github.com/ckolivas/cgminer/blob/master/driver-avalon.c

Compared to the BFGminer source code, it has some additional #ifdefs for AVALON_A3255, for example for the nonce offset. I wonder if this works, because the datasheet says the offset is 0x180 and not 0xc0. And looks like it doesn't send the A0-A2 and E0-E2 words as mentioned in the datasheet. I wonder how this could work, or maybe the datasheet is wrong? Of course, the miner doesn't send it to directly the ASIC, but it is some USB device in between, maybe this does some more calculations and data conversions.

[FrankBuss]

Since Bitcoin is based on SHA256, could obsolete Bitcoin ASICs be repurposed for other uses like high speed generation of random numbers?

No, because the only output of the ASIC is the nonce, which generates some leading zeros when SHA256 hashed with some more data. You don't get the hashes itself from the chip.