DIY Ghz sampling head for <100Mhz scopes

[Mosaic]

Hi all:
This is a project I've been giving some thought to and I wanted to open a conversation on it.

1Ghz being the first target or merit, 3% accuracy a figure of merit. An overall stretch goal of 3Ghz to cover wifi etc.
Hopefully the outcome can be a kit or a DIY project etc.

I feel there is a need for this as >  1Ghz  scopes tend to stretch the hobbyist budget compared to the sub 100Mhz Rigol, Siglents etc.

So there's sequential sampling, random  sampling and Coherent Interleaved sampling methods I know of.

To me the trick is in the strobe triggering, triggering reliably (with known delays) off the signal itself  and the jitter management in a cost effective and DIY manner.
Balancing the  detector bridge strobe with a balun might be a bit interesting as well.

[rfeecs]

You have probably seen this old article:
http://electronicdesign.com/boards/1-ghz-sampling-oscilloscope-front-end-easily-modified

[Mosaic]

Yes I have, thx.

It is interesting and can no doubt be improved now.

It might be a reasonable starting point from a bock diagram or perhaps a Tektronix S1 or S3 approach as well can be looked at from the sampling POV.

Triggering and timing precision though needs thought given component availability like an ADCMP820 etc.

[Earendil]

I don't think there's a real need for a sampling scope front-ends.
There was a guy here who tried to do a 10 Ghz sampling scope. He had a working prototype yet he didn't manage to get the necessary funding on Kickstarter.
It's pretty much limited what you can do with it anyway. Most hobbyists don't do multi gigabit digital boards so they don't need it to verify signal integrity.

[Mosaic]

Maybe so:
But 10 Ghz sits squarely in the commercial arena of folks like Picoscope and may not be commercially viable given that mainly corporate and lab interests require proper warranty support and service and therefore will not support a KS project over an established product line.

Speed of data is guaranteed to improve all the time. Therefore instrumentation to monitor  such data is also required, maybe this project is before its time. I don't mind developing it for non commercial purposes.

 

[Kalvin]

Things may be changing as we now have USB 3.0. Also, using and probing FPGA LVDS signals in hobby projects would be possible, too.

[rfeecs]

... There was a guy here who tried to do a 10 Ghz sampling scope. He had a working prototype yet he didn't manage to get the necessary funding on Kickstarter.

It did eventually become an actual product.

The previous thread discussing that project:
https://www.eevblog.com/forum/testgear/10-ghz-usb-oscilloscope-by-darwin-sabanovic/

[Mosaic]

The approach of using a fast comparator with a DAC for a trigger/sample is interesting as a means to side step strobing a quad detector bridge.
This approach requires a means to track the trigger time of the comparator in the picosecond range ideally. For now I'd settle for the 20 pico second stepping range as a first run.
 Thus two comparators,  one to define the  zero time trigger , then one to trigger on +ve and then -ve going transitions and then use sin(x)/x interpolations for the inflection interpolation. Time stamping the triggering of the 2nd comparator is the key to reconstructing the signal.

Any suggestions for a low jitter, picosecond scale delay timing chip?

I can step back a bit in time and use a slotted line approach with the 2nd comparator. Then derive the signal reconstruction based on signal propagation and a capacitive vernier distance encoder. This would perhaps reduce semiconductor jitter issues, but enlarge the device and add mechanical issues. Advantage here is possible oversampling at any position along the wave front for better resolution of aberrations or ringing. Maybe 300 dpi as a realistic lower stepping precision.

With a modern uC the, slotted line / microstrip/ coplanar waveguide can be 'calibrated' for amplitude flatness and % signal transfer efficiency given a known signal reference, reducing mechanical precision requirements and wear effects over time. Add SOL cals and the device can also become a standing wave analyzer and impedance matcher with TDR benefits.

http://www.ultracad.com/mentor/microstrip%20propagation.pdf

Averaging propagation at, say, 150 ps per inch of FR4. With 300 dpi resolution we have 1/2 pico sec resolution. With enough oversampling jitter noise can be substantially reduced.

[tggzzz]

Any suggestions for a low jitter, picosecond scale delay timing chip?

Turn the problem on its head and look for time-to-digital (TTD) devices.

Or there are ECL delay lines for aligning clocks.

[NiHaoMike]

One that can go up to 5.8GHz or so would be very useful for analyzing 802.11.

[Lukas]

Some years ago, I've been into building a sampling scope using the comparator-as-sampler approach. Unfortunately, I never finished it
Sampler comparator was an ADCMP582.
For trigger generation, I used a startable ring oscillator (basically an and gate and transmission lines on the PCB) and an MC100EP196 delay line with analog fine tuning. The ring oscillator's output is divided by 2 to to reduce the length of the delay line. This signal is fed an ECL counter, that generates a pulse every 256(?) clock cycles. By presetting this counter, I can control the sampling instant with a granularity of approx. 10ns. To get down to ~1ps, the delay line is used.
Since both of these delay elements are rather inaccurate, the MCU measures the frequency of the ring oscillator. To calibrate the MC100EP196, it can be configured as ring oscillator as well, so the MCU can measure its frequency as well.

Unfortunately, I haven't been to characterize the start-up behaviour of the ring oscillator yet.

In general the approach of using a startable ring oscillator has the disadvantage, that for fast start up, the oscillator should have low Q, but for low jitter it should have high Q.
Anyone got any expericene with going the analog way? I.e. steering currents in and out of a capacitor for ramp generation

[Earendil]

One that can go up to 5.8GHz or so would be very useful for analyzing 802.11.

How would you use a sampling oscilloscope to analyze 802.11?

[Marco]

In general the approach of using a startable ring oscillator has the disadvantage, that for fast start up, the oscillator should have low Q, but for low jitter it should have high Q.

Why would that matter? You aren't relying on noise to start the oscillation are you? You said AND but I assume you meant NAND, the trigger makes one input high, output goes low and cycle starts ... how does high Q matter?

The problem is that your first cycle starts with a gate signal shape different from the steady state, so it will take a while to settle. A high Q simply means insensitivity to such effects, but it would still instantly start up. The higher the Q the better.

[Mosaic]

Some years ago, I've been into building a sampling scope using the comparator-as-sampler approach. Unfortunately, I never finished it
Sampler comparator was an ADCMP582.
For trigger generation, I used a startable ring oscillator (basically an and gate and transmission lines on the PCB) and an MC100EP196 delay line with analog fine tuning. The ring oscillator's output is divided by 2 to to reduce the length of the delay line. This signal is fed an ECL counter, that generates a pulse every 256(?) clock cycles. By presetting this counter, I can control the sampling instant with a granularity of approx. 10ns. To get down to ~1ps, the delay line is used.
Since both of these delay elements are rather inaccurate, the MCU measures the frequency of the ring oscillator. To calibrate the MC100EP196, it can be configured as ring oscillator as well, so the MCU can measure its frequency as well.

Unfortunately, I haven't been to characterize the start-up behaviour of the ring oscillator yet.

In general the approach of using a startable ring oscillator has the disadvantage, that for fast start up, the oscillator should have low Q, but for low jitter it should have high Q.
Anyone got any expericene with going the analog way? I.e. steering currents in and out of a capacitor for ramp generation

So you're doing random, non sync'd triggering? Then using known sequential time slices to sample the waveform for up to 10nS? But the EP196 isn't giving a reliable, known, delay and needs calibration?
The Ep196 appears to have a 16.7 pS  timing drift per °C rise. That is a lot for the app. Looks like you might need to do a 0.1°C accurate Oven controlled  box for it.

Then it has > 120ps Tr so  how accurate is this going to be for the app?

[Lukas]

In general the approach of using a startable ring oscillator has the disadvantage, that for fast start up, the oscillator should have low Q, but for low jitter it should have high Q.

Why would that matter? You aren't relying on noise to start the oscillation are you? You said AND but I assume you meant NAND, the trigger makes one input high, output goes low and cycle starts ... how does high Q matter?

The problem is that your first cycle starts with a gate signal shape different from the steady state, so it will take a while to settle. A high Q simply means insensitivity to such effects, but it would still instantly start up. The higher the Q the better.

Since I'm using an differential AND gate, I can make it a NAND gate just by swapping differential pairs. I'm not relying on noise for startup, the circuit is inherently unstable.
IIRC, I read that fact about Q factor in some paper about sampling scope timebases and considered ist plausible. Maybe I can find that paper again.

random, non sync'd triggering? Then using known sequential time slices to sample the waveform for up to 10nS? But the EP196 isn't giving a reliable, known, delay and needs calibration?
The Ep196 appears to have a 16.7 pS  timing drift per °C rise. That is a lot for the app. Looks like you might need to do a 0.1°C accurate Oven controlled  box for it.

Then it has > 120ps Tr so  how accurate is this going to be for the app?

No, I'm using the circuit to generate a known delay from the trigger event. Yes, the EP196 needs calibration, that's why I included circuitry to use it in an ring oscillator so that I can calibrate for non-linearity and drift. The idea was to calibrate for nonlinearity once, and do linear calibration every few seconds or minutes.

The rise time will only affect jitter since pretty much all of the trigger path is fully differential.

[Marco]

IIRC, I read that fact about Q factor in some paper about sampling scope timebases and considered ist plausible. Maybe I can find that paper again.

Hmm, I guess high Q higher order oscillators (a delay line oscillator being infinite order) are forced to run near linear ... so it will only reach steady state when the delay line is filled with a half period sine voltage.

Also it only just occurred to me that the inverter for a non-linear delay line oscillator needs to have a schmitt trigger input.

[LaserSteve]

I'd love to have a 1 to 1.5 Ghz sampling head. Especially if it were a dual  head for comparative phase measurements.
One of my friends has an ancient   TEK  1 Ghz sampler and it has turned out to be quite useful...

My contribution to the initial research reading  is attached, it makes a nice test pulse. It was designed by Dr. Houtman who did the delay line sampling scope plans mentioned earlier. When one does a little digging into Dr. Houtman's academic work, its very clear he knows his way around very fast phenomena.

I love the colliding wave  architecture he used to make a symmetrical pulse..

Steve

[Mosaic]

I'd love to have a 1 to 1.5 Ghz sampling head. Especially if it were a dual  head for comparative phase measurements.
One of my friends has an ancient   TEK  1 Ghz sampler and it has turned out to be quite useful...

My contribution to the initial research reading  is attached, it makes a nice test pulse. It was designed by Dr. Houtman who did the delay line sampling scope plans mentioned earlier. When one does a little digging into Dr. Houtman's academic work, its very clear he knows his way around very fast phenomena.

I love the colliding wave  architecture he used to make a symmetrical pulse..

Steve

I've added that doc to my collection of research docs related to this subject so far.

To keep the thread current I'm sharing my drop-box link of what I have collated so far. It is not very well curated yet but, I'm still gathering.
https://www.dropbox.com/sh/kmdbbjrzofdxmkb/AADKVlHctfqbE8CNwntixXnza?dl=0'

[Marco]

I'm not sure a balanced sampling gate with balanced sample pulses is really necessary if you see what LLNL did with an extremely simple two diode sampling gate ... it just makes it harder to go faster.

[xygor]

HMC661LC4B DC-18 GHz, ultra-wideband, 4 gs/s track-and-hold amplifier
HMC1061LC5 DC-18 GHz, ultra-wideband, dual rank 4 gs/s track-and-hold amplifier
LTC6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution

[Marco]

They want 600$ for it ...

[xygor]

I assumed you wanted something that worked.

Some more papers I didn't see in your list:

Random Sampling Oscilloscope for the
Observation of Mercury Switch Closure
Transition Times (1973)
JAMES R. ANDREWS, MEMBER, IEEE
http://w140.com/andrews_random_sampling_observe_mercury_switch.pdf

Random Sampling Oscillography (1964)
G. J. FRYE, MEMBER, IEEE, AND N. S. NAHMAN, SENIOR MEMBER, IEEE
http://w140.com/frye_random_sampling_oscillography.pdf

[Marco]

Tektronix/HP mainframes with sampling heads work for less than that.

[Mosaic]

Perhaps I should  indicate that since this is targeted for folks who can afford modern 100Mhz - 200Mhz scopes etc, perhaps in the $400 to $1K range, the DSO/PC compatible sampling head should also be limited to that range.

While using vintage tek/HP equipment and  CRT photography to do the job is fun, something a bit more PC and DSO friendly is warranted for modern signal analysis convenience.

[Earendil]

Perhaps I should  indicate that since this is targeted for folks who can afford modern 100Mhz - 200Mhz scopes etc, perhaps in the $400 to $1K range, the DSO/PC compatible sampling head should also be limited to that range.

While using vintage tek/HP equipment and  CRT photography to do the job is fun, something a bit more PC and DSO friendly is warranted for modern signal analysis convenience.

What are you talking about? The Tek 11800 series has RS232 interface. You can grab the screen digitally. You can also transfer all your data.
Such a system can be bought under $500 with a 12.5 Ghz low noise sampling head (+ shipping cost, which admittedly can be high if you're not in the US). For $100 more you can have the 20 Ghz version.

Edit: quote added.

[Alex Eisenhut]

Don't forget this monster

http://w140.com/tekwiki/wiki/567

If you can interface to it, you can get the digital readout through the giant circular connectors in the back.

[Mosaic]

Most of those older sampling gear are entirely out of cal. and are made of unobtainium. Often they require separate/additional equipment for triggering.

Of course I don't mind having one, since I like old gear, esp. the versions where there's a service manual.

But this thread isn't about buying vintage gear or everything becomes a moot point.

[Earendil]

These instruments typically have self-calibrating timebases. They even calibrate themselves during measurement sometimes, unless you switch that mode off. You can also calibrate the sampling heads semi-automatically. You just need to connect the sampling head to scope's calibrator output and then to a short.

Most of those older sampling gear are entirely out of cal. and are made of unobtainium. Often they require separate/additional equipment for triggering.

Of course I don't mind having one, since I like old gear, esp. the versions where there's a service manual.

But this thread isn't about buying vintage gear or everything becomes a moot point.

[Mosaic]

Let's not make this a discussion of vintage equipment capabilities as opposed to doing something of value today with readily available parts and techniques.
There are enough forums for vintage eqpt chat and comparisons.
If you believe 20, 30 , 40 and 50yr old vintage eqpt don't need calibration and self calibrate ad infinitum implying that components & connectors don't degrade and drift then that is a discussion for another thread. I won't comment on this one way or the other.

[Alex Eisenhut]

Let's not make this a discussion of vintage equipment capabilities as opposed to doing something of value today with readily available parts and techniques.
There are enough forums for vintage eqpt chat and comparisons.
If you believe 20, 30 , 40 and 50yr old vintage eqpt don't need calibration and self calibrate ad infinitum implying that components & connectors don't degrade and drift then that is a discussion for another thread. I won't comment on this one way or the other.

It's a zombie project, in 2013 I put up a google spreadsheet for a 1GHz sampler and it fizzled out. It's just too niche of a thing, and people like me who buy vintage samplers just to see the fastest rise-time are already in possession of what they want.

[Mosaic]

You have a link for that Alex?

[Alex Eisenhut]

You have a link for that Alex?

https://docs.google.com/spreadsheets/d/1efw5C2U4VGU46GVLI3AxW-FkTFu7iFoWMiCoZVMmH98/edit#gid=0

[Earendil]

It's you who raised the topic of "vintage" equipment and made ridiculous claims about these high-end instruments.

And I don't believe these instruments can self-calibrate. I know. Because I have these stuff.
E.g.: https://www.eevblog.com/forum/testgear/40-ps-rise-time/msg935430/#msg935430

Let's not make this a discussion of vintage equipment capabilities as opposed to doing something of value today with readily available parts and techniques.
There are enough forums for vintage eqpt chat and comparisons.
If you believe 20, 30 , 40 and 50yr old vintage eqpt don't need calibration and self calibrate ad infinitum implying that components & connectors don't degrade and drift then that is a discussion for another thread. I won't comment on this one way or the other.

[Earendil]

Also it seems quite obvious to me that you trying to make money on this. I normally wouldn't care about it but I don't like if someone try to mislead others. Sampling oscilloscopes are very specialized and for everyday use they aren't useful at all.
Without having a picosecond rise time pulse generator you can basically use these only to look at eye-diagrams. And that's it.
You can't decode any data. Also you can't even look at the eye-diagrams of serial communication protocols (like USB) because you need a clock to trigger on. But that's implicit in modern serial communication standards.

It's you who raised the topic of "vintage" equipment and made ridiculous claims about these high-end instruments.

And I don't believe these instruments can self-calibrate. I know. Because I have these stuff.
E.g.: https://www.eevblog.com/forum/testgear/40-ps-rise-time/msg935430/#msg935430

Let's not make this a discussion of vintage equipment capabilities as opposed to doing something of value today with readily available parts and techniques.
There are enough forums for vintage eqpt chat and comparisons.
If you believe 20, 30 , 40 and 50yr old vintage eqpt don't need calibration and self calibrate ad infinitum implying that components & connectors don't degrade and drift then that is a discussion for another thread. I won't comment on this one way or the other.

[Mosaic]

Earendil:
Please refrain from commenting on my thread. Your comments clutter constructive efforts.
Thanks for understanding.

You are self contradictory. Since, as you say,  this is a niche item and I am hoping to achieve it for a small investment, it's not about making money.

[Marco]

Some low ball GHz range sampler isn't too interesting. But a double digit GHz range sampling oscilloscope with TDR could be handy at low enough cost, especially for the TDR. Parts wise it could be done very cheap, especially if you avoid the boring high speed ICs.

This guy made a pulser with a rise time which is the near equal of integrated GaAs NLTL shock lines pulsers, he did it on a 2 layer FR4 board for a couple dollar in parts with rivets used for via stitching ... it's only let down in fall time because of the large dimensions of his CPW differentiator.

[Earendil]

Don't worry. I won't comment anymore since you never really answered any of the issues I raised. I  see no point of arguing with someone who just evades the questions without addressing the fundamental issues.
I'm off.

Earendil:
Please refrain from commenting on my thread. Your comments clutter constructive efforts.
Thanks for understanding.

You are self contradictory. Since, as you say,  this is a niche item and I am hoping to achieve it for a small investment, it's not about making money.

[KE5FX]

Some low ball GHz range sampler isn't too interesting. But a double digit GHz range sampling oscilloscope with TDR could be handy at low enough cost, especially for the TDR. Parts wise it could be done very cheap, especially if you avoid the boring high speed ICs.

This guy made a pulser with a rise time which is the near equal of integrated GaAs NLTL shock lines pulsers, he did it on a 2 layer FR4 board for a couple dollar in parts with rivets used for via stitching ... it's only let down in fall time because of the large dimensions of his CPW differentiator.

That's really interesting.  I've never heard of a step-recovery effect in ordinary bipolar transistors.  Usually they're operated in avalanche mode in this type of circuit, but he's only using 5 volts to power the whole thing.

I also like his construction technique -- CPW on a homebrew PCB with rivets (?) as vias is another cool trick I haven't run into before.

[Marco]

That's really interesting.  I've never heard of a step-recovery effect in ordinary bipolar transistors.  Usually they're operated in avalanche mode in this type of circuit, but he's only using 5 volts to power the whole thing.

I also like his construction technique -- CPW on a homebrew PCB with rivets (?) as vias is another cool trick I haven't run into before.

The method from this paper. A paper which deserved much more attention than it has had. I suspect there is a parallel to the DSRD diode effect because the way the transistor is driven is very similar (it's not simply taken out of saturation to create the pulse, but only driven into saturation for a short period before being turned off again).

[Mosaic]

Some low ball GHz range sampler isn't too interesting. But a double digit GHz range sampling oscilloscope with TDR could be handy at low enough cost, especially for the TDR. Parts wise it could be done very cheap, especially if you avoid the boring high speed ICs.

This guy made a pulser with a rise time which is the near equal of integrated GaAs NLTL shock lines pulsers, he did it on a 2 layer FR4 board for a couple dollar in parts with rivets used for via stitching ... it's only let down in fall time because of the large dimensions of his CPW differentiator.

Yes. But I don't have a sampling scope, but I am hoping to obtain a TDS694C 3Ghz, 5Vrms  real time scope. I have one being calibrated by a vendor now, which I'll buy if it cals on all 4 channels.
Then use that as the basis for 1 to 3 Ghz sampling pulse design. Gain skills/abilities/ experience and then go for the improved TDR level capable units.

Also just got a  60's era model 3300 Alford slotted line with all parts as a means of crosschecking propagation and impedances. I do have a 3Ghz VNA with SOL cal kit and a 3Ghz noise figure analyzer with cal'd noise source.

I can get a Tek 7854 with TDR 7S12 and sampling/pulse heads for about $400. Having problems locating a 7T11/A triggering plugin tho.

I love vintage Tek and HP/Agilent gear. (got 3 x 2465X scopes and  all the TM500 req'd calibration plugins). But I also love designing new things as I learn by doing. I forget half the theory stuff I learned from MIT  EE now and I still use my HP28S RPN programmable 32Kbyte  calculator from 1987!

I do appreciate all the links & papers shared so far and I'll keep updating the dropbox link with  them so its a general resource for anyone interested.

[LaserSteve]

Lets be practical a moment, shall we?

     She Whom Must be Obeyed/Honored has cut my new gear space allocation to near zero..   I thus must go the home-made  sampling route rather then buying big boxen that take up gear space..  She also does not understand taking risks on Ebay, but will allow new construction as she can sit with me while I solder... And she is handy with a wrench. No, I'm not THAT whipped, but she does have a point about my owning more then enough gear now..  Especially since she'd like to see my car fit into the other side of the garage, rather then see it piled with more gear....

     As I work on sampling phase detectors for 10 and 24 Ghz ham radio, having a 1.5 Ghz scope is more then enough to view my sampling gate signals.  Unlike the naysayers who think "free running" scopes are an abomination, I know the limitations, but really enjoy using the sampling method.  MY friend has a pile of Tek sampling gear, but his is an hour and a half away..  Not to mention his "SWMBO", who is an engineer,  wants him to spend more time on their family, and I don't blame her..  So I'd like my own sampler, and I know how to use it...

    Damn, If I could have found the ideal mate, the conversation would have been like this:   "Honey, I think we need a new Oscilloscope...  I'd like to get a 1 Ghz scope.." No Dear Heart, One Ghz is far too slow, would it not be more economical to just get the 2 Ghz now, Because next year you'll need to upgrade anyway.  Besides, I have a 20% off coupon for Lecroy." 

Instead I'm dating a Librarian...

      So lets not derail this with discussions of Tek and HP's past glory, which contain un-obtainium  custom parts from when they had their own fabs...

    Some day, some of you will be in EXACTLY the same place I am now... Enjoy it while your young and single and can blow a whole paycheck on a cool toy... And marry wisely, find a supportive  one who can/will tolerate and encourage  your need for hardware and hording parts...

 I'm still trying to explain to Her why I own a full size milling machine... Thank God for a guy from church who agreed to host it in his warehouse...

Steve

[LaserSteve]

As I am working at RF, I bought three of these sampling phase detectors, but would like to extend down to DC... And "UP" to pulses...

http://www.ebay.com/itm/131608328730?_trksid=p2060353.m1438.l2649&ssPageName=STRK%3AMEBIDX%3AIT

I convinced the seller to break the auction from whole lot to singles..

Steve

[Mosaic]

His PDF spec links seems broken.
but I found this gen. ref.
http://www.digikey.jp/en/pdf/s/skyworks-solutions/skyworks-sampling-phase-detector

[rfeecs]

Another link to the Macom datasheet:
http://www.datasheets360.com/pdf/7844736903451203870

Interesting little module.  I honestly didn't think that a hobbyist could make a fast sampler without being able to handle chip and wire, beam leads, etc.  Maybe with something like that, they could.

[Marco]

It's an interesting component, only needs a relatively slow (but high amplitude) balanced signal to drive the SRD to turn it into a sample bridge (basically figure 3b, the input capacitance of the buffers captures the sampled signal). That said LLNL, proved that even commodity schottky diodes can get up there.

PS. this kind of sample gate has a relatively small range by the way, couple 100 mVpp max.

[Mosaic]

His PDF spec links seems broken.
but I found this gen. ref.
http://www.digikey.jp/en/pdf/s/skyworks-solutions/skyworks-sampling-phase-detector

I ordered 3 as well, along with a few other mini circuits parts  (mmic amp, 4 GHz- digital step RF attenuators, low pass filter etc etc.) as he has a fair selection.

[chris_leyson]

Thanks Mosaic, it's going to be an interesting thread.

Funny how both the scopes I use are undersamplers and they get used on a daily basis, HP-54610B and Tek-7854. They each use different methods for capturing signals, the Tek samples both the X and Y channels randomly using a pair of sample and hold amplifiers and single 10-bit ADC multiplexed between X and Y channels. The HP samples Y1 and Y2 and probably uses sequential sampling, I'm still not sure how HP derive their sample timing they weren't giving much away in the HP Journal.

Thanks LaserSteve, those MACOM phase detectors look interesting, nice having the the SRD built in.

[Earendil]

Mosaic,

Please receive my heartfelt apologies. There's a real need for your sampler. It seems you found your target audience.
I'm a bit stunned by this yet. But it was hell of a learning experience. Not in engineering. But it was very useful for learning something new about the world and the human psyche.
I probably go now and bang my head to my desk for some time. 

[Marco]

I'm still not sure how HP derive their sample timing they weren't giving much away in the HP Journal.

Dunno about those scopes but the 11800 and it's many successors use the method described in this patent. Found the reference in the 50 Years of RF and Microwave Sampling overview paper. It's a triggered delay line oscillator like Lukas described, but with temperature compensation. Also build with discrete transistors rather than boring expensive ECL ICs (In my opinion ECL ICs and ultrafast comparators should be avoided to keep costs down, the most expensive components should be the PCB and the SMA connectors.) The vernier they use for fine grained delay is an IC ... a simple ramp based delay would probably be good enough though, you don't absolutely need 10 fs precision.

For long delays a method using a triggered oscillator is one of two options ... the other option being a ramp based delay with clock based interruption (ie. start the ramp on the trigger, at the next clock edge interrupt the charge/discharge for N clock cycles, then continue the charge/discharge until the level detector triggers).

[Mosaic]

Picked up this as a reference:
http://www.cambridge.org/us/academic/subjects/engineering/circuits-and-systems/circuits-electronic-instrumentation

Seems very pertinent.

[Mosaic]

Picked up this as a reference:
http://www.cambridge.org/us/academic/subjects/engineering/circuits-and-systems/circuits-electronic-instrumentation

Seems very pertinent.

Ramp based delays and SMPS PWM triggers/controllers go hand in hand. Perhaps there's a possibility there.

[LaserSteve]

This PDF covers the simplified SRD based sampling head used in a very popular microwave "Brick" oscillator with very low phase noise used by us HAMs.   Page 5 covers the sampler schematic used to lock the 1.2 Ghz  sapphire rod/cavity  oscillator used in the brick.  The sampler is driven from a ~100 Mhz crystal oscillator...

      The ~1.2 Ghz oscillator, at a Watt or more is multiplied up to the final frequency by a harmonic generator...  I'm posting the link so that those who bought the Ebay sampler can see an implementation...  Simple, no prescaler, and the phase noise is very low, which is needed for long distance, narrowband, SSB comms with microwaves..

John,  KE5FX, deserves a lot of credit for hosting this... I know it has helped me considerably...

http://www.ke5fx.com/brick/fwbrick.pdf

Steve

[Marco]

Is there any advantage to the test circuit from Skyworks using an isolating balun to drive the SRD over the unun transformer in the Brick oscillator?

If the ADC isn't all that fast you should add a buffer and peak detector behind the resistor combiner, Schottkys leak a lot.

[rfeecs]

If the ADC isn't all that fast you should add a buffer and peak detector behind the resistor combiner, Schottkys leak a lot.

Apparently it was common practice to feedback a portion of the amplified sample.  This is described here as "slide-back feed-back":
http://w140.com/tek_sampling_notes.pdf

It is also mentioned here:
http://w140.com/andrews_construction_of_broadband_sampling_head.pdf

The manual for the Tek S-4 sampler gives a great description of the theory of operation and schematics for the sampler.  It uses a "traveling wave sampler" which is described elsewhere.  Great pictures of it on this page, too.:
http://w140.com/tekwiki/wiki/S-4

I love these old manuals and the detail they go into.  All open source.

Clearly there are a lot of secondary issues like "blow-by" that they found ways to deal with.

Amazing that this stuff is 50 years old now.

[LaserSteve]

When working with low noise microwave sources, or any RF at all, ANY additional isolation is always a good idea.
Hence the Skyworks board layout. A lack of isolation in a PLL almost always results in more sidebands or noise....
In a sampling scope it is far more sensitive to any lack of isolation.

The toroid transformer  in the microwave  brick is encased by a 2.5 mm thick steel case that holds the crystal  oscillator and  sampler,  on one PC board.  The probe extends out of the case, into the power VCO.  However the sampler probe  is going to radiate into the VCO  oscillator a bit... But the field in the VCO oscillator cavity is so high (watts)   that it will swamp tiny amounts of reverse injection...

The sweep ramp and phase lock/ lock detector opamps, as well as the VCO driver are on another board, mounted in a
different cavity on the main block, which serves to aid in isolation from any RF. As these units were designed to be master oscillators in a RF noisy environment in a microwave relay station or Telco switching office, the shielding is well thought out and all lines into and out of the block are on capacitive, hermetic sealed, feed throughs.

If the device were not built the way it is, with very highly isolated modules, I'm sure more isolation at the injection frequency would have been used. Still amazing to obtain 10.244 Ghz with no prescaler, no counter, and a couple of op-amps as the signal processing.  This way the sideband noise is low, and the reliability is extremely high, with a loss of lock often triggering a automatic switch to a "protection channel" with a complete backup TX-RX system to ensure communications continues.  All done with a few opamps and some "jellybean" discrete transistors, with a second SRD installed in a microwave  filter creating the harmonics of the 1.2 Ghz oscillator up at 10 Ghz....

For bench tests, you could certainly get away with a toroid transformer with no shield... However I'd  want the baluns on my implementation.

I have no idea which SRD is used in the Brick's discrete  sampler, but the sampling diodes are 5082-2835 in the big glass packages, even at 1 Ghz...  Checking for a data sheet revealed this little gem:

http://www.rf-microwave.com/uploads/diodes/AN942.pdf

[LaserSteve]

One more link...  If this were only 1/5th the price...

http://www.semiconductorstore.com/cart/pc/viewPrd.asp?idproduct=46951

Steve

[rfeecs]

And yet another classic ap note, on step recovery diodes:
"Pulse and Waveform Generation with Step Recovery Diodes (AN 918)"
http://literature.cdn.keysight.com/litweb/pdf/5954-2056.pdf

And one more from the frequency domain point of view:
"Harmonic Generation Using Step Recovery Diodes and SRD Modules (AN 920)"
http://cp.literature.agilent.com/litweb/pdf/5989-6258EN.pdf

[Marco]

This PDF covers the simplified SRD based sampling head used in a very popular microwave "Brick" oscillator with very low phase noise used by us HAMs.   Page 5 covers the sampler schematic used to lock the 1.2 Ghz  sapphire rod/cavity  oscillator used in the brick.  The sampler is driven from a ~100 Mhz crystal oscillator...

How does it create pulses from the SRD step by the way? Reflections from the 150 Ohm resistors?

[Mosaic]

Found this to be useful  regarding phase noise/jitter measurement techniques. There's also a pdf online for the Rigol DSA 815 TG on the subject....as i have that I mention it here as well.
http://www.rohde-schwarz-usa.com/PhaseNoiseOnDemand.html?aliId=11319444

[Mosaic]

One more link...  If this were only 1/5th the price...

http://www.semiconductorstore.com/cart/pc/viewPrd.asp?idproduct=46951

Steve

yeah, that was pointed out early in the thread, but maybe we can do one for that? DIY though, not retail via middleman distributor.

[rfeecs]

This PDF covers the simplified SRD based sampling head used in a very popular microwave "Brick" oscillator with very low phase noise used by us HAMs.   Page 5 covers the sampler schematic used to lock the 1.2 Ghz  sapphire rod/cavity  oscillator used in the brick.  The sampler is driven from a ~100 Mhz crystal oscillator...

How does it create pulses from the SRD step by the way? Reflections from the 150 Ohm resistors?

Refer to page 2, figure 3:
http://cp.literature.agilent.com/litweb/pdf/5989-6258EN.pdf

On one half cycle, the SRD is forward biased and charge is stored in the SRD junction.  On the other half cycle, current is pulled out of the diode and energy is stored in the inductance of the transformer secondary.  When its stored charge is depleted, the SRD snaps off very fast.  The current switches to the Schottky diodes and the energy in the transformer inductance discharges in a short impulse.

[LaserSteve]

Some more Literature: One of my Favorite Journals is Review of Scientific Instruments... The nitty gritty "How To" journal of applied science that does not attract mere  theoreticians. 

Sampling Oscilloscope for Milli-microsecond Pulses at a 30 Mc Repetition Rate
Arnold S. Farber
Citation: Review of Scientific Instruments 31, 15 (1960); doi: 10.1063/1.1716780

Uses a simple diode shunt switch across a waveguide to act as a sampler to view a  10 Ghz carrier, downside, signal must be in a waveguide and have enough amplitude to drive a shunt switch and a diode detector, rep rate is 30 Mhz and uses vacuum tubes except for the detector and shunt switch diodes...  Gate pulse generated by a 2C39A disk triode.  Brilliantly simple for what it is.. Author found that by injecting a RF  signal to be viewed into the gate diode's cable, he could view those signals as well, via mixing.


---------------------------------------------------------------

Time-to-digital converter of very high pulse stretching ratio for digital storage
oscilloscopes

Keunoh Park and Jaehong Park
Citation: Review of Scientific Instruments 70, 1568 (1999); doi: 10.1063/1.1149626

Generates a ECL signal proportional to the time between a sampling gate pulse and a 250 Mhz sampling gate clock for interpolation of signals, ~ 20 picosecond resolution, up to 4 nanoseconds period...  Uses a series of ECL chips  and a current source driven ramp to generate a time measurement.  Worth viewing if you wish to have a means of calibrating the time between sampling pulses.

---------------------------------------------------


Optically coupled electrical sampling system with 4 GHz bandwidth
S. B. Samaan, L. Wilson Pearson, and Charles E. Smith
Citation: Review of Scientific Instruments 58, 60 (1987); doi: 10.1063/1.1139514

Turns a TEK  S6 Sampling head into a optical TDR using a 1 nanosecond, six amp,  Avalanche pulse to drive a laser diode.. Very interesting pulse generator and diode detector, plus it levels the laser pulse to pulse amplitude using feedback..... Many of the parts are pure un-obtainium, but there are modern equivalents...

---------------------------------------------------------------------------------------

High Speed Single Event Sampler
Hector A. Baldis and Jamshid Aazam-Zanganeh
Citation: Review of Scientific Instruments 44, 712 (1973); doi: 10.1063/1.1686228

Has a schematic of a complete sampling gate  head using HP diodes and an avalanche driver for said gate.
Uses matched HP 5082-2800 in a bridge, and author claims gate can pass 500-700 ps pulses..
Probably a 500 Mhz unit, but worth a read...  Author used 16 such gates as a sequential sample and hold matrix  driven by a 125 Mhz clock, using for the time, overdriven Schottkey  TTL counters.  Of course its missing feedback, slide thru protection, all the other stuff needed for a serious sampling scope...  No, they do not mention what the transformer material is...  Sensitivity is supposed to be 20 mV and up, no mention of upper limit...   And they do not describe how they did a high bandwidth, DC Coupled,  1:16 Fanout,  50 Ohm splitter for the input...

Partial Pic attached per Educational Use Clause... I deleted a good deal..   If you want more details, buy the article from RSI...

-------------------------------



Steve

[Mosaic]

This is interesting:
http://www.ti.com/lit/ds/symlink/adc32rf45.pdf

[PA4TIM]

I have a HP 3GHz prescaler unit from a counter that is modded by someone in the past to a standalone unit that can be used for a scope. The output is 0-50 MHz. But instead of feeding it to a counter you feed it to a scope. Maybe something to look at.

Just something I think of now, most DSO's have an equivalent sampling mode (or something like that) I never tried it but I think it does what you want; seeing higher frequency repetitive signals

I have a Philips 3400 1GHz dual channel sample scope, two 1GHz Tek 1S1 plugins and a 5GHz Tek 1S2 plugin. The latter is great for TDR but a disaster as sample scope unless you use it with a delay line (a rather big suitcase with a lot of cable).
Besides that, I use them only to play with pulsgens or other experiments, but never used them for something serious, tried them a few years back to repair a wifi router but they are not suitable for that. Finally I used a spectrum analyser to do the job.

[Mosaic]

I have a HP 3GHz prescaler unit from a counter that is modded by someone in the past to a standalone unit that can be used for a scope. The output is 0-50 MHz. But instead of feeding it to a counter you feed it to a scope. Maybe something to look at.

How shall we look at it?

[Mosaic]

I've devised an approach to throw out for comments. It goes like this.

1) A digital attenuator front end controlled by a uC.
2) A trigger comparator (ADCMP58x) next, feeding a 5ps stepping digital delay chip (sy8927u?, 2ns min delay, 7 ns max)
3) A 2.5 ns delay line (about 15" of 50 ohm FR4 microstrip, maybe U shaped) going to item 4.
4) A peak detect (ADCMP58x) comparator 'sampler' with a flash 8 bit DAC resistor R-2R  ladder Vref. driven by a uC & the nearby (<1") delay chip signal from (2).

Ok, the 8 bit DAC R-2R ladder is configured in 'reverse' where the delay chip pulse feeds the top via a current limiting resistor and the uC either floats or grounds the  'legs'  for the R-2R DAC to establish a Vref tapped just after the current limit  resistor fed by the delay line. This effectively becomes the 'sampling pulse' for the 2nd comparator.
The duration of the sampling 'pulse' from the delay chip can be controlled by a TDR grounded leg cancelling reflection and by the hysteresis of the first comparator to a suitable period.

The basic operation goes like this.
The uC steps the dig. RF attenuator and the Vref of comparator #1 (a regular R-2R 8 bit affair) to obtain a peak triggering of say 80% of the max comparator voltage input. This gives some DAC resolution control and a bit of input protection. This 'trigger' becomes the time reference for the sampling.

Once the trigger occurs, it is shaped by the hysteresis of  comp#1 and a TDR ground leg into a fixed length pulse period, suitable for use by comp#2.
The delay chip  has a 2nS min, which requires the 2.5nS delay line so we can peak sample a bit BEFORE the trigger event, which I think is a useful capability.

Now once the delay chip time period is set the  comp# 2 will 'sample' based on the analog  Vref produced by the trigger pulse and controlled by 8 uC lines. In order to get a peak sample, the uC will have to start from a max Vref and work down via the 8 bit control until comp# 2 triggers. Using comp#2 latch setting will inform the uC of the peak detection and it can calculate the actual Vref that = peak detect based on the known amplitude of the delay trigger and the setting of the 8 DAC lines. Achieving this first peak detection will take a few cycles of the RF input while the uC steps down the DAC Vref.

Having obtained the first known Peak detection and the first known time step from the trigger based on the delay chip setting, the uC can proceed to repeat this process by resetting the latches of the comparators after adding known delays (delay chip), maxing the 2nd comparator's Vref again and resampling the signal detection (now time offset triggered from the ref. peak) thereby building up a sequential profile of the signal.

The data from the sampling can be laid off to some FRAM memory to allow for upload via USB to a PC or output via a calculated 10 bit PWM & low pass filter to a low speed scope.

Depending on the uC speed and the fact that the parallel sampled DAC Vref/ Vpeak is derived on the fly with a simple calc with no use of an ADC I'd  venture that a couple hundred KSPS can be obtained.
The uC will know when a complete signal period is complete when a delayed signal sample = the peak sample. (This will require a manual tolerance tuning input by the user - perhaps by a quadrature encoder to prevent false period detection due to noise etc.). The uC  can  then report on frequency or perhaps do useful things like focus/zoom by oversampling of some part of the wave for better  time resolution samples and improved details.

Well, time to poke some holes in the concept folks.

[rfeecs]

Item number 3 stands out for me.

15" of microstrip on FR-4.  I would worry that might distort your signal.  Microstrip is dispersive and any lossy transmission line is dispersive.  So its loss and phase velocity changes with frequency.

According to this article (which may be biased against FR-4), at 3GHz the loss would be about 0.3dB per inch:
https://www.rogerscorp.com/documents/2122/acm/articles/Understanding-When-To-Use-FR-4-Or-High-Frequency-Laminates.pdf

So 15" would have about 1.5dB loss at 1GHz and 4.5dB loss at 3GHz.  That seems like a potential problem.

Notice the Electronics Design article mentioned at the beginning of this thread uses a loss compensation circuit for the delay line.

[Mosaic]

Yes. that looks like a good area to  invest more thought into. Perhaps some low loss semi rigid coax is required.

Also, I have to think some more on the sampling of the signal. The way it is the  2nd comparator can still trigger/latch high once there is no High Vref present as it is seeing the RF signal all the time or the digital hi from the 1st latched comparator once the trigger occurs.
This  would still happen when there is no sampling trigger presenting a high Vref via the R-2R ladder.

Introducing capacitive coupling post the 1st comparator driving the coax 2.5nS delay line will prevent any 'high' latched DC comp signal from  propagating to the 2nd voltage sampling comp. except for a quick transient pulse. Once that pulse isn't long enough or large enough to be noticed by the 2nd comp. the sampling should be ok.
 Then the 2nd Voltage sampling comparator will only latch high when  the Vref (trigger & DAC combo level) steps below the actual peak RF signal.

That capacitive coupling will have to have a fairly high resonance Frq and very low inductance to not cause issues at the freq span of interest. Also it will limit the low end of the freq span by acting as an HPF. But that should be manageable.

[rfeecs]

I've devised an approach to throw out for comments. It goes like this.

1) A digital attenuator front end controlled by a uC.
2) A trigger comparator (ADCMP58x) next, feeding a 5ps stepping digital delay chip (sy8927u?, 2ns min delay, 7 ns max)
3) A 2.5 ns delay line (about 15" of 50 ohm FR4 microstrip, maybe U shaped) going to item 4.
4) A peak detect (ADCMP58x) comparator 'sampler' with a flash 8 bit DAC resistor R-2R  ladder Vref. driven by a uC & the nearby (<1") delay chip signal from (2).

Ok, the 8 bit DAC R-2R ladder is configured in 'reverse' where the delay chip pulse feeds the top via a current limiting resistor and the uC either floats or grounds the  'legs'  for the R-2R DAC to establish a Vref tapped just after the current limit  resistor fed by the delay line. This effectively becomes the 'sampling pulse' for the 2nd comparator.
The duration of the sampling 'pulse' from the delay chip can be controlled by a TDR grounded leg cancelling reflection and by the hysteresis of the first comparator to a suitable period.

You are driving an R-2R ladder from the output of a delay chip with a 50 ohm impedance and a 55pS rise/fall time?  I can't see how that is going to work.  Your R-2R ladder will need to be able to pass a 6 GHz bandwidth signal through it to maintain that rise time.

Maybe just use a DC DAC signal for the comparator input and drive the latch on the comparator with your delayed trigger edge?

[PA4TIM]

I have a HP 3GHz prescaler unit from a counter that is modded by someone in the past to a standalone unit that can be used for a scope. The output is 0-50 MHz. But instead of feeding it to a counter you feed it to a scope. Maybe something to look at.

How shall we look at it?

Sorry, I missed it. I wanted to add the model number in my previous post but I forgot it. I mean looking in the manual/schematics from that plug in for ideas. Thinking outside the box. Just because it does work but it is a totally different way. Prescalers are cheap today and maybe it is an easy way to use them for instance for triggering.

It is the HP5254C. The mod is a power supply to use it stand alone and a smal 0-50MHz counter display. if you tune it for, let say, 2,524 Hz, you set the dial to 2,5 and the 7 segment led display at 24. To my surprise  this works better as my sample scope. http://www.pa4tim.nl/?p=1040 a picture of the plugin.

I have designed and build a 25MHz to 2GHz sweep generator. I made an attenuator with pin diodes and coplanar waveguide made from  FR-4.  https://en.wikipedia.org/wiki/Coplanar_waveguide That turned out to be a real pain in the .. The first setup worked rather well, but with an other piece of FR-4 to build it for my friend it was a disaster. I made filters and a VCO before this, but with microstrip based on FR4 and that worked better as coplanar waveguide. Reading about it at that time, the problem is the "epoxy" they use to make it hard (can not remember the English word for it) is not very constant and can differ from brand to brand and even within a brand. Also the moisture absorbed by the pcb from the air can have an influence. The better way is teflon (but not tried that myself)

[Marco]

I think the clock interrupted capacitor charge method makes most sense for a delay generator. This paper describes an example of a time to digital converter which combines capacitor charging with a clock in an similar way to how a delay generator would do it. I'm not a fan of all the ECL logic and high end opamps though, because it would jack the price up, but still it shows the potential of what can be done with discrete components.

The delay ranges you can get with those ECL programmable delay ICs is simply insufficient in my opinion.

[Lukas]

The delay ranges you can get with those ECL programmable delay ICs is simply insufficient in my opinion.

That's why I included the triggered oscillator in my design. It may not be the best solution, but it's rather simple since it doesn't involve any fast analog wizardry. It's easy to calibrate as well.

[Marco]

That is one of two options, I just think the other option is superior.

The problem with a square wave delay line oscillator is that jitter is a random walk additive process. This prevents them from being able to provide the stable longer delays "normal" oscillators can, where the cycle to cycle jitter at the amplifier has a much smaller effect on the fundamental oscillation in the tank circuit.

[Lukas]

Someone wrote me an email, asking for schematics of my sampling scope design, so I may as well post them here. Sorry for them being so messy... For some reason part numbers are missing, but they should be pretty easy to guess.

Some random notes:
IC3 selects between the two trigger inputs and rising/falling edge trigger. When a trigger arrives, IC4's output goes high starting the ring oscillator made of IC5 and IC6. The feedback
All single jumpers are pin headers for connecting control signals. The feedback path is approximatly 25cm long. Its output gets divided to reduce the ring delay line's length.
This clocks U$1 and IC8. U$1 is a counter that can be pre-set. When it reaches 0xff, the TC output goes low for one clock cycle, thus by changing the pre-set value, I can adjust the sampling instant in steps of approx. 10ns. The TC output gets resampled by IC8 to improve timing accuracy. Fine delay is adjusted using IC10 (should be an MC100EP196). The circuitry surrounding it is for configuring it as an ring oscillator for calibration purposes. Its output then gets buffered by IC12 and strobes both ADCMP582.

[David Hess]

Mosaic, I thought maybe we might have discussed this over at TekScopes@yahoogroups.com but a search did not turn up anything.  Other people have proposed and discussed your idea there.

I looked at this a couple years ago and concluded the following:

1. A sample head based on the Tektronix S-2 will work to at least 4 GHz and probably more like 8 GHz with modern schottky diodes which are better than what Tektronix used.  One of the participants in the TekScopes@yahoogroups.com group documented a rebuilt of his S-2 with diodes from Avago and got considerably improved performance.

2. Traveling wave gate samplers like the Tektronix S-4 have the advantage of working with step recovery diode pulse generators instead of avalanche pulse generators but are more complex and seem to suffer more from blowby.

3. Varactor and PIN diodes can be qualified to operate as step recovery diodes.  I remember it being mentioned that some bipolar transistors can be used this way as well.

4. I would completely throw out sequential operation and go with random sampling like the Tektronix 7T11 supports simply to get rid of any delay line and pretrigger requirements for viewing the leading edge of a pulse.  Unfortunately this means measuring positive or negative time between the sampling strobe and trigger but the 7T11 manages it just fine.  A modern implementation could get away with using two separate time-to-voltage converters.  Note that small amounts of trigger to strobe jitter are an advantage in this case and irrelevant if you only measure the actual trigger to strobe delay.

5. I would keep the internal trigger source function of the S-2 and S-4.  This would allow eye diagrams *without* a separate clock signal.  Note that when using random sampling, the strobe will corrupt the trigger where they meet but this could be seen as an advantage because it shows where the actual trigger point is visually.  When making eye diagrams, this is irrelevant because you can use a different area of the waveform for measurements.

6. When I looked into this, I concluded based on interest that it was uneconomical.  The people who could most use it have the funds to buy something from Picotech.  Maybe adding TDR capability like the Tektronix 11k series sampling heads would help but I doubt it would be enough.

7. Current integrating time to amplitude and amplitude to time circuits are completely adequate to get below 10ps resolution.  Power supply rejection will be critical however.

Take a look at "Circuits for Electronic Instrumentation" by T.H. O'Dell.  It has many chapters on pulse generation and sampling including an intriguing idea for using an open transmission line in place of the sampling storage capacitance.

[Mosaic]

Thx for the tips David:
I did acquire that text and it is very useful.

When I get time I'll refocus on the subject as there are some challenges I'd have to address now that I have a better understanding.

For the moment I'm refining the SG504 head to a full metal jacket affair with an offset nulling calibration on the 6Mhz datum line to 'compensate' for the small connector VHF losses on the output side, and I'm doing the Tekprobe 'improved' low noise, hi precision PSU to use the 4Ghz active probe on my other scopes & DSA.

[David Hess]

I considered a couple of different designs which I am just going to ramble on for a bit about.

For a sampling unit and sweep which uses an existing oscilloscope for a display, if the output is Y-T then the time measurement facilities of the existing oscilloscope can be used.  The problem with this is that the T output can have considerable jitter at fast time/div settings.  This does not matter with an X-Y display because points can be displayed out of order but it makes a Y-T display unusable unless the output is regenerated which could be done with a low performance microcontroller.  Some high performance test instruments like the Standford Research 620 frequency counter do this:

http://www.thinksrs.com/assets/instr/SR620/SR620scr1LG.jpg
http://www.thinksrs.com/assets/instr/SR620/SR620scr2LG.jpg

This problem can be ignored for time/div settings slower than about 100 picoseconds/division because the jitter in a good design will not be visible.  If you want to see what the jitter looks like, operate a Tektronix sampling oscilloscope in manual scan mode.

An X-Y display has its own problems though.  Automatic measurements will not be available and perhaps worse, DSOs, or at least all of the modern ones I have used, have terrible X-Y displays compared to analog oscilloscopes except in bandwidth and sometimes they do not even have that advantage.  Some very old DSOs support a clocked X-Y mode where samples can be strobed individually and these might work better but how many people have and use this unusual DSOs?  Might as well use an analog oscilloscope and avoid this problem altogether.

The other set of designs I considered were for complete DSOs which include both low bandwidth real time sampling and high bandwidth equivalent time sampling.  The idea here was to combine as many functions as possible.  Instead of a dedicated time delay counter, the low bandwidth real time digitizer can be used as a transition midpoint or centroid timing to digital converter to support high bandwidth sampling operation.  Alternatively if the time delay counter is implemented independently, then it can be used with both the real time and sampled inputs although modern DSOs have eschewed this capability.

Ultimately I would want to be able to create displays like this one which shows pattern dependent jitter in a TTL based delay:

[jcbottorff]

I'll stop being a lurker here and solicit some feedback on a potential low cost sampler design.

Suppose we made a PCB with a signal transmission line and a sample gate line, such that the length of the sample gate line was physically longer, so the velocity down the sample gate transmission line generates the inter-sample delays. Suppose we then place multiple sampling bridges along the signal line, with the sampling gate pulse coming from the longer path gate line. It looks like using a track-and-hold design would allow the signal to feed down the signal line continuously, with the sample bridges tracking, and when we interrupted the sample gate line with a sharp trailing edge, we could close successive sample bridges at periodic intervals. This would essentially take a burst of real-time samples. We then have some slow cheap ADCs, like SPI interfaced to a micro-controller, to read the row of sample values. If you had 64 sample bridges and ADC inputs (multiplexed?), and you arranged the physical properties to give 50 ps per sample delay, that would give just over 3 ns of samples, which for 1 Ghz+ signals would perhaps be sufficient data to average together.

Some unusual things about this design would be:

1) There is no trigger, as we will collect a group of consecutive real-time samples, and use software to align them. Each batch of samples would be randomly placed from the waveform start, but you could in software extrapolate the zero crossings, which seems like is enough to align multiple samples batches. You might also use software to calibrate each sample gates signal strength, as sample gates further down the path seem like some of the signal is diverted to earlier samples. No trigger means, no high speed variable delay or time measurement needed.

2) There would only be a single sampling frequency, so this does not work at less than really high frequencies. A 300 Mhz scope is available for a non-insane price ($2600 - Rigol MSO2302A). The minimum frequency would be determined by the burst sample time, which is determined by the sample time interval (physical distance) and the number of sample bridges.

3) A quad diode bridge that looks potentially appropriate for a sampling gate (Broadcom/Avago HSMS-282P-TR1G) seems to cost about $1.50, and you would need a sample capacitor and an ADC channel. If you had 64 sample points, and could get the per sample site down to $5 in parts, that's $300 for a 64 sample collection mechanism. You would need a microcontroller to read the ADCs and output either USB data or synthesize a much slower analog signal that you feed to your low bandwidth scope (like 1ns = 1 millisecond)

4) The PCB to do all this sounds really complex, although I know boards that have 96 lanes of PCIe-3 8 Ghz signals. To delay the 64th sample gate by a few ns would take a few feet more of signal path than the measured signal path. The really simplistic board looks like a straight line for the measured signal path, and an arrays of longer and longer zigzag gate paths. This also potentially is a transmission line with 64 long stub tees, which sounds like a reflection nightmare. I suppose another question is could you have a measured signal path with 64 sample bridge taps that didn't mangle the signal. 

5) Putting digital signals near analog signals you are trying to measure sounds bad, but perhaps you could stop all the digital activity before you initiated a sample burst 

Even if this design seems impractical (or insane), hopefully you found it an interesting workout for your brain. It initially seemed like eliminating variable delay lines or ps resolution time measurements was a good direction, but after explaining this design I wonder if I just traded some expensive parts for a really expensive impossible to design PCB.

I don't do RF design for a living (I do high speed software). I did grow up with a parent who was an RF designer in the 60s/70s (our family business made coaxial connectors), and while other kids were learning about baseball, I was learning about TDR on a Tek sampling oscilloscope. I've recently reactivated my electronics hobby, and pleased at how easy is was to make a 2ns edge pulse generator with modern parts. Making a better one, like the avalanche transistor on a transmission line kind, would require a lot better bandwidth scope to try it out. Some people go skiing, or play soccer for fun, I guess some of us find measuring the behavior of electricity fun. I regularly write software that executes 12 billions instructions/sec (per core) so guess it seems reasonable that I should be able to easily measure 1/12 billionth of a second.

Jan   

[Mosaic]

I have thought about that approach Jeff. In an effort to control cost and complexity:

I have also thought about using a slotted line method for doing the sampling along the signal path using linear inkjet printer transport mechanisms for a about 1 thou location accuracy over about a 10" distance which works out to 1Ghz or more  wavelengths at 70% propagation speeds.
This could also permit the investigation of VSWR and precision impedance matching.

[David Hess]

What you suggest has been done and I think HP may have used a sampling head which captured several samples per trigger.

[Mosaic]

Figure 4 in the PDF depicts a multiple of wavy lines carrying the signal and a straight strip carrying the trigger. This implies a multi channel sampler, each with multiple detectors.
Now the signal is propagating at a speed equivalent to the sampling trigger speed with a stepped 'delay'  introduced by the wavy microstrip.
I am presuming signal processing will compensate for the propagation of the signal waveform relative to the propagation of the trigger so as to make the trigger appear instantaneous so as to show an accurate waveform.

Couldn't an equidistant star distribution of trigger lines provide for an instantaneous trigger relative to the signal being sampled?

[David Hess]

If the the trigger lines are all equidistant, then the sampling time resolution is limited by the minimum distance between the sampling elements.  The divider network takes considerable space and the attenuation requires a stronger strobe.

The form shown in the LLNL sampler makes the sampling time resolution equal to the difference between the propagation delays of the two transmission lines and the space taken up by the sampling element becomes irrelevant.  Adjusting the length of the little loops changes the sampling time resolution.

[Mosaic]

If the the trigger lines are all equidistant, then the sampling time resolution is limited by the minimum distance between the sampling elements.  The divider network takes considerable space and the attenuation requires a stronger strobe.

The form shown in the LLNL sampler makes the sampling time resolution equal to the difference between the propagation delays of the two transmission lines and the space taken up by the sampling element becomes irrelevant.  Adjusting the length of the little loops changes the sampling time resolution.

I am not sure I follow this....what divider network and how does the sampling element space become irrelevant.

[Marco]

instantaneous so as to show an accurate waveform.

The sampling doesn't need to be instantaneous. Let say the trigger pulse takes 10 ps to travel between samplers and the signal takes 100, the first sampler takes the signal at 0 ps, by the time the trigger pulse is at the second sampler it sees the signal at -100 (what was there when the trigger initiated) + 10 (because the signal kept moving, it became a bit younger) = -90 ps, at the third it's -200 + 20 = -180 ... so you get equidistant sampling in time, exactly what you want. No processing necessary.

PS. maybe it would be better to say sampling pulse rather than trigger pulse so it's not confused with the actual trigger function. The signal is usually substantially delayed to give you some breathing room for the generation of the sampling pulse.

[David Hess]

I am not sure I follow this....what divider network and how does the sampling element space become irrelevant.

In order for the sampling gates to all operate simultaneously, the sampling strobe has to be divided and distributed using a network of equal length transmission lines.  These will take up a lot of space and unless the substrate has a uniform dielectric constant which common FR4 does not, the dividing network will accumulate delay errors from one end to the other although these could be calibrated out.

If the sampling gates all operate simultaneously, then the effective sampling rate is determined by the propagation delay along the signal's transmission line between sampling gates.  This limits the maximum effective sampling rate to how physically close the sampling gates can be constructed next to each other along the signal's transmission line.

For a 50 ohm microstrip on FR4, the propagation delay is about 80ps/cm.  How many sampling gates can be fit into 1cm? (1)  If two, that only yields 40ps between samples or 25GS/s which may seem fast but is what I would expect of a 500MHz to 1GHz equivalent time sampling oscilloscope.  My old 300MHz DSO is that fast and my analog sampling oscilloscope is a lot faster.

The arrangement shown in the LLNL paper makes the spacing of the sampling gates irrelevant because it is the difference in propagation delay between the signal and strobe transmission lines which determines the effective sampling rate.  The LLNL arrangement also solves the problem of distributing the sampling strobe and substrate variation in propagation velocity tends to cancel out.

Whether the LLNL design is the best arrangement for a cheap FR4 substrate is another matter but if you are using FR4, then I doubt you are interested in performance above 4GHz or maybe even 1GHz.  Sampling oscilloscopes with a single sampling gate only require a tiny amount of high performance printed circuit layout.

(1) In deference to your System International heritage, I will use metric units.

[Mosaic]

I do want to try making a sampling gate as an experiment on FR4 first. 1 Ghz is fine at first. I can use a TDS694C to compare/ calibrate results etc.

I see info on using a balun and a full wave bridge schottky sampling arrangement for a balanced result although that isn't mentioned by the LLNL folks.

I have Rodgers Duroid substrates on hand for more advanced work once I learn enough.

[David Hess]

I do want to try making a sampling gate as an experiment on FR4 first. 1 Ghz is fine at first. I can use a TDS694C to compare/ calibrate results etc.

I see info on using a balun and a full wave bridge schottky sampling arrangement for a balanced result although that isn't mentioned by the LLNL folks.

I have Rodgers Duroid substrates on hand for more advanced work once I learn enough.

Take a look at how the well documented Tektronix 7S14 and S-2 sampling heads which use half bridges are designed.

[jcbottorff]

If the sampling gates all operate simultaneously, then the effective sampling rate is determined by the propagation delay along the signal's transmission line between sampling gates.  This limits the maximum effective sampling rate to how physically close the sampling gates can be constructed next to each other along the signal's transmission line.

For a 50 ohm microstrip on FR4, the propagation delay is about 80ps/cm.  How many sampling gates can be fit into 1cm? (1)  If two, that only yields 40ps between samples or 25GS/s ...

Yes, the LLNL design is exactly what I was thinking.

I see the problem of how physically close you could put sampling gates. A potential solution would be to split the input signal along multiple paths, with each path having a slightly different physical offset. So if you had two signal paths, with an offset of half the distance  of each sampling gate, and all the sampling gates had an equal distance strobe, then one signal path would be the odd samples and the other path would be the even samples. This could be expanded to N input paths, limited by signal degradation and the physical accuracy of the sample gate placement.

For low-cost, the existing DS800 is pretty impressively priced, $300 on ebay for the 4 Ghz version. I'm not the designer of the DS800, so am only making guesses based on info I can find on the Internet of how it works. A downside is it seems to not use a sample-hold with an ADC, it seems to use a DAC with a comparator, so each sample only get's one bit, with multiple samples per trigger to sample delay to build up enough bits for a meaningful sample. The plus seems like perhaps it can adjust the amplitude resolution by adjusting how many bit samples it takes.

It's unclear to me how the DS800 using just a comparator makes a narrow sample time window, but posts on here seem to say the DS800 works ok. Perhaps the sample time windows overlap, and I'd have to do some research to decide if it really works to have overlapped sampling time windows, like if you took a 1ns wide sample every 50 ps, can you process that into the same result as having 50 ps wide sample windows. A 1 ns wide sample seems like it's the average of twenty 50 ps samples, so if you moved the 1 ns sample window by 50 ps (assuming perfect 0 ps risetime sample window edges, which they aren't), what you get is the average of 19 of the same sample points, with the leading edge sample point different, and the value can't change more than 1/20 of the full range, so if you had 4 or 5 bits more of amplitude resolution, you could calculate what the new value must be even though you can't directly isolate it from the other 19 sample points. I suppose a problem is a 1 ns sample doesn't have a 25 ps edge, so reality is a 1 ns sample windows will blur across multiple 50 ps sample windows, although if you knew the slope, it seems like software could still calculate the value of the new 50 ps window. It's a sliding weighted average instead of a simple uniform average.

Thinking about how sample windows work, makes me think of using an analog bucket-brigade (https://en.wikipedia.org/wiki/Bucket-brigade_device) for the samples. The Houtman sampler circuit used a master/slave sample and hold configuration. If you could perhaps have a bucket-brigade like way to store multiple samples, you could take groups of samples, and greatly expand the total sample window (or reduce the number of sample gates needed). For a purely hypothetical example, say you had 60 sample gates, put 50 ps apart, strobed every 3 ns, and then could store samples sets in a 10 stage bucket brigade (at 333 Mhz). At the end of the 30 ns sampling burst (33 Mhz), you would have to read out the 1800 real-time samples into ADCs. Oddly, this is beginning to sound like how CCD camera chips read out lines. I wonder if there are fast chips to read CCD charge lines, like a much faster version of the MN3867S. 

Jan   

[David Hess]

I see the problem of how physically close you could put sampling gates. A potential solution would be to split the input signal along multiple paths, with each path having a slightly different physical offset. So if you had two signal paths, with an offset of half the distance  of each sampling gate, and all the sampling gates had an equal distance strobe, then one signal path would be the odd samples and the other path would be the even samples. This could be expanded to N input paths, limited by signal degradation and the physical accuracy of the sample gate placement.

Signal degradation is a big problem.  Wideband resistive splitters have a loss of 6dB instead of 3dB so you very quickly reach the point where you signal is too small.  The last generation of Tektronix 500MHz and 1GHz 7000 mainframes used them because if you have enough gain available, they make a high performance design easier.

For low-cost, the existing DS800 is pretty impressively priced, $300 on ebay for the 4 Ghz version. I'm not the designer of the DS800, so am only making guesses based on info I can find on the Internet of how it works. A downside is it seems to not use a sample-hold with an ADC, it seems to use a DAC with a comparator, so each sample only get's one bit, with multiple samples per trigger to sample delay to build up enough bits for a meaningful sample. The plus seems like perhaps it can adjust the amplitude resolution by adjusting how many bit samples it takes.

It's unclear to me how the DS800 using just a comparator makes a narrow sample time window, but posts on here seem to say the DS800 works ok. Perhaps the sample time windows overlap, and I'd have to do some research to decide if it really works to have overlapped sampling time windows, like if you took a 1ns wide sample every 50 ps, can you process that into the same result as having 50 ps wide sample windows. A 1 ns wide sample seems like it's the average of twenty 50 ps samples, so if you moved the 1 ns sample window by 50 ps (assuming perfect 0 ps risetime sample window edges, which they aren't), what you get is the average of 19 of the same sample points, with the leading edge sample point different, and the value can't change more than 1/20 of the full range, so if you had 4 or 5 bits more of amplitude resolution, you could calculate what the new value must be even though you can't directly isolate it from the other 19 sample points. I suppose a problem is a 1 ns sample doesn't have a 25 ps edge, so reality is a 1 ns sample windows will blur across multiple 50 ps sample windows, although if you knew the slope, it seems like software could still calculate the value of the new 50 ps window. It's a sliding weighted average instead of a simple uniform average.

The DS800 is a clever low cost design which requires a high performance time-interval measurement which is required in a sampling oscilloscope anyway.  The comparator makes for a simple implementation but for a given construction technology, a sampler will be higher bandwidth at the expense of complexity.  The comparator also leaves you at the mercy of its analog performance and it lacks the overload recovery of a sampling bridge.

Thinking about how sample windows work, makes me think of using an analog bucket-brigade (https://en.wikipedia.org/wiki/Bucket-brigade_device) for the samples. The Houtman sampler circuit used a master/slave sample and hold configuration. If you could perhaps have a bucket-brigade like way to store multiple samples, you could take groups of samples, and greatly expand the total sample window (or reduce the number of sample gates needed). For a purely hypothetical example, say you had 60 sample gates, put 50 ps apart, strobed every 3 ns, and then could store samples sets in a 10 stage bucket brigade (at 333 Mhz). At the end of the 30 ns sampling burst (33 Mhz), you would have to read out the 1800 real-time samples into ADCs. Oddly, this is beginning to sound like how CCD camera chips read out lines. I wonder if there are fast chips to read CCD charge lines, like a much faster version of the MN3867S.

Existing sampling oscilloscopes do this in a very limited way with the fast but high droop sampling gate being followed by a slow but low droop sampling gate which gives enough time for the sample to be processed.  An analog design will also have a memory gate for the display so that is three buckets in series.

Tektronix has a long history with CCD sampling for real time digital storage oscilloscopes but I do not think they ever extended this to sampling oscilloscopes.

[Marco]

I see info on using a balun and a full wave bridge schottky sampling arrangement for a balanced result although that isn't mentioned by the LLNL folks.

Their setup is quite unlike the usual sampling bridges you see in most text, those tend to seek to create a connection to the sampling capacitor which can charge/discharge it.

AFAICS the LLNL one starts with a charged sampling capacitor, then the sampling pulse discharges it until it's equal with the sampled voltage. That's why it only needs the bottom of the bridge.

[Lukas]

Sad news: Avago/Broadcom recently discontinued their whole non-smart (i.e. diodes, transistors, frequency doublers and the like) RF lineup: https://docs.broadcom.com/docs-and-downloads/wsd/OBS120117WSD3-PLMM.pdf

If anyone plans on building a sampler based on the HSMS-282x diodes, better get hold of some before stock is depleted...

[David Hess]

Sad news: Avago/Broadcom recently discontinued their whole non-smart (i.e. diodes, transistors, frequency doublers and the like) RF lineup: https://docs.broadcom.com/docs-and-downloads/wsd/OBS120117WSD3-PLMM.pdf

I saw that.  I was hoping that that division was being sold off to someone else but it looks like it is dead and buried instead.

If anyone plans on building a sampler based on the HSMS-282x diodes, better get hold of some before stock is depleted...

A couple of other companies make similar schottky detector diodes up to duals with good availability and pricing.

[Lukas]

A couple of other companies make similar schottky detector diodes up to duals wit good availability and pricing.

Which ones? A quick search didn't yield any devices comparable to the HSMS-282x series.

[Marco]

JDH2S02FSTPL3 seems okay for single diodes.

[David Hess]

A couple of other companies make similar schottky detector diodes up to duals wit good availability and pricing.

Which ones? A quick search didn't yield any devices comparable to the HSMS-282x series.

Look for low voltage low current low capacitance small signal schottky diodes intended for microwave RF mixer applications.  Many include multiple diodes in one package.  I have not done a comprehensive search but these look likely:

Infineon BAT15 series
Skyworks SMS392x series
Nexperia 1PS70SB series

[Marco]

Looking carefully, the leakage current on JDH2S02FSTPL3, BAT15 are inconveniently high. Capacitance and package on 1PS70SB not ideal.

So that leaves Skyworks, slim pickings.

[David Hess]

I only went through datasheets for a few 10s of minutes.

Another alternative which might even be better than a microwave schottky diode is the base-emitter junction of a small signal microwave RF transistor.

[Marco]

They might be silicon diodes with very pure semiconductors and low inductance connections, but Schottky they aren't. They have recovery effects.

[David Hess]

They might be silicon diodes with very pure semiconductors and low inductance connections, but Schottky they aren't. They have recovery effects.

They sure do have recovery effects but schottky diodes have not been around forever and before they became available, silicon diodes were used in sampling heads up to at least 4 GHz.

[Marco]

The gate junction of a pHEMT is a Schottky by the way, most seem to have rather high leakage though.

[jcbottorff]

How about the MMDL301T1G as a sampling diode? The datasheet says the typical capacitance is 0.9 pF, the minority carrier lifetime is typically 15 ps, and a reverse leakage of typically 13 nADC. They're also $10 for 100 on Digikey (or $0.25/each), with 150K shown as available anywhere on Octopart.

The Avago quad bridge diodes, HSMS-282P-TR1G seems to be going fast on Digikey, there were about 3K a few days ago and I just bough 20 (as I've been toying with sampler ideas), with less than 500 left. Mouser still has about 800. The plus of the multi-device package is the diodes are claimed to be better matched, which is good for a sampling bridge.

Jan

[David Hess]

How about the MMDL301T1G as a sampling diode? The datasheet says the typical capacitance is 0.9 pF, the minority carrier lifetime is typically 15 ps, and a reverse leakage of typically 13 nADC. They're also $10 for 100 on Digikey (or $0.25/each), with 150K shown as available anywhere on Octopart.

Try them and find out.  They are a higher voltage part with higher capacitance though.

The Avago quad bridge diodes, HSMS-282P-TR1G seems to be going fast on Digikey, there were about 3K a few days ago and I just bough 20 (as I've been toying with sampler ideas), with less than 500 left. Mouser still has about 800. The plus of the multi-device package is the diodes are claimed to be better matched, which is good for a sampling bridge.

I think dual diodes make for a better layout and not all samplers use a four diode bridge.  In addition, using two schottky diodes in series for each element seems to yield much better results.

[Marco]

Why not build a sampling gate from a single diode? With the double diode setup ala LLNL the diode voltage theoretically cancels out, but you have to calibrate these things digitally any. Every extra component makes things slower with discretes. Tek could afford long ago to put tiny raw dies on subtrates and modern MMICs can use introductory electronics course component modeling into 10s of GHz ... but not us lesser souls. Of course others must have followed the same reasoning, so with my Google skills I found this patent.

UHS logic could provide a fast step with reasonable amplitude. Or if you want something even faster, the reverse recovery of a saturated BJT.