DIY Ghz sampling head for <100Mhz scopes

[Mosaic]

Thx for the tips David:
I did acquire that text and it is very useful.

When I get time I'll refocus on the subject as there are some challenges I'd have to address now that I have a better understanding.

For the moment I'm refining the SG504 head to a full metal jacket affair with an offset nulling calibration on the 6Mhz datum line to 'compensate' for the small connector VHF losses on the output side, and I'm doing the Tekprobe 'improved' low noise, hi precision PSU to use the 4Ghz active probe on my other scopes & DSA.

[David Hess]

I considered a couple of different designs which I am just going to ramble on for a bit about.

For a sampling unit and sweep which uses an existing oscilloscope for a display, if the output is Y-T then the time measurement facilities of the existing oscilloscope can be used.  The problem with this is that the T output can have considerable jitter at fast time/div settings.  This does not matter with an X-Y display because points can be displayed out of order but it makes a Y-T display unusable unless the output is regenerated which could be done with a low performance microcontroller.  Some high performance test instruments like the Standford Research 620 frequency counter do this:

http://www.thinksrs.com/assets/instr/SR620/SR620scr1LG.jpg
http://www.thinksrs.com/assets/instr/SR620/SR620scr2LG.jpg

This problem can be ignored for time/div settings slower than about 100 picoseconds/division because the jitter in a good design will not be visible.  If you want to see what the jitter looks like, operate a Tektronix sampling oscilloscope in manual scan mode.

An X-Y display has its own problems though.  Automatic measurements will not be available and perhaps worse, DSOs, or at least all of the modern ones I have used, have terrible X-Y displays compared to analog oscilloscopes except in bandwidth and sometimes they do not even have that advantage.  Some very old DSOs support a clocked X-Y mode where samples can be strobed individually and these might work better but how many people have and use this unusual DSOs?  Might as well use an analog oscilloscope and avoid this problem altogether.

The other set of designs I considered were for complete DSOs which include both low bandwidth real time sampling and high bandwidth equivalent time sampling.  The idea here was to combine as many functions as possible.  Instead of a dedicated time delay counter, the low bandwidth real time digitizer can be used as a transition midpoint or centroid timing to digital converter to support high bandwidth sampling operation.  Alternatively if the time delay counter is implemented independently, then it can be used with both the real time and sampled inputs although modern DSOs have eschewed this capability.

Ultimately I would want to be able to create displays like this one which shows pattern dependent jitter in a TTL based delay:

[jcbottorff]

I'll stop being a lurker here and solicit some feedback on a potential low cost sampler design.

Suppose we made a PCB with a signal transmission line and a sample gate line, such that the length of the sample gate line was physically longer, so the velocity down the sample gate transmission line generates the inter-sample delays. Suppose we then place multiple sampling bridges along the signal line, with the sampling gate pulse coming from the longer path gate line. It looks like using a track-and-hold design would allow the signal to feed down the signal line continuously, with the sample bridges tracking, and when we interrupted the sample gate line with a sharp trailing edge, we could close successive sample bridges at periodic intervals. This would essentially take a burst of real-time samples. We then have some slow cheap ADCs, like SPI interfaced to a micro-controller, to read the row of sample values. If you had 64 sample bridges and ADC inputs (multiplexed?), and you arranged the physical properties to give 50 ps per sample delay, that would give just over 3 ns of samples, which for 1 Ghz+ signals would perhaps be sufficient data to average together.

Some unusual things about this design would be:

1) There is no trigger, as we will collect a group of consecutive real-time samples, and use software to align them. Each batch of samples would be randomly placed from the waveform start, but you could in software extrapolate the zero crossings, which seems like is enough to align multiple samples batches. You might also use software to calibrate each sample gates signal strength, as sample gates further down the path seem like some of the signal is diverted to earlier samples. No trigger means, no high speed variable delay or time measurement needed.

2) There would only be a single sampling frequency, so this does not work at less than really high frequencies. A 300 Mhz scope is available for a non-insane price ($2600 - Rigol MSO2302A). The minimum frequency would be determined by the burst sample time, which is determined by the sample time interval (physical distance) and the number of sample bridges.

3) A quad diode bridge that looks potentially appropriate for a sampling gate (Broadcom/Avago HSMS-282P-TR1G) seems to cost about $1.50, and you would need a sample capacitor and an ADC channel. If you had 64 sample points, and could get the per sample site down to $5 in parts, that's $300 for a 64 sample collection mechanism. You would need a microcontroller to read the ADCs and output either USB data or synthesize a much slower analog signal that you feed to your low bandwidth scope (like 1ns = 1 millisecond)

4) The PCB to do all this sounds really complex, although I know boards that have 96 lanes of PCIe-3 8 Ghz signals. To delay the 64th sample gate by a few ns would take a few feet more of signal path than the measured signal path. The really simplistic board looks like a straight line for the measured signal path, and an arrays of longer and longer zigzag gate paths. This also potentially is a transmission line with 64 long stub tees, which sounds like a reflection nightmare. I suppose another question is could you have a measured signal path with 64 sample bridge taps that didn't mangle the signal. 

5) Putting digital signals near analog signals you are trying to measure sounds bad, but perhaps you could stop all the digital activity before you initiated a sample burst 

Even if this design seems impractical (or insane), hopefully you found it an interesting workout for your brain. It initially seemed like eliminating variable delay lines or ps resolution time measurements was a good direction, but after explaining this design I wonder if I just traded some expensive parts for a really expensive impossible to design PCB.

I don't do RF design for a living (I do high speed software). I did grow up with a parent who was an RF designer in the 60s/70s (our family business made coaxial connectors), and while other kids were learning about baseball, I was learning about TDR on a Tek sampling oscilloscope. I've recently reactivated my electronics hobby, and pleased at how easy is was to make a 2ns edge pulse generator with modern parts. Making a better one, like the avalanche transistor on a transmission line kind, would require a lot better bandwidth scope to try it out. Some people go skiing, or play soccer for fun, I guess some of us find measuring the behavior of electricity fun. I regularly write software that executes 12 billions instructions/sec (per core) so guess it seems reasonable that I should be able to easily measure 1/12 billionth of a second.

Jan   

[Mosaic]

I have thought about that approach Jeff. In an effort to control cost and complexity:

I have also thought about using a slotted line method for doing the sampling along the signal path using linear inkjet printer transport mechanisms for a about 1 thou location accuracy over about a 10" distance which works out to 1Ghz or more  wavelengths at 70% propagation speeds.
This could also permit the investigation of VSWR and precision impedance matching.

[David Hess]

What you suggest has been done and I think HP may have used a sampling head which captured several samples per trigger.

[Mosaic]

Figure 4 in the PDF depicts a multiple of wavy lines carrying the signal and a straight strip carrying the trigger. This implies a multi channel sampler, each with multiple detectors.
Now the signal is propagating at a speed equivalent to the sampling trigger speed with a stepped 'delay'  introduced by the wavy microstrip.
I am presuming signal processing will compensate for the propagation of the signal waveform relative to the propagation of the trigger so as to make the trigger appear instantaneous so as to show an accurate waveform.

Couldn't an equidistant star distribution of trigger lines provide for an instantaneous trigger relative to the signal being sampled?

[David Hess]

If the the trigger lines are all equidistant, then the sampling time resolution is limited by the minimum distance between the sampling elements.  The divider network takes considerable space and the attenuation requires a stronger strobe.

The form shown in the LLNL sampler makes the sampling time resolution equal to the difference between the propagation delays of the two transmission lines and the space taken up by the sampling element becomes irrelevant.  Adjusting the length of the little loops changes the sampling time resolution.

[Mosaic]

If the the trigger lines are all equidistant, then the sampling time resolution is limited by the minimum distance between the sampling elements.  The divider network takes considerable space and the attenuation requires a stronger strobe.

The form shown in the LLNL sampler makes the sampling time resolution equal to the difference between the propagation delays of the two transmission lines and the space taken up by the sampling element becomes irrelevant.  Adjusting the length of the little loops changes the sampling time resolution.

I am not sure I follow this....what divider network and how does the sampling element space become irrelevant.

[Marco]

instantaneous so as to show an accurate waveform.

The sampling doesn't need to be instantaneous. Let say the trigger pulse takes 10 ps to travel between samplers and the signal takes 100, the first sampler takes the signal at 0 ps, by the time the trigger pulse is at the second sampler it sees the signal at -100 (what was there when the trigger initiated) + 10 (because the signal kept moving, it became a bit younger) = -90 ps, at the third it's -200 + 20 = -180 ... so you get equidistant sampling in time, exactly what you want. No processing necessary.

PS. maybe it would be better to say sampling pulse rather than trigger pulse so it's not confused with the actual trigger function. The signal is usually substantially delayed to give you some breathing room for the generation of the sampling pulse.

[David Hess]

I am not sure I follow this....what divider network and how does the sampling element space become irrelevant.

In order for the sampling gates to all operate simultaneously, the sampling strobe has to be divided and distributed using a network of equal length transmission lines.  These will take up a lot of space and unless the substrate has a uniform dielectric constant which common FR4 does not, the dividing network will accumulate delay errors from one end to the other although these could be calibrated out.

If the sampling gates all operate simultaneously, then the effective sampling rate is determined by the propagation delay along the signal's transmission line between sampling gates.  This limits the maximum effective sampling rate to how physically close the sampling gates can be constructed next to each other along the signal's transmission line.

For a 50 ohm microstrip on FR4, the propagation delay is about 80ps/cm.  How many sampling gates can be fit into 1cm? (1)  If two, that only yields 40ps between samples or 25GS/s which may seem fast but is what I would expect of a 500MHz to 1GHz equivalent time sampling oscilloscope.  My old 300MHz DSO is that fast and my analog sampling oscilloscope is a lot faster.

The arrangement shown in the LLNL paper makes the spacing of the sampling gates irrelevant because it is the difference in propagation delay between the signal and strobe transmission lines which determines the effective sampling rate.  The LLNL arrangement also solves the problem of distributing the sampling strobe and substrate variation in propagation velocity tends to cancel out.

Whether the LLNL design is the best arrangement for a cheap FR4 substrate is another matter but if you are using FR4, then I doubt you are interested in performance above 4GHz or maybe even 1GHz.  Sampling oscilloscopes with a single sampling gate only require a tiny amount of high performance printed circuit layout.

(1) In deference to your System International heritage, I will use metric units.

[Mosaic]

I do want to try making a sampling gate as an experiment on FR4 first. 1 Ghz is fine at first. I can use a TDS694C to compare/ calibrate results etc.

I see info on using a balun and a full wave bridge schottky sampling arrangement for a balanced result although that isn't mentioned by the LLNL folks.

I have Rodgers Duroid substrates on hand for more advanced work once I learn enough.

[David Hess]

I do want to try making a sampling gate as an experiment on FR4 first. 1 Ghz is fine at first. I can use a TDS694C to compare/ calibrate results etc.

I see info on using a balun and a full wave bridge schottky sampling arrangement for a balanced result although that isn't mentioned by the LLNL folks.

I have Rodgers Duroid substrates on hand for more advanced work once I learn enough.

Take a look at how the well documented Tektronix 7S14 and S-2 sampling heads which use half bridges are designed.

[jcbottorff]

If the sampling gates all operate simultaneously, then the effective sampling rate is determined by the propagation delay along the signal's transmission line between sampling gates.  This limits the maximum effective sampling rate to how physically close the sampling gates can be constructed next to each other along the signal's transmission line.

For a 50 ohm microstrip on FR4, the propagation delay is about 80ps/cm.  How many sampling gates can be fit into 1cm? (1)  If two, that only yields 40ps between samples or 25GS/s ...

Yes, the LLNL design is exactly what I was thinking.

I see the problem of how physically close you could put sampling gates. A potential solution would be to split the input signal along multiple paths, with each path having a slightly different physical offset. So if you had two signal paths, with an offset of half the distance  of each sampling gate, and all the sampling gates had an equal distance strobe, then one signal path would be the odd samples and the other path would be the even samples. This could be expanded to N input paths, limited by signal degradation and the physical accuracy of the sample gate placement.

For low-cost, the existing DS800 is pretty impressively priced, $300 on ebay for the 4 Ghz version. I'm not the designer of the DS800, so am only making guesses based on info I can find on the Internet of how it works. A downside is it seems to not use a sample-hold with an ADC, it seems to use a DAC with a comparator, so each sample only get's one bit, with multiple samples per trigger to sample delay to build up enough bits for a meaningful sample. The plus seems like perhaps it can adjust the amplitude resolution by adjusting how many bit samples it takes.

It's unclear to me how the DS800 using just a comparator makes a narrow sample time window, but posts on here seem to say the DS800 works ok. Perhaps the sample time windows overlap, and I'd have to do some research to decide if it really works to have overlapped sampling time windows, like if you took a 1ns wide sample every 50 ps, can you process that into the same result as having 50 ps wide sample windows. A 1 ns wide sample seems like it's the average of twenty 50 ps samples, so if you moved the 1 ns sample window by 50 ps (assuming perfect 0 ps risetime sample window edges, which they aren't), what you get is the average of 19 of the same sample points, with the leading edge sample point different, and the value can't change more than 1/20 of the full range, so if you had 4 or 5 bits more of amplitude resolution, you could calculate what the new value must be even though you can't directly isolate it from the other 19 sample points. I suppose a problem is a 1 ns sample doesn't have a 25 ps edge, so reality is a 1 ns sample windows will blur across multiple 50 ps sample windows, although if you knew the slope, it seems like software could still calculate the value of the new 50 ps window. It's a sliding weighted average instead of a simple uniform average.

Thinking about how sample windows work, makes me think of using an analog bucket-brigade (https://en.wikipedia.org/wiki/Bucket-brigade_device) for the samples. The Houtman sampler circuit used a master/slave sample and hold configuration. If you could perhaps have a bucket-brigade like way to store multiple samples, you could take groups of samples, and greatly expand the total sample window (or reduce the number of sample gates needed). For a purely hypothetical example, say you had 60 sample gates, put 50 ps apart, strobed every 3 ns, and then could store samples sets in a 10 stage bucket brigade (at 333 Mhz). At the end of the 30 ns sampling burst (33 Mhz), you would have to read out the 1800 real-time samples into ADCs. Oddly, this is beginning to sound like how CCD camera chips read out lines. I wonder if there are fast chips to read CCD charge lines, like a much faster version of the MN3867S. 

Jan   

[David Hess]

I see the problem of how physically close you could put sampling gates. A potential solution would be to split the input signal along multiple paths, with each path having a slightly different physical offset. So if you had two signal paths, with an offset of half the distance  of each sampling gate, and all the sampling gates had an equal distance strobe, then one signal path would be the odd samples and the other path would be the even samples. This could be expanded to N input paths, limited by signal degradation and the physical accuracy of the sample gate placement.

Signal degradation is a big problem.  Wideband resistive splitters have a loss of 6dB instead of 3dB so you very quickly reach the point where you signal is too small.  The last generation of Tektronix 500MHz and 1GHz 7000 mainframes used them because if you have enough gain available, they make a high performance design easier.

For low-cost, the existing DS800 is pretty impressively priced, $300 on ebay for the 4 Ghz version. I'm not the designer of the DS800, so am only making guesses based on info I can find on the Internet of how it works. A downside is it seems to not use a sample-hold with an ADC, it seems to use a DAC with a comparator, so each sample only get's one bit, with multiple samples per trigger to sample delay to build up enough bits for a meaningful sample. The plus seems like perhaps it can adjust the amplitude resolution by adjusting how many bit samples it takes.

It's unclear to me how the DS800 using just a comparator makes a narrow sample time window, but posts on here seem to say the DS800 works ok. Perhaps the sample time windows overlap, and I'd have to do some research to decide if it really works to have overlapped sampling time windows, like if you took a 1ns wide sample every 50 ps, can you process that into the same result as having 50 ps wide sample windows. A 1 ns wide sample seems like it's the average of twenty 50 ps samples, so if you moved the 1 ns sample window by 50 ps (assuming perfect 0 ps risetime sample window edges, which they aren't), what you get is the average of 19 of the same sample points, with the leading edge sample point different, and the value can't change more than 1/20 of the full range, so if you had 4 or 5 bits more of amplitude resolution, you could calculate what the new value must be even though you can't directly isolate it from the other 19 sample points. I suppose a problem is a 1 ns sample doesn't have a 25 ps edge, so reality is a 1 ns sample windows will blur across multiple 50 ps sample windows, although if you knew the slope, it seems like software could still calculate the value of the new 50 ps window. It's a sliding weighted average instead of a simple uniform average.

The DS800 is a clever low cost design which requires a high performance time-interval measurement which is required in a sampling oscilloscope anyway.  The comparator makes for a simple implementation but for a given construction technology, a sampler will be higher bandwidth at the expense of complexity.  The comparator also leaves you at the mercy of its analog performance and it lacks the overload recovery of a sampling bridge.

Thinking about how sample windows work, makes me think of using an analog bucket-brigade (https://en.wikipedia.org/wiki/Bucket-brigade_device) for the samples. The Houtman sampler circuit used a master/slave sample and hold configuration. If you could perhaps have a bucket-brigade like way to store multiple samples, you could take groups of samples, and greatly expand the total sample window (or reduce the number of sample gates needed). For a purely hypothetical example, say you had 60 sample gates, put 50 ps apart, strobed every 3 ns, and then could store samples sets in a 10 stage bucket brigade (at 333 Mhz). At the end of the 30 ns sampling burst (33 Mhz), you would have to read out the 1800 real-time samples into ADCs. Oddly, this is beginning to sound like how CCD camera chips read out lines. I wonder if there are fast chips to read CCD charge lines, like a much faster version of the MN3867S.

Existing sampling oscilloscopes do this in a very limited way with the fast but high droop sampling gate being followed by a slow but low droop sampling gate which gives enough time for the sample to be processed.  An analog design will also have a memory gate for the display so that is three buckets in series.

Tektronix has a long history with CCD sampling for real time digital storage oscilloscopes but I do not think they ever extended this to sampling oscilloscopes.

[Marco]

I see info on using a balun and a full wave bridge schottky sampling arrangement for a balanced result although that isn't mentioned by the LLNL folks.

Their setup is quite unlike the usual sampling bridges you see in most text, those tend to seek to create a connection to the sampling capacitor which can charge/discharge it.

AFAICS the LLNL one starts with a charged sampling capacitor, then the sampling pulse discharges it until it's equal with the sampled voltage. That's why it only needs the bottom of the bridge.

[Lukas]

Sad news: Avago/Broadcom recently discontinued their whole non-smart (i.e. diodes, transistors, frequency doublers and the like) RF lineup: https://docs.broadcom.com/docs-and-downloads/wsd/OBS120117WSD3-PLMM.pdf

If anyone plans on building a sampler based on the HSMS-282x diodes, better get hold of some before stock is depleted...

[David Hess]

Sad news: Avago/Broadcom recently discontinued their whole non-smart (i.e. diodes, transistors, frequency doublers and the like) RF lineup: https://docs.broadcom.com/docs-and-downloads/wsd/OBS120117WSD3-PLMM.pdf

I saw that.  I was hoping that that division was being sold off to someone else but it looks like it is dead and buried instead.

If anyone plans on building a sampler based on the HSMS-282x diodes, better get hold of some before stock is depleted...

A couple of other companies make similar schottky detector diodes up to duals with good availability and pricing.

[Lukas]

A couple of other companies make similar schottky detector diodes up to duals wit good availability and pricing.

Which ones? A quick search didn't yield any devices comparable to the HSMS-282x series.

[Marco]

JDH2S02FSTPL3 seems okay for single diodes.

[David Hess]

A couple of other companies make similar schottky detector diodes up to duals wit good availability and pricing.

Which ones? A quick search didn't yield any devices comparable to the HSMS-282x series.

Look for low voltage low current low capacitance small signal schottky diodes intended for microwave RF mixer applications.  Many include multiple diodes in one package.  I have not done a comprehensive search but these look likely:

Infineon BAT15 series
Skyworks SMS392x series
Nexperia 1PS70SB series

[Marco]

Looking carefully, the leakage current on JDH2S02FSTPL3, BAT15 are inconveniently high. Capacitance and package on 1PS70SB not ideal.

So that leaves Skyworks, slim pickings.

[David Hess]

I only went through datasheets for a few 10s of minutes.

Another alternative which might even be better than a microwave schottky diode is the base-emitter junction of a small signal microwave RF transistor.

[Marco]

They might be silicon diodes with very pure semiconductors and low inductance connections, but Schottky they aren't. They have recovery effects.

[David Hess]

They might be silicon diodes with very pure semiconductors and low inductance connections, but Schottky they aren't. They have recovery effects.

They sure do have recovery effects but schottky diodes have not been around forever and before they became available, silicon diodes were used in sampling heads up to at least 4 GHz.

[Marco]

The gate junction of a pHEMT is a Schottky by the way, most seem to have rather high leakage though.