DIY Modular Test Equipment Project

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whilst proper eurocard rack enclosures are expensive, i bet you could do a simple DIY solution using std back plane connectors and some laser cut acrylic or simple ally frame etc??

Design you "processing" pcb as the back plane, with the IO and numerous serial bus connections, and have the various cards slot into that!

That would be possible but I would lose compatibility with solderless breadboards and protoboards which both use 0.1 inch spacing. The reason for the modules having 0.1 inch headers is if someone wants to hook up a module (like the waveform generator) to their own "processing board" like an arduino or raspberry pi they wouldn't need a custom made adapter board. They also have to fit in an off-the-shelf enclosure.

The other issue with plugging the modules at 90 degrees is that all the different IO would have to be on the processing board so they would be accessible on the front panel and they would take up a lot of space, not to mention the mechanical part, securing all modules so they don't flop around. That's the reason the current mechanical layout was chosen, as it only needs one surface to attach to, in the case of the waveform generator which has a 3D model shown shown here, is the front panel.

I also have to mention that all the bits of test equipment here are not precision driven but more by price, ease of construction and versatility so some compromises have been made.

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Some significant progress has been made on the DC Electronic Load module.

The microcontroller for the "smart" version is going to be a PIC16F18345, again, a newer part, chosen for the pin reallocation feature and the multitude of peripherals, most notable being the availability of two hardware SPI ports, one used for communicating with the UI board, the other one handles the peripherals.

Having all the versions on one board is going to be a bit tricky and it'll involve a few jumper links.

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The DC load will be split into two, one board with the analog stuff and temperature sensors, the other board will include the ADCs and DAC with the digital isolator and shift registers, haven't decided exactly what goes where but I'll make it in such a way so it will be shared with the lab supply.

I'm also thinking about a purely analog version, but that implies analog temperature sensors and comparators for the over temperature pretection as well as some solution for fan control.

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Made some block diagrams of what I have in mind so far. Hopefully I find a way around the tricky DC load requirements...
While I was still at it I decided to make one for each piece of test equipment.

If anyone's wondering what Q7 & Q15 are they're the last stage outputs of the shift registers used for Chip Select multiplexing.
DAC_I, ADC_I etc. are the chip select signals.
For the Waveform Generator I chose +7.5V to feed the linear regulator powering the square/PWM output driver but that might change. I could just slap a 5V linear regulator and ditch the +5V output from the Aux Digital Power Supply. It'll be cheaper too.

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The DC load final schematic is beginning to take shape.

Some changes were made to accomodate analog control so the digital temperature sensors were replaced by a pair of LM56.

The nice thing about them is that they have two built-in comparators with an input and an output available externally for each of them and the obvious way to go was to slap an SR flip-flop (with an inverter on one of its inputs) and turn each temperature sensor into a schmitt trigger with the input being the temperature and presettable high/low temperature thresholds.
It even has an internal voltage reference but it's not going to be used as there's already a more accurate LM4132-4.1 on board.

The UI board will read the temperature via two MCP3001 ADCs, the cheapest I could find with a SPI interface and external voltage reference input. 10bit is probably overkill anyway.

What's left to add is a PWM circuit for fan control for a fully analog version.

With all of those things in place I had an idea...

On paper a single DC Load module should be able to dissipate 100W but it should be tested after the thing is built. How? The answer lies in some lines of code that have yet to be written. I'm thinking about a test mode where you connect the load to a 150W+ voltage source and start "cranking" the current up while keeping a close eye on the temperature. Once things start warming heating up to a predefined temperature reduce the the current until thermal equilibrium is reached (in other words temperature reaches a stable value) and read the input power.

Another thing worth mentioning is the availability of two current ranges implemented like Dave described in his EEVblog #931. Look it up on youtube if you haven't already.

The SPI Isolation board will also include fan control/monitoring as well as the MCU for the "smart load" configuration along with isolated power. Nothing fancy, just a tiny MCP1416 driven pulse transformer with a few diodes and caps feeding two LDOs. The tricky part is having the whole lot of variants on a single board. I've previously done something similar and it's so easy to screw it up. Triple-checking won't cut it.

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I just realized I could simplify some things... maybe...
And reduce the BOM.
The only thing I have to do is delete the level shifters from wherever they're used and put them on the UI board but there might be some drawbacks...
You won't be able to use modules with different I/O voltages together without an additional level shifter but I won't do that so it's fine with me.

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Found another thing I f***ed up badly at. 74HC595 as SPI Chip Select multiplexer. I'll either have to use its reset pin or find a way to interrupt the data flow past it to the other SPI peripherals while shifting data into the 595 preferably using existing connector pins.

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Problem solved using a 74HC74 configured as a 2-bit Gray code counter since I only have one pin available for latching the 595's outputs. One output goes to 595 latch pin, the other to the reset.

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Problem solved using a 74HC74 configured as a 2-bit Gray code counter since I only have one pin available for latching the 595's outputs. One output goes to 595 latch pin, the other to the reset.

Better/simpler idea: divide the 74HC595 latch pulse by 2 and use it as a clock enable to the other SPI peripherals. Only a D-type flip-flop and some gates are required. The reset pin on the 74HC595 won't be needed.

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Eventually I ended up with a demultiplexer for the SPI clock line.
While looking for parts I ran into these really versatile configurable gates:
http://cache.nxp.com/documents/data_sheet/74LVC1G57.pdf
http://cache.nxp.com/documents/data_sheet/74LVC1G58.pdf
I might actually replace all of the different discrete gates with some of these so there are less part numbers on the BOM.

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Looks like having two current ranges for the DC Load is pointless but I might keep the range switching for voltage measurement just to get better resolution at lower input voltages.
I settled for 2A & 50V per module.
Minimum current will depend on the minimum output voltage of the DAC and the offset of the op amps but it will go down to 1mA.

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I did mention I found pin-compatible ADCs and DACs from TI & AD.
Here's a small list. These are the parts available at Farnell, and there's also a LT part I found.

• ADC
  
  • 12bit
    
    • ADS7816
    • LTC1860
  • 16bit
    
    • ADS8320
    • ADS8325
    • ADS8326
    • AD7683
    • AD7684

• DAC
  
  • 16bit
    
    • AD5662
    • DAC8501
    • DAC8531
    • DAC8551

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Had an idea for an OPP (Over Power Protection) circuit. That means I don't have to settle for 50V & 2A but an upper power limit while keeping a maximum voltage limit.
One way to achieve this is to set the threshold for the OVP (Over Voltage Protection) comparator based on the set current determined by the DAC output voltage. An op amp should do the trick. Time to play with LTspice.

[prasimix]

I don't see an OPP as critical to deserve dedicated circuit and not be limited/calculated by MCU or you want response time in microseconds range? Of course if you have dedicated OVP circuit than suggested method make sense when you are in CC mode, isn't it? For CV mode you have to take into account max. current.

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If there is a MCU then there won't be a dedicated OPP circuit but since there'll also be a non-MCU version on the same board I thought I'd design that in so it's harder to blow the MOSFETs up.

[0xPIT]

You might be interested in this project: http://www.heise.de/ct/projekte/machmit/ctlab/wiki (German)

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You might be interested in this project: http://www.heise.de/ct/projekte/machmit/ctlab/wiki (German)

To be honest, it would take me about a decade to build something like that on my own...
NI have done something similar but it's bloody expensive...

I never intended to put everything in the same box. Maybe I should change the title to "DIY Partially Modular Test Equipment Project"?

Anyway...
OPP circuit is working in simulation (LTspice). I used a discrete VCA and I know it has a lot of drawbacks as I played with one on a breadboard a few years ago. Since OPP doesn't have to be accurate it should be enough, limiting the maximum power to roughly 105% which is within safe limits. Hopefully this is the last thing I have to implement.

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OPP circuit is working in simulation (LTspice). I used a discrete VCA and I know it has a lot of drawbacks as I played with one on a breadboard a few years ago. Since OPP doesn't have to be accurate it should be enough, limiting the maximum power to roughly 105% which is within safe limits. Hopefully this is the last thing I have to implement.

And it's ditched as soon as I did a temperature sweep and expected it to be a mess and I was right.
I guess I'll have to live with some limitations for a fully analog version if anyone wants to build one...
In that case for a 2A version the load will shut down above 50V. Nothing more than a schmitt trigger needed.

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I'm thinking of changing the MCU again for something more powerful. Although the new 8-bit 16F1xxxx series has a lot of good stuff built in it might be a bit slow and lacking memory, and so far the only one I could find at Farnell and TME is the PIC16F18875 which has only 1k of RAM.
The other MCU which will be part of the control loop for the E-load, the 16F18345 is not available at the aforementioned distributors either.
EDIT: Guess I was wrong. Farnell has it.

Changing to a PIC18F would be quite pointless because I won't gain much from the 8x8 HW multiplier but the PIC24s have a 17x17bit multiplier and 32/16bit divider which is useful given the multitude of tasks it has to do.

To summarize, I'd use a PIC24FJ series 64-pin MCU in a TQFP package which will allow me to remove the shift registers on the UI board, and a PIC24F04KA201 for the E-load control loop for constant resistance / constant power loop. The other modification would be switching from SPI to UART for communication with the "smart" load modules since the 24F04K201 has only one MSSP module.They're both quite cheap.

Any thoughts on this? Let me know.
Too complicated, would take me too much time.

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The SPI isolation board is turning into a connectivity nightmare when it comes to routing. I'm limited to a width of 80mm and height of 20mm less than the DC load board which has to fit into a case which is 100mm or 115mm tall since it's going to sit on top. It'll also have to support both regular 0.1 inch pin headers as well as IDC headers. The pin headers will be used for daisy-chaining and the IDC headers only for the first board in the chain on the UI side. Daisy chaining using the pin headers also requires a mirrored pinout for right angle pin headers so this means another row of pins connected to ground.

Since the SPI isolation board also has to plug into the Lab PSU board it means that that latter has to also be 80mm wide so I guess I'll have to start working on that too to make sure everything fits together.

This is going to be tricky.

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Everything is starting to come together nicely. The DC load schematic is almost finished as well as the SPI isolation board.
I've also started working on the linear part of the lab power supply aka the post-regulator to make sure the SPI isolation board fits on top of it and the whole thing seems to end up around 100x80mm.

The pre-regulator is going to be on a separate board which will also output the +/-5V rails required by  the lab power supply as well as a bias voltage around 5V above the pre-regulator voltage.

There's still a long way to go.

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Sorry for not posting anything lately... that doesn't mean I abandoned this though.

Some changes are in place, mainly changing the bus used to link all the modules together to something similar, a simplified version of what prasimix proposed here, which he's developing with a bit of assistance from me.

For the simplified version of the bus only 15 lines are necessary, as described below for the UI board:

• CLK - clock line for feeding a clock signal to other microcontroller in the bus
• GPO - General Purpose Output - user configurable output, can be used to control fans, etc.
• GPI - General Purpose Input - user configurable input, can be used for measuring fan rpm, etc
• SDA - I2C data line
• SCL - I2C clock line
• 1-WIRE (Note 1) - for connecting devices using Maxim's one-wire bus
• TX - UART TX - configured as open drain to allow multiple master devices
• RX - UART RX
• ST_CP - 595 shift register storage pulse, latches the shifted data to the ouputs
• SH_CP (Note 2) - 595 shift register clock, driven from the SPI clock line
• QS (Note 3) - SPI data output to 595 shift register
• MOSI - SPI data out
• MISO - SPI data in
• SCLK - SPI clock
• nCS - SPI chip select output

Notes:
1. the one wire bus uses a UART module
2. SPI output available via Peripheral Pin Select (PPS)
3. on peripheral boards (waveform gen, etc) it will connect to the 595's data input via the bus input connector, while the 595's last bit shift register output (QS) will connect to the bus output connector and to the data input on the next board for daisy chaning, a schematic will explain this better

Changes have been made to the UI board to accommodate the new bus connection which uses 5V signalling. The microcontroller used will be a PIC18F65K40 or any of its bigger brothers in case more RAM is needed. Ditched the switchmode regulator in favor of cheaper LDOs. Since the LCD runs on 3.3V while the MCU rins on 5V some level shifting was required. This was achieved by making the I/O pins open drain and setting the input levels to TTL, with pull-ups to 3.3V.

The Waveform Generator has changed a bit, with the square wave output fed from a comparator connected to the first amplification stage after the DDS filter, capacitively coupled. What that means there's no PWM capability on that output anymore, that will be available on the Frequency Counter module, the next one I'll be working on. I'm also using a dual output reference, a REF3140 since it's easier to bias things.

As far as connectors are concerned no changes will be made, sticking to ribbon cables for data and keyed headers for power.

If anyone's still following this I have to say I want to see this completed as soon as possible but with so many modules I have to make sure everything fits together before throwing money at it. I don't want to have a second revision right after I build the first one so I'm taking my time to make sure it works first go.

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Looks like I haven's posted anything in here for quite some time...
Well then...

After running into the 500-pin limit of the free non-profit version of DipTrace more than enough times I decided to give KiCad another go after watching some random presentation on YouTube so here goes me redrawing everything. There won't be any lack of drawbacks however, because you can't use sheets in KiCad yet(?) and although there's a workaround using hierarchical sheets you can't copy anything from the root sheet so unless you start messing with the files you've got your work cut out so I'm not going to do everything twice and since this is not a review of KiCad I shall end the rant here.

What I'm going to end up with due to the lack of sheets is huge schematics but at least they'll be separated into functional blocks.

Creating all the missing components is going to take some time as well.

More updates coming soon^TM.

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Things look like they're coming together nicely. Since I have no pin limit anymore I'm going to put the Waveform Generator and the Frequency Counter on the same PCB while keeping the mounting on the back of the UI board.

The Lab Power Supply schematic is almost finished, the only thing that's preventing completion is that I'd like to have as many components / functional blocks shared between all modules, making PCB layout, firmware and ordering of parts less tedious. I'm also keeping the option of having it work without digital control while keeping switchmode regulator sync, fan control with OTP (Over Temperature Protection) and switching off the pre-regulator for low output current settings.

It has been previously mentioned that there were going to be two AUX power supply modules, they're now going to be merged into one and used to power the Waveform Generator + Frequency Counter or the DC Load modules. Where there are linear regulators there will be the option to choose between TLV1117/LM317 and 78xx for the positive supply rails and LM337 and LM79xx for the negative supply rails. There might also be a fan control circuit on that, haven't decided yet.

Since I've mentioned the DC Load I might as well get into some details, first of which will be the 'weird' supply voltages of +7.5V and -2.5V for the op amps (OPA2727, also used in the Lab Power Supply) since their maximum supply voltage is 13.2V along with +5V/-5V

On the ADC side I ended up using only one with a 74HC4051 multiplexer for all measurements on both the Lab Power Supply and the DC Load. There's a list of pin-compatible ADCs and DACs a few posts back.

As you've probably noticed, updates on this will be fairly random.

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It's Aux Power Supply time.

With some of the modules using more power rails than you can poke a stick at (you need more sticks) some form of power sequencing will be required, not so much because the power rails need to all come up at exactly the same moment in time but for that fault scenario when one of the rails outputs a voltage out of spec which could cause current to take the shortest path through the input protection diodes of some ICs and weird stuff could happen.

A simple solution to this is to use a window comparator circuit (LM393) for each rail and some P-channel MOSFETs paired with a delay circuit (CMOS 555 or some monostable using logic gates) and a cheap voltage reference (TL431 or LMV431).

It has been previously mentioned that there were going to be two AUX power supply modules, they're now going to be merged into one...

That turned out to be not such a good idea. I want to be able to use the boards for other things and not having them only 20% populated.

One more thing worth mentioning is the use of a 74HC138 3-to-8 line decoder to drive the CS pins of the SPI peripherals on the boards that use them, which means I can use only one 74HC595 where I would have otherwise needed two and adding an extra level of idiot-proofness.