Does parallel RGB LCD need termination?

[stmdude]

I've designed a board with a 24bit parallel RGB LCD attached to it. However, I'm getting some strange artifacts on it (high-speed flickering, looks like it's an interlaced CRT).

I've verified the timings with an oscilloscope, and they match what the datasheet says.

Looking at the pixel-clock signal, there's quite a bit of over and under-shoot (5.1V PtP, should be 3.3V ideally) as well as a bit of ringing.

The board is impedance controlled to 50ohms (DDR3 on the same PCB works fine at 528MHz), so I'm wondering if I need termination resistors? Anyone with some experience with parallel LCDs?

(Pixel-clock is at 9MHz, so it's not that fast...)

[capt bullshot]

Your symptoms point in that direction. I don't know if termination is required in general for those things, for sure it depends on your ground plane and trace lengths. I'd give it a try with an AC coupled end termination for the clock signal, or a source point series termination. One of these usually cures the ringing. 9MHz isn't that fast, yes that's true, but these modern CMOS chips put out quite fast edges, and  the inputs might be sensitive to ground bouncing or noise at way much higher frequencies, causing the flickering.

Configuring the micro's output pins to a less powerful drive / slower edge might also help (many modern uC's have these settings, and often default to fastest, sometimes slower is better).

[rstofer]

FPGAs tend to have very fast edges and when I wanted to talk to a Compact Flash, I had to add 330 Ohm series resistors to knock down the ringing.  Many development boards now come with the resistors.  I think they were added to prevent short circuit damage but they also help with ringing.

You might try just a simple series resistor but adding them into a completed board will be pretty grim.

[stmdude]

Configuring the micro's output pins to a less powerful drive / slower edge might also help (many modern uC's have these settings, and often default to fastest, sometimes slower is better).

Thanks for reminding me of that (amazing how you forget some things when you focus too much on the problem). Drastically lowering the slew-rate and drive-strength helped quite a bit. I'm down to 3.6V PtP, and negligible ringing.

The display got a bit better, but still not good enough (tm). However, with the now less than impressive rise/fall times, I might actually need to length-tune the LCD signals. Oh well, another revision was planned anyways.

[Siwastaja]

9 MHz is completely irrelevant - only the edge rate matters. Even 1Hz pulses can be problematic. If this is a single point-to-point, use series termination (at the source pins) to your 50 ohm controlled impedance. 33R would probably be close enough, when added up with the FPGA's CMOS source/sink resistance. You can use higher resistance if the speed is not an issue, as it probably isn't.

9 MHz, however, is a relevant number when it comes to length tuning the parallel bus - no need to go for it.

Clock polarity issue is one possible cause.

[T3sl4co1l]

If you're getting overshoot and ringing, it's not impedance controlled, simple as that.   Add termination to address that.

Tim