Hi group,

There has been a lot of interest in the forum on building constant current loads. One of the frequent questions that is asked is how do I stop my load from oscillating? or how do I choose the components around the op-amp to obtain stability. Other popular questions are how does the MOSFET gate capacitance impact my design.

I am going to share some analysis on a constant current load using LTspice. The analysis is done in the frequency domain. The goal is get reasonable bandwidth while being stable. For stability the phase shift has to be less than 180 degrees when the gain is greater than 1 (0dB). The loop bandwidth and phase margin are figures of merit for a control system.

Since the gain of a control loop is the product of the gains of the individual stages, we can build the control loop from the building blocks used in the circuit.

**Power Stage**I could start by trying to model the power stage like this:

And I get the following result, which is useless:

The reason that the result is useless, is that the MOSFET has not been biased to the correct operating point.

The easy way to correct this is add an automatic Bias generator. This will servo the gate voltage to the correct operating point:

The result from this circuit are:

I can also reduce the MOSFET to a voltage controlled current source and its Gate-Drain and Gate-Source Capacitors:

If I model the correct values of transconductance, Crss and Ciss I get the same results. I do not need a bias circuit, because this model has no gate threshold voltage:

I now have a model that I can explore the effects of the gate capacitors directly. The DC gain is determined by the value of the source and the transconductance of the MOSFET. There is a pole formed by the gate resistor and input capacitance of the MOSFET.

**Op-Amp Circuit**An op-amp is used to stabilize the load current. Typical this circuit it used:

The results show a single pole. It important that the op-amp has sufficient gain bandwidth product (GBW) so that the op-amp does not limit the bandwidth.

The circuit can also be reduced to this:

The results for this circuit are:

You can see that the real circuit, with the op-amp, has the same characteristics as the simplified model. The characteristics are determined by the resistor and the capacitor.

**Open Loop Model**The two previous models can be placed in series to obtain the control loop response (oops!! replace R5 and L1 with a short

):

The loop model response is:

This is great and the control loop is stable. What would happen if there is some inductance in the leads between the load and the power supply being tested?

The results indicates that the circuit is very close to oscillating. There is very little phase margin when the gain is 0dB. We could reduce the gain, but this would also reduce the bandwidth of the control loop.

We could add a damping circuit as shown in this model:

The result is:

The potential for oscillations resulting from inductance on the leads to the load has been significantly reduced.

**Closed loop Modelling**The loop gain can be measured with the control loop closed, by placing the disturbance source in the feedback path. The signal can be measured on either side of the disturbance source to determine the loop gain.

The results of the closed loop model are:

To be continued....

Jay_Diddy_B