Author Topic: EMC design rule check  (Read 4762 times)

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Offline pix3lTopic starter

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EMC design rule check
« on: December 05, 2016, 03:59:29 pm »
Dear masterminds,

I'm currently facing a challenge: I need to get the device I've been developing through EMC compliance testing which turns out to be a lot harder than with previous products. After a lot of debugging on-site I would like to try to use EMC design rule check software. The suites I've found so far are: EMIStream, CST Boardcheck, EMSAT Viewer and IQ-Harmony.

Does anyone have experience with these tools? How useful and accurate are they? And what kind of price tag do I need to think of?

PCB was designed using AD, so the suite would need to be compatible with AD.

Cheers,
Pix3l

 

Online T3sl4co1l

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Re: EMC design rule check
« Reply #1 on: December 05, 2016, 06:39:18 pm »
I can't even begin to imagine what an "EMC design rule check" program might do.  (Separate its users from their money, perhaps?)

Not having used or seen one myself, mind.

On the other hand, I'm compatible with AD, and am capable of synthesizing data from disparate sources, including accumulated knowledge, datasheets, program code and layout. ;D

Tim
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Offline pix3lTopic starter

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Re: EMC design rule check
« Reply #2 on: December 05, 2016, 07:21:03 pm »
Thank you Tim for your answer.

Of course, hiring an EMC expert is also an option. And I'm aware of the fact that there is no software that will tell me right away - with the click of a button - where my issue is.

I was just wondering if anyone here used such a tool and if they found it insightful.
 

Offline nctnico

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Re: EMC design rule check
« Reply #3 on: December 05, 2016, 07:44:11 pm »
Perhaps you could elaborate a bit more on what the problem is. Emissions? Susceptibility to external interference? Surge? ESD? Do you need a lot of improvement or just a little. In my experience fixes for EMC problems can be very specific for the design.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline AndyC_772

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Re: EMC design rule check
« Reply #4 on: December 05, 2016, 07:54:00 pm »
I can't even begin to imagine what an "EMC design rule check" program might do.  (Separate its users from their money, perhaps?)

Not having used or seen one myself, mind.

I wondered exactly the same. There was me thinking that designing for EMC was an engineer's skill, requiring knowledge, experience and a degree of empirical testing, but apparently the machines are coming for us after all.

Offline nctnico

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Re: EMC design rule check
« Reply #5 on: December 05, 2016, 08:09:03 pm »
I can't even begin to imagine what an "EMC design rule check" program might do.  (Separate its users from their money, perhaps?)

Not having used or seen one myself, mind.
I wondered exactly the same. There was me thinking that designing for EMC was an engineer's skill, requiring knowledge, experience and a degree of empirical testing, but apparently the machines are coming for us after all.
I took a quick peak at the programs and it seems they do analysis of board designs where it comes to power planes, potential resonators, signal integrity. However unless you really screw a layout up I don't see that translating into severe problems when it comes to failing emissions or immunity testing during an EMC compliance test. What usually kills passing an EMC test is related to the wiring.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Online T3sl4co1l

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Re: EMC design rule check
« Reply #6 on: December 05, 2016, 11:12:56 pm »
Planes and resonators and integrity are one thing, but those can be as much functional as EMC.  And such is hardly a true measure of "what u hear" with an antenna at 3 meters!

Regarding engineers, certainly, some day we will be out of a job.  Until then though, :)

Tim
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Offline pix3lTopic starter

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Re: EMC design rule check
« Reply #7 on: December 06, 2016, 08:23:08 am »
Hi all,

The problem is in the radiated emissions (in the sub-200MHz domain) of the device. We're trying to get it below the CE/FCC class B limits (which is 40dBuV/m for the lower frequencies). And many hours of testing in the certification lab have been spent testing, modifying, retesting etc. This is what lead me to my question.
 

Offline AndyC_772

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Re: EMC design rule check
« Reply #8 on: December 06, 2016, 09:17:35 am »
The problem is in the radiated emissions (in the sub-200MHz domain) of the device.

It usually is!

Harmonics of clock frequencies? With a nice, rounded hump towards the bottom end?

How much experience do you and your team have in designing for EMC? Can you respin the PCB or do you really need a retro-fit patch for the first units?

Offline nctnico

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Re: EMC design rule check
« Reply #9 on: December 06, 2016, 01:22:17 pm »
Hi all,

The problem is in the radiated emissions (in the sub-200MHz domain) of the device. We're trying to get it below the CE/FCC class B limits (which is 40dBuV/m for the lower frequencies). And many hours of testing in the certification lab have been spent testing, modifying, retesting etc. This is what lead me to my question.
Do you have a graph of the frequency spectrum? The usual approach is to use a spectrum analyser with a H field probe (also easely made from a piece of coax and some heat shrink tubing) and 'scan' the PCB to find the source of the specific frequencies. From there you can modify the circuit to reduce the output. If you hold the H field probe in the same orientation then the reduction you'll see with a simple DIY probe will be very much the same as the reduction you'll see in the measurements at the certification lab. If you know how much the frequencies are over the limit you'll know how many dB you'll have to reduce the emissions at that frequency.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline pix3lTopic starter

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Re: EMC design rule check
« Reply #10 on: December 06, 2016, 01:58:02 pm »
Indeed harmonics, 3rd harmonics.

We can respin the board but of course we want to know fairly certain that this will eliminate our problems. So modifying our current small batch is the approach for now. Not a problem since we use mostly 0402 and TQFP/QFN packages.

And we have a graph of the spectrum and some small probes which we can use (these: http://www.saelig.com/product/M00154003.htm ). We used these with an Aaronia spectrum analyzer but some frequencies we could just not find with this setup
 

Offline AndyC_772

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Re: EMC design rule check
« Reply #11 on: December 06, 2016, 02:50:58 pm »
We can respin the board but of course we want to know fairly certain that this will eliminate our problems. So modifying our current small batch is the approach for now. Not a problem since we use mostly 0402 and TQFP/QFN packages.

OK, but what if your problem is caused by, say, the lack of a series terminator in a high speed signal? Or a mismatch between the two halves of a differential pair?

There's plenty of remedies which are quite easily applied to a new PCB, but which are difficult if not impossible to retro-fit in a way which maintains the desired high frequency performance.

It's hard to say much more without seeing your specific schematic and layout.

Offline pix3lTopic starter

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Re: EMC design rule check
« Reply #12 on: December 07, 2016, 08:30:24 am »
Thank you Andy for your reply.

The highest clock speed on the board is 27.12MHz (double of NFC carrier wave), so a missing termination could be the case but it's not really a high-frequency board.

I don't think that I can disclose the schematics/layout
 

Offline nctnico

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Re: EMC design rule check
« Reply #13 on: December 07, 2016, 09:32:04 am »
Can you show the frequency graph?
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline pix3lTopic starter

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Re: EMC design rule check
« Reply #14 on: December 07, 2016, 03:39:45 pm »
Here is the graph:
 

Offline Neilm

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Re: EMC design rule check
« Reply #15 on: December 07, 2016, 07:42:45 pm »

The highest clock speed on the board is 27.12MHz (double of NFC carrier wave), so a missing termination could be the case but it's not really a high-frequency board.


It is not the clock frequency that is the issue - it is the speed of the edges. A fast transition will easily have frequency components in the hundreds of MHz. The frequency just says how often they arrive.
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Offline nctnico

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Re: EMC design rule check
« Reply #16 on: December 07, 2016, 08:58:51 pm »
To me the graph looks like problems from a flyback switching power supply because it shows several frequency peaks with no harmonic relation. Perhaps increasing the gate resistor (or inserting a small resistor in series with a boost capacitor) or putting a ferrite bead in series with the rectifier diode to kill the reverse switch-off current may help but first you'd need to measure in the power supplie(s) using an oscilloscope and FFT to see where the problem is generated. Once the source is located I have had succes with simulating the offending parts of the circuit and see what kind of solution works best.

And how is the rest of the EMC test setup? Any cables coming from the device? You can put a ferrite clamp around the cable where it reaches the floor. When it is a close call this could get you a few dB extra. Some lab techs don't care about this but the cable can be influencing the measurements while it is not part of official test setup.
« Last Edit: December 07, 2016, 09:04:36 pm by nctnico »
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline pix3lTopic starter

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Re: EMC design rule check
« Reply #17 on: December 09, 2016, 04:09:04 pm »
Had another day in the lab yesterday and contrary to earlier conclusions the source of the waves was the peripheral device which we use to have our device be operating in its normal operating mode....

@Neil: the rise/fall time of the 27.12MHz oscillator is between 3 and 4ns and the trace runs for about 1.4". So if you compare this to the rule of thumb of 2"/ns then this signal should be fine

@Nico: we don't have any switch mode power on the board, only low dropouts..

Thanks all for your answers :-+
 

Offline Jeroen3

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Re: EMC design rule check
« Reply #18 on: December 09, 2016, 04:20:57 pm »
Such EMC problems can be as simple as driving a LED with an overexcited gate. (eg: flanks too steep)
 

Offline Neilm

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Re: EMC design rule check
« Reply #19 on: December 09, 2016, 05:28:15 pm »
One easy way to finding these sorts of emission problems is with a spectrum analyser and a small antenna. Even an antenna made from a bent paper clip can allow you to scan the board for where the signal is at a peak.
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