Ethernet MII routing and jumping layers

[jc101]

I have a project with a 144 pin PIC32 running multiple serial interfaces, USB, SD Card, and also a LAN9303 switch.  A fair number of pins on the PIC are also used for I/O and driving some RGB LEDs (as status indications so only R, G, or B are on at any one time) too, so it's reasonably busy with most pins in use.  Communication between the LAN9303 and PIC32 is over MII.  It isn't a huge board (100mm x 90mm) and I'm using a 4 layer PCB with a stack of Sig, GND, PWR, Sig.  It will be in a metal enclosure once complete.

Owing to the pinout on the PIC I need to look at routing the MII signals on the bottom of the board.  The RX and TX ethernet clocks I can route on the top layer, so adjacent to the GND plane.  For the MII signals though I need to go via the bottom layer even if only to swap the order of the tracks, do I need to add stitching caps at the crossing points as I've altered the reference plane from GND to PWR?  If I do, do I need one per signal or if I group the layer changes will one place (within 5mm-10mm) per group be enough?

There isn't a huge number of pins to break out, but all the interconnections looks like it will mean quite a bit of hopping between layers once the faster signals have been put down.

[ejeffrey]

Yes, you need stitching caps whenever a fast edge signal changes reference plane.

You don't necessarily need one per signal if there are several signals close together.  What you need exactly depends on your signals, but you can look at it this way:  the transition is mostly the same as what happens at the sending IC when it switches.  So your bypass needs are comparable to what the MCU or PHY needs -- generally far less than 1/pin.

[rs20]

Does this apply to differential signals too? In principal, the caps would be carrying virtually zero current, so they may as well not be there, right? (Fully aware that I'm probably wrong.)

[T3sl4co1l]

I wouldn't worry about it.

1. MII isn't terrifyingly fast.  It's just a CMOS signal.  Routes much shorter than the edge time (a few nanoseconds?) do not need termination; long routes can be source terminated (if point-to-point routed, which is likely the case here).
2. With a large amplitude, and high threshold, signal quality isn't a big priority.  (Do prioritize CLK quality, though.)
3. Parallel planes are great, to the point where capacitors tend not to have much local effect.  You can dot around a dozen bypass caps and probably not worry about local bypass anywhere (ah, but better safe than sorry, of course -- you can always test DNP's later, if time allows).

Consider this: an edge of 1ns fits within a ~20cm span.  The image current, of the wave front traveling along the trace, over the ground plane, and dipping (along the via) through a hole in the plane, and out the other side, acts like an impulse current applied between the edges of the ground plane holes.  That current spreads out, radially, in the space between planes.  As it goes, impedance starts low (10s ohms) and drops proportionally with distance.  By the time that wavefront is 5 or 10cm away (reaching its peak current flow), the VCC-to-GND impedance is perhaps single ohms.  For a peak current on the order of (delta 1.6V) / (100 ohms) = 16mA, expect a peak VCC-GND voltage, as measured at the edge of the holes in the planes (assuming you could probe such a location!), on the order of (16mA) * (single ohms), or well under 100mV.  With a ~1V noise margin, the impact of a single via is negligible here.

(Assuming a ~100 ohm trace, source terminated, 3.3V supply.  So the initial wavefront is 1.65V, followed by the 1.65V reflection, for a total 3.3V swing.)

Now, if you have, say, low noise, sensitive analog or RF circuitry right beside here -- you may need additional bypass, or even a split plane.  But for just digital, medium speed, it's very noncritical.

Tim

[Ice-Tea]

Is the power plane continuous and shared between the swich and uC? In that case, it doesn't really matter. For AC, the signal won't care if it is GND of, say, a shared +3V3 plane.

[jc101]

Thanks for the replies, all makes sense.

Is the power plane continuous and shared between the swich and uC? In that case, it doesn't really matter. For AC, the signal won't care if it is GND of, say, a shared +3V3 plane.

Yes it's a single 3.3v PWR plane used by everything on the board, with two islands for the two Ethernet ports TX created via a FB and caps as per the spec for the LAN9303.  No signals cross these islands which run from the PHY up to the magnetics.  There is some 5v too for the USB port.  The board also has a DC-DC converter to take the 12v in to 5v, then an LDO for the 3.3v.

Now, if you have, say, low noise, sensitive analog or RF circuitry right beside here -- you may need additional bypass, or even a split plane.  But for just digital, medium speed, it's very noncritical.

No all digital and no RF, just a real pain as the even after moving things around with PPS on the PIC32 a fair number of things need to bounce between the top and bottom to get to where they are needed.  I've kept the ethernet CLKs on the top layer though.

[T3sl4co1l]

Last board like that I routed, there was probably an average of three-ish vias per trace, for the buses leaving the microcontroller.  This includes MII (or RMII, I forget), external SDRAM, Flash and LCD (16 bit port), and a couple ports worth of general purpose signals (slow analog and digital).

No signal quality problems.  There was some spooky behavior with the memory and LCD, which was traced to shitty code generated by the tool chain and HAL library.

Probably no EMC problems due to anything I had control over, either; unfortunately the one thing I did not, was the connector to the LCD board, which didn't carry enough ground connections.  Between this, and the lack of grounding (e.g., metal spacers and screws) between boards, there was a nice spike at 250.0MHz in radiated.

Tim