I get that the switch + capacitor works as a simulated resistor where R = 1/Cs*Fs
So I see there he has 1/(0.0000000001*1000) and 1/(0.00000001*1000) (10:1 clock ratio ) =
10 meg to 10K = gain of 1000
I built this circuit up, though I did not have the same parts on hand, so I used a 1uF and a 10nF
1/(0.00000001*1000) = 100k
1/(0.000001*10000) = 100
So the simulated resistances are alot smaller but the ratio is the same.
I used a 10nF integrator capacitor (just like the app note) and TTL clocks using two function generators (1k and 10k Hz).
I am using a LT1677 op amp with this circuit
I also am using the non inverting form of the circuit (swap pins 7A and 6A (datasheet mentions 8A incorrectly, but I cross checked with the LTC1043 datasheet which has it right).
However, this circuit won't work. It just slowly counts up to the + supply rail, the frequency adjust stage does not matter and if I disconnect the 1KHz clock it outputs close to zero, if I connect the 1KHz clock it slowly moves up to + rail on the output.
Why did the original circuit use such high resistances and a JFET op-amp? And how about the integration capacitor ?
*I used all polypropylene capacitors