Extremely fast analogue switch

[lazaraza]

Dear EEVblog community,
I am a lone physicist lost in the sea of microelectronic, abound to design a device where one of the most critical component is an extremely fast analogue switch. It must switch OFF/ON a signal from a Photo-Multiplier Tube (PMT) the ON/OFF time duration must be at most 200 ps. So far the closest match is Micrel's SY56023R which has delay (SEL-to-OUT) of 350 ps. Another potential candidate is MAXIM's MAX3841, but there it is unclear what the ON/OFF timing is. Presumably it will be better than SY56023R since the propagation delay is twice shorter in MAX3841.

Could you please advice me on the current options as well as on any other switch I may use?

ps. I refrain from posting links to the corresponding components since am unaware of the forum's policy toward links, but simple google search should give you all the related info.

[nctnico]

Perhaps it is better to describe your circuit. Maybe there is a better overall solution for what you are doing without difficult or impossible parts. BTW: there is no problem at all with placing on-topic links.

[amyk]

Those are for digital signals, I don't think they'll work well with analogue since they act as buffers.

As for linking policy, read a few more threads here and you'll clearly see what it is...

[tggzzz]

Describe your problem and then mention your solution - there might be other solutions.

Distinguish between the characteristics of the signal being switched and the signal doing the switching. Define the characteristics in terms of analogue/digital/RF, signal levels, upper/lower frequencies.

Distinguish between latency and bandwidth, e.g. how long it takes before something is on/off vs the time period for which it is on/off.

[Marco]

You seem to want a sampling gate, not a switch per-se. Unless the system behind the switch has 100 GHz range bandwidth (in which case the switch will need that same bandwidth, as will the rest of your circuit ... good luck).

Are you sure simply using a sampling scope with the PMT won't provide you with what you want?

[lazaraza]

Hi to all, and thanks for the fast response!

Now I will try and elaborate on your comments, but first of all please excuse my lapsus with the analogue switch, what I need is just a switch, but extremely fast.

The problem I face is the measurement of the time duration between the signals from two PMTs. The resolution of the measurement should be better than 300ps with a range of 0.3 to 10 ns. I address this problem by designing a simple sample and hold (SH) which can provide resolution of few tens of ps in the range 3 to 20 ns. The PMT signals are fed to a Schmitt Trigger (ST) which gives PECL as output with RT/FT of 90 ps and the whole system downstream is designed for PECL signals.

Since the lower limit of the SH measurement range is too high, the signal from the second PMT will be routed via a programmable delay to add 3 or more ns to compensate for the slow turning on of the SH. The PECL signal from the ST is split in two using ADCLK925 from Analogue Devices, one part of the signal is used to control the master-switch in question. The master switch decides which signal will be routed via the delay and as such is the most critical part of the design, any time duration which is smaller or comparable to the reaction time of the master-switch will lead to a race condition and undefined result.

Ah, and did I mention, my detector will have several tens of thousands such channels (PMT pairs) so using of the readily available of-the-shelve products will make the costs prohibitive, so I need a really CHEAP solution 

Marco, I will have to read further on about the sampling gates to understand if I can use them. Will come back at that once I am better prepared.

[sarepairman2]

this is an interesting topic and I have nothing to add at this time but I am wondering, were you brutalized by newsgroup administrators or something?

[sarepairman2]

If I understood correctly, you want thousands of 200ps S&H switches? At this quantity, a more sensible choice is to design your own switch. Both imag.fr and europractice offer low volume ASIC prototyping service. The MPW NRE cost averaged down to 1000 chips will be below $1.

Such super simple complexity design can be done using open source IC tools, such as Electric or Magic. Of course, you need an IC engineer PhD or at least MSEE in your team.

The upside is you can save a LOT of money in components, and you can publish another paper.

For what I know, you can either use SiGe process to design a transmission gate switch, or you can design a true switch based on MEMS technology (which Agilent uses to build their 20GHz scopes).

Both technology can be prototyped below $1000. Once design gets proven, mass production of IC is almost free.

PS. I'm not crazy.

Are you saying that I can design an asic and have these guys give me a working chip for 1000$?

[tggzzz]

I suspect this is a relatively standard HEP problem. How have other people solved it?

Have a look at time-to-digital converters, e.g. http://www.ti.com/lit/gpn/tdc7200
Have a look at digital delay lines, e.g. http://www.onsemi.com/PowerSolutions/product.do?id=NB6L295
Google for those terms
Use a high-speed comparator rather that a schmitt trigger.

[nctnico]

Programmable delay lines... switches.. routing.. sounds complicated. How about feeding the signals into FPGAs and have them measure the delay? You can use a string of logic elements to create a delay line with multiple outputs; these get sampled using a clock (say 200MHz) so you know the position of the edge and determine timing from there. This takes constant calibration but you can expect to get your required resolution. Google 'spartan6 delay line resolution' for more information on a time to digital converter.

[German_EE]

Where do you work? Daresbury Lab, Rutherford Appleton or JET?

[lazaraza]

Hi blueskull,
Thank you for your advice
Believe it or not, I was considering ASIC as main route for the mass production.
However, our project is at a stage where we need to prove the concept that we can create a circuit that can deliver the performance we need. I have inherited this task few months ago from an EE colleague who retired so I found myself deep in the blue silicon sea. Now I have the time by December to come out with working prototype... of some sort 

@tggzzz,
thanks for the insight mate! It is more or less a standard HEP problem short of the lower range and the scale of the project. All of the HEP solutions are too expensive, trust me I'm from this community.
The TI chip you showed me is essentially what I have already designed and soon will test, if test fails will try the TDC7200.
However this doesnt solve the problem of routing the signals and the master-switch I need
And yes, I use comparator with a hysteresis instead of ST, just said ST to be more clear.

[daqq]

I agree with the Time-To-Digital converter advice - this is ideal for measuring such stuff, and I doubt that you can get better parameters. You can get such converters from various vendors with various parameters (resolutions of 20ps exist, which boggles my mind) and they will have a greater repeatability.

If you don't mind my asking, what are you designing? Sounds sciency with particle accelerators on top

[f5r5e5d]

XOR?

or duplicate delays, S/H - pick the output for the order of pulses?

the signal/problem description in EE terms is still fuzzy to me - you have enough S/N to give up all of the PMT information by just Schmidt triggering on the edge(s)?

do you have other time signals, arming/gate/reset - what repetition rate...

[Marco]

How about using the CTMUs of two PICs instead?

I assume it will need a little more delay between CTEDG 1 and CTEDG 2 than 300 picoseconds as well for accurate measurement. So, measure the time between signal 1 and delayed signal 2 and the time between signal 2 and delayed signal 1, no need to switch anything AFAICS. The two results (or absence of a result for one of them) will allow you to determine which came first.

[nctnico]

@tggzzz,
thanks for the insight mate! It is more or less a standard HEP problem short of the lower range and the scale of the project. All of the HEP solutions are too expensive, trust me I'm from this community.
The TI chip you showed me is essentially what I have already designed and soon will test, if test fails will try the TDC7200.
However this doesnt solve the problem of routing the signals and the master-switch I need

What must the master switch do with the signal?

[T3sl4co1l]

Sounds like photon coincidence counting or something??

A high frequency multiplier, e.g. diode ring mixer, might do.  You might also consider band-pass filtering it and looking at it in terms of RF correlation in the GHz (since I guess you're looking at sub-ns rates).

Tim

[Marco]

What must the master switch do with the signal?

He wants to switch the signal from the lagging PMT, which can be either one, through the delay line.

As I said, I think it would make more sense to simply have two delays and perform two time measurements and throw away the one which wasn't relevant (based on the results you can determine which one that was). The cost of a single PECL Schmitt trigger can pay for a lot of PICs (which can do 50ps resolution in single shot mode according to this). Let alone all those other pricey components he mentioned.

PS. a custom ASIC is indeed interesting too if he can find someone with the expertise, you would be able to put a lot of channels on a single chip and academic shuttle services aren't that expensive.

[LaserSteve]

I would be talking to Jim Thompson at Analog Innovations  (ASIC/IC Design)  or Phil Hobbs at Electro-optical.net , maybe John Larkin at Highland Technology...

Get some one who has done this before, or use time to digital, ring mixer, sampling gate etc...

You really need a specialist or two if your building 1000 pairs.

Steve

[Someone]

However, our project is at a stage where we need to prove the concept that we can create a circuit that can deliver the performance we need. I have inherited this task few months ago from an EE colleague who retired so I found myself deep in the blue silicon sea. Now I have the time by December to come out with working prototype... of some sort

The companies serving this industry have high prices because there are so few customers, some of the products might only be made for one or two installations. Position sensitive detection is relatively mature with TDC techniques allowing MHz peak count rates, if you want to go with slower count rates then the analog ramp techniques are readily applicable with a slow clock and simple electronics.

Are you interfacing with an existing storage/binning system or is that to be designed and built as well?

[jwm_]

Hi to all, and thanks for the fast response!

Now I will try and elaborate on your comments, but first of all please excuse my lapsus with the analogue switch, what I need is just a switch, but extremely fast.

The problem I face is the measurement of the time duration between the signals from two PMTs. The resolution of the measurement should be better than 300ps with a range of 0.3 to 10 ns. I address this problem by designing a simple sample and hold (SH) which can provide resolution of few tens of ps in the range 3 to 20 ns. The PMT signals are fed to a Schmitt Trigger (ST) which gives PECL as output with RT/FT of 90 ps and the whole system downstream is designed for PECL signals.

Since the lower limit of the SH measurement range is too high, the signal from the second PMT will be routed via a programmable delay to add 3 or more ns to compensate for the slow turning on of the SH. The PECL signal from the ST is split in two using ADCLK925 from Analogue Devices, one part of the signal is used to control the master-switch in question. The master switch decides which signal will be routed via the delay and as such is the most critical part of the design, any time duration which is smaller or comparable to the reaction time of the master-switch will lead to a race condition and undefined result.

Ah, and did I mention, my detector will have several tens of thousands such channels (PMT pairs) so using of the readily available of-the-shelve products will make the costs prohibitive, so I need a really CHEAP solution 

Marco, I will have to read further on about the sampling gates to understand if I can use them. Will come back at that once I am better prepared.

I am crossing my fingers that you are a super hard-core amateur astronomer that decided to one up everyone and build a private neutrino observatory in your underground pool  No waiting for anyone else to tell you when a supernova goes poof. Just because that would be awesome. My friend from school worked on the super-k detector, I never had a chance to visit it though.

[Marco]

if you want to go with slower count rates then the analog ramp techniques are readily applicable with a slow clock and simple electronics.

Since he only needs 300 ps resolution it seems a lot of effort to replicate something Microchip put in a nice package with a free microcontroller, you'll have a hard time even beating them on price.

[Someone]

if you want to go with slower count rates then the analog ramp techniques are readily applicable with a slow clock and simple electronics.

Since he only needs 300 ps resolution it seems a lot of effort to replicate something Microchip put in a nice package with a free microcontroller, you'll have a hard time even beating them on price.

I've not seen any detailed analysis of the TDC performance of those parts but they may be a solution for low count rates, getting accuracy into the 100's of ps might be solvable with online calibration between counts. You may not have worked with this sort of equipment but the signal conditioning and connectors will dwarf the price of a micro and there may be rad hard considerations when selecting parts.

[daqq]

Are you making something like this maybe?

There are very few details available though.

[nctnico]

What must the master switch do with the signal?

He wants to switch the signal from the lagging PMT, which can be either one, through the delay line.

And then? What is the final goal? Does that switch need to measure the time differences? Some other processing?

If the goal is to measure the delays between pulses and use low cost (off the shelve) hardware then I'd look at CERN's White Rabbit project and their FMC carrier boards. These are commercially available and allow synchronising FPGAs up to 10km apart within picoseconds. For a demonstrator a PCI express/stand alone FMC carrier board can be used with a dedicated FMC card. For a final solution the same FMC card design can be used on a larger FMC carrier to get 50 to 100 channels on one carrier. These carrier boards can be mounted in a standard chassis. Because the time synchronisation system is based on network technology everything has a 1Gb/s ethernet connection to transport data. At the end a PC can collect the data and process it. The only thing that needs to be dedicated is the PMT interface but it seems at least Nikhef (nikhef.nl) has already build such an interface.

CERN uses the White rabbit protocol + FMC carrier boards to correlate the time in various experiments. One of my customers uses it for an agressively priced (=cheaper than the competition) distributed data acquisition system (I did the FPGA design for it).