EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: Chris Wilson on February 17, 2017, 02:37:36 pm
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How do I calculate what the maximum input capacitance this FET driver chip will drive please? I am experimenting with different voltage driven Class D push pull PA MOSFETs and I suspect my two in parallel per side may be getting near the limits of its driving abilities.
The driver chip is an IR2110 and its data sheet is at http://www.futurlec.com/Others/IR2110.shtml (http://www.futurlec.com/Others/IR2110.shtml)
I have Googled but see no obvious way of working out if chip A will drive MOSFET's B.
For example, will the above driver IC happily drive 2 per side in parallel, in a push pull circuit, of these devices?
http://www.st.com/content/ccc/resource/technical/document/datasheet/fb/f2/81/40/ca/19/43/e0/CD00222640.pdf/files/CD00222640.pdf/jcr:content/translations/en.CD00222640.pdf (http://www.st.com/content/ccc/resource/technical/document/datasheet/fb/f2/81/40/ca/19/43/e0/CD00222640.pdf/files/CD00222640.pdf/jcr:content/translations/en.CD00222640.pdf)
Thanks
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The best spec to use is "total gate charge", Qg, from the MOSFET datasheet. Peak current is then Qg/t, where Qg is in nanocoloumbs, t is the transition time in nanoseconds and Ipk is in amps.
This assumes the gate is driven across a specific voltage swing (usually 10V for MOSFETs).
For a Class D audio application the transition time is usually fairly leisurely - 200ns is more than fast enough and shouldn't cause too much problems exciting stray resonances, but as long as 1us is fine as long as SOA isn't violated (modern MOSFETs don't like to operate in the linear region, ie - when transitioning from on to off or vice versa).
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Just to add, this is an RF amp and the FET's run at 137kHz, 50V at about 20 to 25 Amps at the moment, on FET's that are a bit near their limit.
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Some drivers are tested "quasi-static" by using a fuckoff big cap load like 0.1uF, which takes tens of microseconds to charge and discharge. The rate of charge shows current output. This is safer than measuring the current by trying to hold the output pin at fixed voltages, which would dissipate huge power, destroying the chip.
So the answer is almost certainly: "all".
But a simple yes/no is the wrong question to ask. That misses the deeper truth: more gate charge takes longer to drive.
IR2110 is pretty weak, so it will drive those fairly slowly. But in your application, that's probably not a big deal.
I might go with a TC4429 or something like that, personally.
Tim
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Just to add, this is an RF amp and the FET's run at 137kHz, 50V at about 20 to 25 Amps at the moment, on FET's that are a bit near their limit.
Okay, well, if you are driving the MOSFETs at 137kHz to get a 137kHz output then the previous advice applies [edit - delete irrelevant commentary on class of operation since I'm not entirely sure whether 137kHz is modulated or not].
So, for example, the MOSFET you referenced earlier has a Qg of 100nC and the usual rule of thumb for smps design is to make the transition time (ton or toff) 1% or less of a switching period, or 73ns in this case. 100nc/73ns = 1.4A, which is within the capability of the IR2110 you also referenced earlier.
But if this is a true Class-D amplifier, in which a lower frequency signal (ie - 137kHz) PWM's a higher frequency carrier followed by low-pass filtering to recover the modulating signal, then your switching frequency might need to be 600kHz or more to allow for a simple LC low pass filter on the output. That means a transition time in the sub-10ns range, which will require a peak current that will likely exceed the ampacity of the gate bond wires and/or die metallization, while the stray inductance of the package alone will conspire to prevent slewing that much current that quickly with just 10V of drive.
It is possible to drive the gate resonantly, or use a matching network to transform the impedance, but this is pretty advanced stuff.