Could someone explain how this IC is being used please?

[Chris Wilson]

Attached is the schematic of a frequency doubler. It takes a 136kHz input and doubles it to give a 472kHz output. I am not sure how the IC and the two transistors function. The IC is a 74HCT4046 and its data sheet is available here: http://www.farnell.com/datasheets/66679.pdf?_ga=1.131595913.701848857.1475733716

Finally, as a beginner I am unsure about the note on the schematic regarding a 51 Ohm resistor, I assume it's for impedance matching, but what I don't understand is why it would be a series resistor at the doubler's output, but a parallel one on the Class D amp input. Thanks

[Benta]

There's not too much to understand.
The frequency doubling happens at the input transformer through full-wave rectification.
The 4046 (which is a PLL) is misused as amplifier/buffer only to drive the bipolar buffer stage. If you look at the datasheet, pin 14 is the input to the preamplifier ("self bias circuit"), the PC1 is just an EXOR gate with the other input tied to V+.

Concerning the resistor notes: the normal way of matching impedance, in this case 50 ohms, is a series resistor at the sending end and a parallel resistor at the receiving end.

[Andy Watson]

Benta beat me to it!

If you want 272kHz, why not generate it directly?

[Chris Wilson]

Thanks for the fast reply!


The PA needs a square wave input, I am guessing the (as you say, misused 4046) does this squaring up? Despite what the build notes say should I run a series resistor at the output of the doubler *AND* a parallel one, which i have already, at the amp input? I am having issues with glitches at the amp input, and i am testing with 4 feet or so of RG-58 co-ax between doubler output and amp input. When a signal ceases I sometimes see a lot of sudden noise and this signal stays high for a few hundred uS, which does the Class D push pull FET's a mischief. Here attached is the PA circuit from the same designer.

[Chris Wilson]

Benta beat me to it!

If you want 272kHz, why not generate it directly?

The issue here is the way WSPR digital mode software works, the software is designed to work with a set frequency for each band, apparently unless I double the frequency  of the output of the exciter which has the WSPR signal imposed upon it, and let the push pull driver of the Class d amp divide by 2 again, WSPR won't work. This is documented and has caught others out who tried just running the exciter at 272kHz. PITA, and I don't fully understand why WSPR needs this, but there you go. Thanks Andy!

[PA0PBZ]

Benta beat me to it!

If you want 272kHz, why not generate it directly?

The issue here is the way WSPR digital mode software works, the software is designed to work with a set frequency for each band, apparently unless I double the frequency  of the output of the exciter which has the WSPR signal imposed upon it, and let the push pull driver of the Class d amp divide by 2 again, WSPR won't work. This is documented and has caught others out who tried just running the exciter at 272kHz. PITA, and I don't fully understand why WSPR needs this, but there you go. Thanks Andy!

I can't see why it wouldn't work with 272KHz, there is nothing in the 272KHz square wave that shows it was ever made by doubling 136KHz. Do you have any pointers?

[bson]

I am having issues with glitches at the amp input, and i am testing with 4 feet or so of RG-58 co-ax between doubler output and amp input. When a signal ceases I sometimes see a lot of sudden noise and this signal stays high for a few hundred uS, which does the Class D push pull FET's a mischief.

The output is unbiased, so will float during transition through the "dead zone".  Vintage CMOS has sh*tty bandwidth and transition times, so it's going to spend some significant time transitioning through this dead zone.  While floating, your cable picks up noise since it's not actively driven.  Noise on a clock translates to jitter and duty cycle variance, if not frequency error or failure to maintain lock altogether.

[Benta]

Despite what the build notes say should I run a series resistor at the output of the doubler *AND* a parallel one, which i have already, at the amp input?

No.

This would be correct impedance matching, but you have to take the voltage division of the two 50-ohm resistors into consideration, so you'd only have half the voltage for the 74F74, which is not enough to trigger it correctly. I think the original designed forgot this, which explains the footnote.

On top of that, driving a 74F74 directly from a coax input is bad design.

My suggestions would be:
1: use a standard CMOS 4046 and power it from +8 V (78L08). This will give you around 6 Vpp at the bipolar output.
2: use a series resistor at the sending end and the parallel resistor at the receiving end. This will give you 3 Vpp for 74F74 with optimum impedance matching.
3: use transient protection at the input to the 74F74 combined with a buffer/Schmitt-trigger (on edit: badly phrased, should be: protection -> buffer -> 74F74). The bipolar output will not go sufficiently low to trigger the 74F74 correctly.

[Chris Wilson]

Sorry for the delayed reply. I have used all this info to good effect though and fixed the amplifier's propensity for eating PA FET's at an alarming rate. The level I was driving the doubler at was too high and at the end of transmission period the output to the PA was being held high with noisy bursts for about 900uS. This was killing PA FET's as one pair (two FET's in parallel per side in push pull) were being held on too long. I reduced the output of the pre-amp feeding the doubler at circa 0 to 2dBm from the exciter and this hold on glitch disappeared. i will most likely try and get my head fully around what you have said about biasing and levels, and maybe change this IC. As a beginner I am a bit nervous of fiddling now I have it working, but I now know how to look at the drive to the amp with power to the PA FET's off to check if things are behaving, so will probably give this a go. Sincere thanks to all for the help and advice!