Finalizing the design of my lab PSU

[erikj]

Hi everyone!

First time posting on this forum. 
There has been several good threads here lately about DIY lab power supplies. Reading them gave me some inspiration to try to come up with my own design.

So lets start with some goals and ideas I had for the design (in no particular order).

• Fairly high power: 0-40V adjustable voltage and 0-5A current limit.
• I will be using some kind of tracking switched mode pre-regulator to reduce the heat sink requirements.
• Analog controls with coarse and fine settings for voltage and current, but adding digital control at a later stage should be an easy task.
• I am planning on using a 48V 250W switched mode power supply instead of a mains transformer.
• I want the ability to use external voltage sense wires.
• If possible, very low or no output capacitor in order to have very fast current limiting.
• I want it to be rugged and well protected
• ...and as stable and accurate as possible of course...

Anyway, this is the design I have managed to come up with so far. It is based on an early version of void_error's Lab PSU design, but with quite a few changes.
I have simulated and also bread-boarded the main part of the schematic and it seems to be working OK.

This is the most complex design I have attempted as of yet so I am now looking for some feedback and suggestions.

Schematic


Some thoughts and comments for the schematic:

• The pre-regulator part is not included. I will start playing around with that part at a later stage.
• SD1, SD2 are intended to clamp the voltage on R20, R21 if the main wires are disconnected but the load is still connected by the voltage sense wires. Maybe there is a better way?
• I used a Vref of 4.096V is to be prepared for digital control later and also as a reference for the voltage and current meters
  (Meters will be using a MCP3551 AD-converter, PIC micro controller and a LED display)
• Compensation capacitor C20 for the current control loop was added after some breadboard experiments. More on this below.
• Zener diodes Z1, Z2 are there to avoid losing regulation if the (front panel-) LEDs should fail or be disconnected.
• Differential amp for current sense is probably not needed, I added that to make the layout of the ground paths simpler.

When breadboarding the circuit I've had some problems with oscillations in the current control loop.
I was using a few 24V light bulbs as dummy load, and in parallel I put a 1000uF low ESR capacitor.
Adding the capacitor when in current limit mode caused the circuit to start oscillating at around 80kHz.
To fix this I tried increasing C7 to 10nF and then to 100nF, but that did not seem to help at all for some reason.
I finally managed to fix the problem by adding a capacitor (C20) from base to collector on T2, something I remember seeing in some audio amplifiers.
I am not quite sure what is going on there... 

Now to the questions:

• Do you see any mistakes or weird design decisions in there?
• I am using 3 out of 4 op-amps from the TL054, can you think of a good use for the last one?
• Most designs I have seen seems to be using high-side current sensing, is that a better solution than my low-side version?
• Is there a better way to stabilize the current control loop than what is in the schematic?
• Do you know a good way to test for overshoot and/or ringing without access to a DSO?
• Can you suggest a really nasty load that I can connect to check how the regulation performs?

[Kevin.D]

Hi everyone!

I have simulated and also bread-boarded the main part of the schematic and it seems to be working OK.

• Is there a better way to stabilize the current control loop than what is in the schematic?
• Do you know a good way to test for overshoot and/or ringing without access to a DSO?
• Can you suggest a really nasty load that I can connect to check how the regulation performs?

Hi erikj  .
Nice job    .
You say you simulated it ?. you have an lt spice asc file to upload ? .It's  alot easier to offer  feedback comment and suggestions if the simulation is available .

In respect to the above :
1/  Yes there probably is a better way to stabilize the CC loop than C20 ,I think youl need at least a small cap on the output .but it's hard for anyone to say , you have to look at a bode plot of the loop ,and thats where your spice sim file helps .

2/ Not without a oscilloscope you need one to see the ringing . You then load the output and  (step the load) with a fast pulse ,then you can catch the recovery response on your O Scope .Wiht this you can  judge how stable your loop is by the number/amplitude  of overshoots in the recovery response.

3/nasty loads . for testing your CC loop .Test with a few sizes of inductors 100uH, 1mH,100mH,10H running at the largest current they can handle ,for a  large inductor hook up a primary of a mains transformer (leave secondary open) .
For nasty loads for a C.V loop try  multiple low esr caps across the output at low currents (so large Rload or open) .Try multiple ceramic caps in parallel ,and then a large low esr electolytic. But without a scope to view results this is all bit futile

Regards[/list]

[dannyf]

Just some random questions for you to think about:

1) the choice of opamps: particularly when they are operating towards the limits -> near short or fully open. Will the opamps behave as expected? If not, what to do?

2) what value does T6/T7 add?

3) what value does D2 add?

4) do you really need T2/T8?

5) C4 / C7 seem too large.

6) R23 should be grounded? What other functions can R23 perform?

7) C5/C8 next to the opamps? Make it easy to add pwm output from a mcu.

...

I posted a tried-and-true design that's much cleaner than this and can be easily converted to be driven by a mcu. Look it up if you want.

[Andreas]

• Fairly high power: 0-40V adjustable voltage and 0-5A current limit.

240 W over 1 transistor that is capable to handle 200W @ 25 deg C case temperature
-> you will need LN2 for cooling.
alternately  around 2 additional power stage transistors.

The current limiting may be too slow for quickly changeing loads:
The largest problems I had with a load that switched from nearly idle at maximum output voltage to maximum limiting current (nearly short).
I simply used a large FET with a PWM-generator to test my PSU this way.
Finally I used a additional current clamping transistor between emitter distribution resistors and base of the power stage to limit the peak current to safe values.

Edit: probably you will need 2 reverse diodes at the output of your 7805/7905. Otherwise the regulators may stuck during power on.

with best regards

Andreas

[blackdog]

Hi erikj


First, 1 powertransitor is not enough, for that kind of power 3 à 4 transitors, its als a plus that you can better distribute the heat.
Look @ the datasheet of the MJ11016, Hfe @ 5A is around 5000, thats 1mA you dont niet de BD139 drivers...
This wil only give you more phase lag (Thats why you schematic is generating 80Khz)
The OP277 is a nice opamp, but... so slowwwwwwww, its whitin de loop of your currend controle, redesign this!
The use op BIG compensation capacitors is a rookie mistake.

If you have e relatif clean 48V supply remove T4 and T5, use a resistor, start with 5mA of current here.
I can go on but than i rebuild your hole schematic *grin*
At the output you need about 50uF/Ampere capacitor.

You can take a look @ this design, its in Dutch, use google translate.


And this is the hole artikel, its BIG and a lot of info.
http://www.circuitsonline.net/forum/view/110029/1

Kind regarts,
Blackdog

[erikj]

Hi erikj  .
Nice job    .
You say you simulated it ?. you have an lt spice asc file to upload ? .It's  alot easier to offer  feedback comment and suggestions if the simulation is available .

In respect to the above :
1/  Yes there probably is a better way to stabilize the CC loop than C20 ,I think youl need at least a small cap on the output .but it's hard for anyone to say , you have to look at a bode plot of the loop ,and thats where your spice sim file helps .

2/ Not without a oscilloscope you need one to see the ringing . You then load the output and  (step the load) with a fast pulse ,then you can catch the recovery response on your O Scope .Wiht this you can  judge how stable your loop is by the number/amplitude  of overshoots in the recovery response.

3/nasty loads . for testing your CC loop .Test with a few sizes of inductors 100uH, 1mH,100mH,10H running at the largest current they can handle ,for a  large inductor hook up a primary of a mains transformer (leave secondary open) .
For nasty loads for a C.V loop try  multiple low esr caps across the output at low currents (so large Rload or open) .Try multiple ceramic caps in parallel ,and then a large low esr electolytic. But without a scope to view results this is all bit futile

1> I am using TI-tina for the simulations, and I don't have very much experience with spice. I also wasn't able to find spice models for all components and used generic ones, so I am not sure the simulations are very accurate. But I'll look into that some more this weekend and see if I can produce some spice files.

2> Actually I do have a scope! But it's an old analog one, so everything I can test will need to be periodic. Maybe I can use a mosfet to switch to load periodically as Andreas suggested. But as I don't have a signal generator I will need to build something to drive it... Or maybe I'll just get a cheap DSO

3> Thanks! I'll have a look in my junk-bin and see what kind of inductors and caps I can find, I think I have a large transformer somewhere.

[erikj]

Just some random questions for you to think about:

1) the choice of opamps: particularly when they are operating towards the limits -> near short or fully open. Will the opamps behave as expected? If not, what to do?

2) what value does T6/T7 add?

3) what value does D2 add?

4) do you really need T2/T8?

5) C4 / C7 seem too large.

6) R23 should be grounded? What other functions can R23 perform?

7) C5/C8 next to the opamps? Make it easy to add pwm output from a mcu.

1> I have been thinking that the negative voltage swing might not be enough to turn the transistors fully off when at full output voltage. If that is the case I'll just I add a diode in series with each led to push the emitter voltage a bit higher. I could also use -12V to supply to the op-amps, but then I'll risk pulling the base too low, and need to add some kind of protection for that. Or am I missing something else here?

2> The idea for T6+T7 was to get a small current needed for the pre-regulator. I will probably be using a circuit similar to the one in EEVblog #329.

3> I added that to protect T3 from reverse base emitter breakdown, but that was before I added SD3 so it is probably not needed now.

4> I might not need them, the reason they are there is to handle the rather large output voltage swing. If I can find a good op-amp that can handle an output swing of 40V or more I could remove them.

5> OK, I'll try something smaller on my breadboard

6> I considered connecting it to +12V instead but wasn't sure how the DC-DC converter would handle that. Not sure what else I could use it for?

7> I guess that could work, but wouldn't that have some unwanted effects for the compensation?

I posted a tried-and-true design that's much cleaner than this and can be easily converted to be driven by a mcu. Look it up if you want.

Thanks, I'll take a look.

[erikj]

• Fairly high power: 0-40V adjustable voltage and 0-5A current limit.

240 W over 1 transistor that is capable to handle 200W @ 25 deg C case temperature
-> you will need LN2 for cooling.
alternately  around 2 additional power stage transistors.

If I run the supply without the pre-regulator, then yes, it is definitely too much for the single transistor. But liquid nitrogen cooling would be an interesting experiment though

My thoughts were that the pre-regulator will be keeping the voltage at 2.5-5 volts (I will see what works best) above the output voltage. If the voltage gets too high the high side switch of the buck converter should turn off, and all the transistor would need to handle is the remaining energy in the output inductor and capacitor + the energy in the extra filter L1+C1. That should last maybe 1 millisecond if my calculations are correct.
The safe operating area for pulses is not specified in the datasheet though, so maybe I am pushing my luck here.
I'll definitely consider adding another one in parallel.

The current limiting may be too slow for quickly changeing loads:
The largest problems I had with a load that switched from nearly idle at maximum output voltage to maximum limiting current (nearly short).
I simply used a large FET with a PWM-generator to test my PSU this way.
Finally I used a additional current clamping transistor between emitter distribution resistors and base of the power stage to limit the peak current to safe values.

Thanks, that is something I had not considered.
Maybe L1 will keep the current from rising too quickly, I need to do some more calculations to see if this will be needed.

Edit: probably you will need 2 reverse diodes at the output of your 7805/7905. Otherwise the regulators may stuck during power on.

with best regards

Andreas

Do you mean diodes from output to ground, or from output to input?

[erikj]

Hi erikj

First, 1 powertransitor is not enough, for that kind of power 3 à 4 transitors, its als a plus that you can better distribute the heat.
Look @ the datasheet of the MJ11016, Hfe @ 5A is around 5000, thats 1mA you dont niet de BD139 drivers...
This wil only give you more phase lag (Thats why you schematic is generating 80Khz)
The OP277 is a nice opamp, but... so slowwwwwwww, its whitin de loop of your currend controle, redesign this!
The use op BIG compensation capacitors is a rookie mistake.

I chose the opa277 for the low noise and offset voltage. What would you suggest instead?
I guess I could adjust the offset with a trimpot so that shouldn't be a problem.

If you have e relatif clean 48V supply remove T4 and T5, use a resistor, start with 5mA of current here.
I can go on but than i rebuild your hole schematic *grin*
At the output you need about 50uF/Ampere capacitor.

You can take a look @ this design, its in Dutch, use google translate.


And this is the hole artikel, its BIG and a lot of info.
https://www.eevblog.com/forum/projects/finalizing-the-design-of-my-lab-psu/msg502757/#msg502757

Kind regarts,
Blackdog

That link you gave didn't work. 
Looking forward to reading that article!

[blackdog]

Sorry Erik,

I got up twice to the wrong link posted ...
I am old-)
Refres the page, the original link works now...


Take your time, its long, at the end you wil find information how to keep the dissipation low in you power transistor.

About the IC for current sensing, high precision is good for the opamp, but with a slow IC there you make to much phase lag, and your current control loop wil generate!
Your current sense opamp need to be as least as fast as the opamp voor the current loop, this because you current sense IC is inside this loop.
The opamp that you use fore the current loop is not designed to have a second opamp in its feedback loop.

Sorry for bad english...

Kind regarts
Blackdog

[void_error]

Wow, so many bench PSU designs on this forum.

You might want to take a look at mine, it's tested and stable on breadboard. https://www.eevblog.com/forum/projects/bench-power-supply-design/90/

Note that not all components have values assigned yet.

[Andreas]

Edit: probably you will need 2 reverse diodes at the output of your 7805/7905. Otherwise the regulators may stuck during power on.

with best regards

Andreas

Do you mean diodes from output to ground, or from output to input?

Hello,

look at D13,D14 in blackarts design.
he also has the peak current limiting transistor (Q6) that I mentioned.

With best regards

Andreas

[blackdog]

Hi Andreas,

Thank you for my nice second name => blackarts
Ore, you find my design Black-Art *grin*


Kind regarts,
Blackdog

[erikj]

Hello,

look at D13,D14 in blackarts design.
he also has the peak current limiting transistor (Q6) that I mentioned.

With best regards

Andreas

Thanks, I'll add the diodes

Sorry Erik,

I got up twice to the wrong link posted ...
I am old-)
Refres the page, the original link works now...


Take your time, its long, at the end you wil find information how to keep the dissipation low in you power transistor.

About the IC for current sensing, high precision is good for the opamp, but with a slow IC there you make to much phase lag, and your current control loop wil generate!
Your current sense opamp need to be as least as fast as the opamp voor the current loop, this because you current sense IC is inside this loop.
The opamp that you use fore the current loop is not designed to have a second opamp in its feedback loop.

Sorry for bad english...

Kind regarts
Blackdog

Thank you! I have some reading to do

Guess I'll have to order some faster op-amps.

[David Hess]

Most designs I have seen seems to be using high-side current sensing, is that a better solution than my low-side version?

Use whatever is more convenient.  Sometimes one is needed over the other because of common ground considerations.

I prefer using single ended level shifting to instrumentation amplifiers because it is faster and does not require resistor matching for high common mode rejection.  I see you implemented remote sense however which is one place I might use an instrumentation amplifier although I have done without them there as well.

Is there a better way to stabilize the current control loop than what is in the schematic?

I had a bunch of comments here about T2 and T8 adding uncontrolled gain within the feedback loop but I see now that you configured them with shunt feedback which neatly solves the problem.  I might try adding a little bit of emitter degeneration to tailor their frequency response and provide stability.  Instead of the shunt feedback amplifiers, I would have tried bootstrapping the operational amplifiers to increase their output voltage range so T2 and T8 could be emitter followers which would simplify frequency compensation.

You have not implemented any lead or pole-zero compensation in the feedback loops to make them more stable.

At least a small output capacitor should be included to help with frequency compensation and stability.

The integration capacitors around OP1.2 and OP1.3 are going to increase the delay when switching between voltage and current modes because of integrator wind-up.  Proper frequency compensation will minimize their value but maybe the integrators should be clamped.

Do you know a good way to test for overshoot and/or ringing without access to a DSO?

I am not sure why a DSO would be needed for this.  A low frequency square wave, 1 kHz is about right, can be used to apply load steps to the output, voltage steps to the voltage loop, and current steps to the current loop while monitoring the transient response.

Can you suggest a really nasty load that I can connect to check how the regulation performs?

Bob Widlar apparently like to run a file across the output terminals generating a shower of spark to see if the power supply would fail.

40 volts at 5 amps is a pretty big supply.  I would consider adding thermal protection to the pass element but maybe that is unnecessary because you are using a switching preregulator.  I would include an SCR crowbar on the output to protect any load from failure of the pass element or voltage control loop.

[erikj]

I had a bunch of comments here about T2 and T8 adding uncontrolled gain within the feedback loop but I see now that you configured them with shunt feedback which neatly solves the problem.  I might try adding a little bit of emitter degeneration to tailor their frequency response and provide stability.  Instead of the shunt feedback amplifiers, I would have tried bootstrapping the operational amplifiers to increase their output voltage range so T2 and T8 could be emitter followers which would simplify frequency compensation.

I might try bootstrapping if I can't get this thing stable, adds a lot of extra parts though.

You have not implemented any lead or pole-zero compensation in the feedback loops to make them more stable.
At least a small output capacitor should be included to help with frequency compensation and stability.

OK,
I will definitely need to learn more about loop compensation
I'll start by trying to measure the step responses and then go on from there.

The integration capacitors around OP1.2 and OP1.3 are going to increase the delay when switching between voltage and current modes because of integrator wind-up.  Proper frequency compensation will minimize their value but maybe the integrators should be clamped.

Good point, do you have any suggestion on how to do that?

I am not sure why a DSO would be needed for this.  A low frequency square wave, 1 kHz is about right, can be used to apply load steps to the output, voltage steps to the voltage loop, and current steps to the current loop while monitoring the transient response.

Great, I have now set up the voltage control loop so that it is controlled by the test square wave signal from my scope.
I will try to get some screen shots and post them here later...

Bob Widlar apparently like to run a file across the output terminals generating a shower of spark to see if the power supply would fail.

40 volts at 5 amps is a pretty big supply.  I would consider adding thermal protection to the pass element but maybe that is unnecessary because you are using a switching preregulator.  I would include an SCR crowbar on the output to protect any load from failure of the pass element or voltage control loop.

Good, I might add something like that.

I am starting to have some seconds thoughts about the single transistor, it is probably better to make something that will work safely even without the pre-regulator but that is limited by an over temp. protection circuit.

[David Hess]

I might try bootstrapping if I can't get this thing stable, adds a lot of extra parts though.

It does but they are all good parts.

I would also consider using operational amplifiers which have a slightly higher supply voltage range.

The integration capacitors around OP1.2 and OP1.3 are going to increase the delay when switching between voltage and current modes because of integrator wind-up.  Proper frequency compensation will minimize their value but maybe the integrators should be clamped.

Good point, do you have any suggestion on how to do that?

Just improving the loop compensation may be all that is needed because it will lower the value of the feedback capacitors.

If that is not enough, then limiting the amplifier output voltage when the loop is broken will help.  I usually hear this called "clamping" or maybe "anti-windup".  Some operational amplifiers bring out special connections so it can be applied to internal nodes.

Usually this just involves tying the output back to the inverting input with diodes or a zener clamp or something more sophisticated.

I am not sure why a DSO would be needed for this.  A low frequency square wave, 1 kHz is about right, can be used to apply load steps to the output, voltage steps to the voltage loop, and current steps to the current loop while monitoring the transient response.

Great, I have now set up the voltage control loop so that it is controlled by the test square wave signal from my scope.

This is one application where I find little or even negative advantage to using a DSO over an analog oscilloscope.  It is possible to calculate the bode plot from the impulse or step response but very few DSOs can do it.

I am starting to have some seconds thoughts about the single transistor, it is probably better to make something that will work safely even without the pre-regulator but that is limited by an over temp. protection circuit.

3 amps would be pushing it if the full supply voltage was across the pass element because of secondary breakdown limitations.

One trick I like to use is bolting an integrated regulator to the output transistor heat sink and using it as part of the pass element or control circuit.  It can be used to provide thermal protection and sometimes safe operating area protection which varies with temperature.

[void_error]

I am starting to have some seconds thoughts about the single transistor, it is probably better to make something that will work safely even without the pre-regulator but that is limited by an over temp. protection circuit.

3 amps would be pushing it if the full supply voltage was across the pass element because of secondary breakdown limitations.

One trick I like to use is bolting an integrated regulator to the output transistor heat sink and using it as part of the pass element or control circuit.  It can be used to provide thermal protection and sometimes safe operating area protection which varies with temperature.

I wouldn't go above 20-30W of dissipated power for a single TO-220 package transistor when mounted on a proper heatsink. For larger packages a ballpark figure would be no more than 50W. Multiple paralleled pass elements with low value emitter resistors to equalize V_BE is the best choice here. This will also lower the total junction-case R_th which is going to be the R_th of each device divided by the number of devices.

[David Hess]

I wouldn't go above 20-30W of dissipated power for a single TO-220 package transistor when mounted on a proper heatsink. For larger packages a ballpark figure would be no more than 50W. Multiple paralleled pass elements with low value emitter resistors to equalize V_BE is the best choice here. This will also lower the total junction-case R_th which is going to be the R_th of each device divided by the number of devices.

I agree.  Power ratings are normally given assuming a Tc (temperature case) of 25C so they are just a starting point before considering thermal resistance and operating temperature.  Spreading the heat out over multiple packages has the effect of paralleling and lowering the thermal interface resistance.

I have occasionally gone higher with very careful thermal design and construction including proper mounting torque and active cooling but it is not something I would want to rely on in a production design because like heat treating, it is easy to screw up with no visible signs until something breaks or explodes.

Or you forget to cool the emitter ballast resistors and they turn red hot. 

[erikj]

I did some scope measurements for the voltage regulation part of the PSU to see what happens with different integrator cap values.
As the source signal I used the square wave from my Agilent multimeter at 4.8kHz, 50% duty.
The signal is connected to Vset in the schematic but without the 470nF smoothing cap (C5), I have also changed the voltage dividers to get about 10V output signal.

Vertical setting is 2V/div for all images.
The lower trace is the input signal and the upper is the regulated voltage. I am using a 12ohms power resistor as the load and running
with no output capacitor.


This is a 150pF capacitor. Horizontal 50µs/div. Not bad!


This is also 150pF cap.  Horizontal 2µs/div, there is a very slight ringing visible.


1nF cap. Horizontal 50µs/div. The input signal is clearly changed by the feedback capacitor, this might affect the results a bit.


80 pF (47+33) cap. Horizontal 2µs/div. Overshoot and a ringing at about 500kHz, this value seems a bit too low.

So I guess 150pF is the value I should be using

[Kevin.D]

The lower trace is the input signal and the upper is the regulated voltage. I am using a 12ohms power resistor as the load and running
with no output capacitor.

Hi erik .
Your supposed to test it under it's worst load conditions .
Try that with 1uF's worth of CERAMIC caps  and a very high value  load resistor (or open ) .

Regards

[David Hess]

You have a couple of things going for you aiding stability.

The kelvin sensing instrumentation amplifier divides the loop gain by 10 which largely offsets the transistor shunt amplifier which multiplies the loop gain by about 20 so that you need only a minimum amount of integration capacitance is not surprising.  I think that explains why such a low value of feedback capacitance makes it stable.

Similar math can be done for the current loop which needs to be checked separately anyway.  I usually start off adjusting the frequency compensation empirically (It is difficult to know what the pass element is doing.) and then go back for an analytical solution.

My usual strategy on the integration capacitors is to increase the resistance in series with the capacitor which will reduce the amount of capacitance needed.

I think phase lead can be added in your design with small capacitors (or networks) added in parallel with R3 and R4.  I usually do this earlier in the circuit path but you have those instrumentation amplifiers in the way.  Eventually C20 should not be needed.

When I have laid out boards in the past, I included parallel C and series RC phase lead and feedback networks which were then populated based on further testing.

As Kevin.D says, testing for worse case load and operating point should be done.  Usually at least a small low Q (relatively high ESR like an aluminum electrolytic or solid tantalum) capacitor is placed across the outputs to swamp other effects.

If this is a production design, then the frequency compensation should be adjusted for the worst case components which implies some sample testing.

What happens when power is first applied? Does the output glitch?

[erikj]

Your supposed to test it under it's worst load conditions .
Try that with 1uF's worth of CERAMIC caps  and a very high value  load resistor (or open ) .

I wanted to start with something easy

So I tried this... and the supply didn't like that at all. It went completely unstable and started oscillating wildly.
Couldn't even get a good sync on the scope.

Next I did some experiment with adding a cap or a cap + resistor across R14 to try to get a bit of lead compensation. This helped a bit, but did not solve the problem. I also simulated this setup and it turns out it is not stable in simulation either.

I then tried swapping the BD139 for something faster, a BC550C. And that made a huge improvement! I guess the BD139 wasn't fast enough. I still had a large ringing, but it was much cleaner and eventually settled to the set voltage.

You have a couple of things going for you aiding stability.

The kelvin sensing instrumentation amplifier divides the loop gain by 10 which largely offsets the transistor shunt amplifier which multiplies the loop gain by about 20 so that you need only a minimum amount of integration capacitance is not surprising.  I think that explains why such a low value of feedback capacitance makes it stable.

Similar math can be done for the current loop which needs to be checked separately anyway.  I usually start off adjusting the frequency compensation empirically (It is difficult to know what the pass element is doing.) and then go back for an analytical solution.

My usual strategy on the integration capacitors is to increase the resistance in series with the capacitor which will reduce the amount of capacitance needed.

Lots of good info, thanks.

I think phase lead can be added in your design with small capacitors (or networks) added in parallel with R3 and R4.  I usually do this earlier in the circuit path but you have those instrumentation amplifiers in the way.  Eventually C20 should not be needed.

I tried adding a 220p cap across R3 after changing the transistor, and that worked beautifully,  thank you!
Much better that putting it on R14.
See below for the result.

If this is a production design, then the frequency compensation should be adjusted for the worst case components which implies some sample testing.

What happens when power is first applied? Does the output glitch?

At the moment this is a one-off project for myself only.

I tried cycling the power several times, and did notice a small glitch once, but only a volt or so on the output. I will have to test this again with the DC-DC converter in place. Currently I am running it from another lab supply.


So here is the result with a 1µF ceramic cap as the only load. This is after changing transistors and adding a cap across R3.

2V/div vertical and 50µs/div horizontal, 4.8kHz square wave input (same as before). Still not perfect, but a huge improvement.
There is also a small ringing there that is visible when I zoom in.

[void_error]

I think the reason for the instability is the fact that the stage between the opamps and the series pass transistor has very little local negative feedback.
In one of my early versions I tried something similar but I wasn't happy with it so I ended up with adding a discrete gain stage with a set gain slightly above the minimmum gain required for the maximum base drive voltage I needed (V_OUT+V_F+2xV_BE). It basically amplifies the opamp's output by a factor of 10 (although 6 would probably be enough) while the opamp still controls the overall gain.

Since you're doing the current sensing on the low side you could replace T6/T7 current sink with a 1k resistor to ground.

Another thing you can do to make your circuit more stable is to add baker clamps to T2 & T8 to prevent them from saturating if that's the cause of instability/ringing. http://en.wikipedia.org/wiki/Baker_clamp

[David Hess]

I think the reason for the instability is the fact that the stage between the opamps and the series pass transistor has very little local negative feedback.
In one of my early versions I tried something similar but I wasn't happy with it so I ended up with adding a discrete gain stage with a set gain slightly above the minimmum gain required for the maximum base drive voltage I needed (V_OUT+V_F+2xV_BE). It basically amplifies the opamp's output by a factor of 10 (although 6 would probably be enough) while the opamp still controls the overall gain.

The transistors are configured with shunt feedback stabilizing their voltage gain.  I would be more worried that their operating current is too low to drive the output at full speed.

Another thing you can do to make your circuit more stable is to add baker clamps to T2 & T8 to prevent them from saturating if that's the cause of instability/ringing. http://en.wikipedia.org/wiki/Baker_clamp

The transistors are so fast compared to the speed of the overall feedback loop that the storage delay from saturation should be insignificant.