Forward body diode voltage of a mosfet

[bentomo]

So I'm trying to debug this circuit using an FDV301 mosfet. http://www.mouser.com/ds/2/149/FDV301N-52768.pdf It's using the FET to isolate an i2c data signal. However, I see a requirement for a maximum voltage on Vsd. I think it means that I can't have a forward voltage of greater than 1.2v when Vgs is 0. Which seems strange to me. What's the point of the FET if it can't even handle a 3.3v isolation, unless my hunch is correct and you can't ignore the body diode. The max I'm worried about is at the bottom of page 3. See attached image


Someone was trying to explain to me that the body diode of a fet doesn't matter either. But that doesn't sound right to me either. I thought for true isolation you would need a FET with the body diode facing in the opposite direction. Doesn't the body diode always conduct if you have a voltage drop across it?

[Someone]

The limits for the part are listed as "Absolute Maximum Ratings" further down specifications such as the one you pulled out are for design, in this case a short pulse of 290mA has a typical forward voltage of 0.8V and no worse than 1.2V (when operated in the conditions specified). They provide an I-V curve of the forward biased body diode in the data sheet if you need more detail.

[ocset]

you can have an off state voltage of up to 25v  across source-drain..best to derate that a little.

Yes the body diode is significant...its just like having a diode externally acrioss the fet.

If  the body diode is upsetting your modus operandi, then consider uing two back to back fets...of course, you need a driver to be able to raise gate above source to be able to switch them on.

[slugrustle]

Your MOSFET is N-channel, and its drain can be up to 25V positive relative to source. The body diode will not conduct besides the "Zero Gate Voltage Drain Current" of 1-10uA. However, if the source is more positive than the drain (Vsd > 0), the current through the diode follows figure 6 on page 4 of the datasheet.

treez' explanation that it's like having a diode across the MOSFET is a good one. The cathode is connected to the drain and the anode to the source. This is shown in the middle circuit symbol on the first page of the datasheet.


It would help to have a schematic and description of the bug you're troubleshooting to determine the relevance of the body diode specs.

Are you interfacing devices at different voltage levels, like in the following PDF? https://www.nxp.com/docs/en/application-note/AN10441.pdf  Page 4 has a schematic for such a scenario and explains in detail how the circuit operates.

[bentomo]

Thank you guys for confirming that. I knew you couldn't just ignore the body diode.

No there is no level shifting going on. It's a 3.3v circuit. I've made a model of what the current state of it is.

Now based on the maximum forward current my hunch is we fried Q1 and Q3 when the second i2c master used to be connected

Where the red text  second SCL/SDA master is there was another set of fets (same part facing the same direction toward the eeprom) and we tried to drive the eeprom from the controller on the board with it's built in i2c engine. This is the same controller driving the Enable signal. The processor is driving a 3.3v output just fine. The idea is that the processor will enable the vpd which will disable the vpd bus from an external host. They tried to do isolation with a few fets but when I looked at the circuit I saw this, which I know isn't true isolation because of that body diode.

I believe this was put on the board because they thought the processor didn't support multimaster i2c. Which it said in the first line of the data sheet description of the i2c controller. 

We'll probably end up ripping this out but here's the weird behavior I'm seeing.

At this point the second master is disconnected. I've also disconnected the SCL and SDA signals on the left side. So the only things on the circuit are the processor enable gpio output, the pull up resistors, and the eeprom.

When the Enable signal is sitting at 0 everything seems fine. SCL and SCL EEPROM are sitting at 3.3v. But when Enable is driven to 3.3v, SCL drops to approximately 0.7v and SCL EEPROM drops to 0.1v. I see the exact same behavior on SDA

I don't see where all the voltage is going unless Q1/Q3 was somehow fried by pushing 3.3v across the body diode and the voltages are escaping through the gates to GND.


EDIT:
So I forgot about the maximum prospective short-circuit current. https://en.wikipedia.org/wiki/Prospective_short-circuit_current The default supply drive strength from the processor is only 8mA and the pull ups would limit the current too. So I don't think anything could get into the circuit with enough current to short it out. So now I'm really stumped

[bentomo]

Found the culprit.

I learned a valuable lesson today, never ignore the internal diodes on a FET.

I was looking at the body diode but didn't think to look at the clamp protection diode.

So when the gate is pulled to GND and the anode of the clamping diode is still 3.3v and we get a negative Vgs, the FET is also ON which causes both sides to be pulled low.