Author Topic: FPGA-based shortwave SDR receiver  (Read 265 times)

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Offline Sparker

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FPGA-based shortwave SDR receiver
« on: December 08, 2017, 10:26:50 AM »
Hello!  :)

I was inspired by awesome projects like WebSDR, PSDR and other SDRs in the Internet and decided to make one myself.

Here's a quick demo video of the project:


It's a small Lithium-powered shortwave receiver that can demodulate AM and SSB in the band up to 10MHz. It also plots waterfall and spectrum in 200kHz band on a large LCD. There are four pushbuttons and two encoders for user input.

The core of the digital side of the device is an Altera Cyclone IV EP4CE6 (6k LEs) FPGA with these major modules attached to it:
- AD9200 10bit 20MSPS ADC;
- SE Vivaz 640x360 LCD;
- ISSI 256kx16 asynchronous SRAM;
- Some serial devices like shift registers, a digital potentiometer for audio volume control and an 8-bit ADC to measure battery voltage.

The FPGA does digital down conversion to 100kHz sample rate, then the I/Q stream is being passed through another complex mixer, filtered and decimated to a lower sample rate(20kHz) stream. The slow sample rate stream is demodulated with a NIOS II/f processor and passed to a PWM module that serves as a DAC. The 100kHz sample rate stream is stored in the SRAM to be later processed by a custom module that calculates 16384-point FFT. The FFT processing is double-buffered, so while the FFT module does its job the processor handles previously calculated FFTs(averaging, converting to dBs, LCD refreshing) thus yielding higher refresh rates.
Another task that I've offloaded to the FPGA is to monitor the pushbuttons and encoders. For each button push or encoder step rotation it writes an entry to a specified circular buffer, so that the processor can do more important things and check that buffer later.

The device consists of two boards. The top one has all the digital ICs, and the bottom one has all the power supply circuitry, audio amp. and the RF amplifier.
The amount of power supply rails here is a total nightmare! The FPGA needs three(3.3V, 2.5V and 1.2V), then ADC has a separate 3.3V supply, the LCD core voltage 2.8V, oh and also there's a step-up converter for the backlight. Probably i could find a better solution for all these LDOs.

There's also an RF amplifier with 10MHz anti-alias filter at the bottom board. The gain can be adjusted between ~10dB and ~40dB with ~10dB steps, controlled from the processor. I'm quite bad at transistor amp design so I didn't manage to make a good one with high gain and low distortion at 3.3V power supply, so I've put a 6V step-up converter to increase the collector voltage and ease the design.

References:
A lot of info on SE Vivaz LCD interfacing at Andy Brown's website.
I used Codehead's Bitmap Font Generator to generate the fonts.
 
The following users thanked this post: daqq, albert22

Offline Kalvin

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Re: FPGA-based shortwave SDR receiver
« Reply #1 on: December 09, 2017, 03:40:05 AM »
Great project!  :-+
 

Offline asmi

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Re: FPGA-based shortwave SDR receiver
« Reply #2 on: December 09, 2017, 06:57:41 AM »
Amazing project! Home-etched FPGA board is :-+
The amount of power supply rails here is a total nightmare! The FPGA needs three(3.3V, 2.5V and 1.2V), then ADC has a separate 3.3V supply, the LCD core voltage 2.8V, oh and also there's a step-up converter for the backlight. Probably i could find a better solution for all these LDOs.
I would suggest replacing all these LDOs (except the one for ADC as they usually don't have very good PSRR) with switchers to increase power efficiency and improve battery life. I would use something like TPS65581 triple DC-DC buck converter - it has very good efficiency and is very easy to use (it requires very few external components to run). I used this PMIC to power Artix-7 FPGA with no problems at all.
 


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