Author Topic: FPGA-based shortwave SDR receiver  (Read 1460 times)

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Offline Sparker

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FPGA-based shortwave SDR receiver
« on: December 08, 2017, 10:26:50 am »
Hello!  :)

I was inspired by awesome projects like WebSDR, PSDR and other SDRs in the Internet and decided to make one myself.

Here's a quick demo video of the project:


It's a small Lithium-powered shortwave receiver that can demodulate AM and SSB in the band up to 10MHz. It also plots waterfall and spectrum in 200kHz band on a large LCD. There are four pushbuttons and two encoders for user input.

The core of the digital side of the device is an Altera Cyclone IV EP4CE6 (6k LEs) FPGA with these major modules attached to it:
- AD9200 10bit 20MSPS ADC;
- SE Vivaz 640x360 LCD;
- ISSI 256kx16 asynchronous SRAM;
- Some serial devices like shift registers, a digital potentiometer for audio volume control and an 8-bit ADC to measure battery voltage.

The FPGA does digital down conversion to 100kHz sample rate, then the I/Q stream is being passed through another complex mixer, filtered and decimated to a lower sample rate(20kHz) stream. The slow sample rate stream is demodulated with a NIOS II/f processor and passed to a PWM module that serves as a DAC. The 100kHz sample rate stream is stored in the SRAM to be later processed by a custom module that calculates 16384-point FFT. The FFT processing is double-buffered, so while the FFT module does its job the processor handles previously calculated FFTs(averaging, converting to dBs, LCD refreshing) thus yielding higher refresh rates.
Another task that I've offloaded to the FPGA is to monitor the pushbuttons and encoders. For each button push or encoder step rotation it writes an entry to a specified circular buffer, so that the processor can do more important things and check that buffer later.

The device consists of two boards. The top one has all the digital ICs, and the bottom one has all the power supply circuitry, audio amp. and the RF amplifier.
The amount of power supply rails here is a total nightmare! The FPGA needs three(3.3V, 2.5V and 1.2V), then ADC has a separate 3.3V supply, the LCD core voltage 2.8V, oh and also there's a step-up converter for the backlight. Probably i could find a better solution for all these LDOs.

There's also an RF amplifier with 10MHz anti-alias filter at the bottom board. The gain can be adjusted between ~10dB and ~40dB with ~10dB steps, controlled from the processor. I'm quite bad at transistor amp design so I didn't manage to make a good one with high gain and low distortion at 3.3V power supply, so I've put a 6V step-up converter to increase the collector voltage and ease the design.

References:
A lot of info on SE Vivaz LCD interfacing at Andy Brown's website.
I used Codehead's Bitmap Font Generator to generate the fonts.

Project files: dropbox
« Last Edit: April 24, 2018, 08:09:36 pm by Sparker »
 
The following users thanked this post: daqq, albert22, 4cx10000, daslolo

Offline Kalvin

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Re: FPGA-based shortwave SDR receiver
« Reply #1 on: December 09, 2017, 03:40:05 am »
Great project!  :-+
 

Offline asmi

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Re: FPGA-based shortwave SDR receiver
« Reply #2 on: December 09, 2017, 06:57:41 am »
Amazing project! Home-etched FPGA board is :-+
The amount of power supply rails here is a total nightmare! The FPGA needs three(3.3V, 2.5V and 1.2V), then ADC has a separate 3.3V supply, the LCD core voltage 2.8V, oh and also there's a step-up converter for the backlight. Probably i could find a better solution for all these LDOs.
I would suggest replacing all these LDOs (except the one for ADC as they usually don't have very good PSRR) with switchers to increase power efficiency and improve battery life. I would use something like TPS65581 triple DC-DC buck converter - it has very good efficiency and is very easy to use (it requires very few external components to run). I used this PMIC to power Artix-7 FPGA with no problems at all.
 

Offline Sparker

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Re: FPGA-based shortwave SDR receiver
« Reply #3 on: December 15, 2017, 09:59:50 am »
Thanks for the response, guys!

I would use something like TPS65581 triple DC-DC buck converter - it has very good efficiency and is very easy to use (it requires very few external components to run). I used this PMIC to power Artix-7 FPGA with no problems at all.
That kind of ICs are pretty hard to get at the local store(but for some reason the FPGA is available at reasonable price). Plus its harmonics could find a way into the  RF amp. In fact the LCD backlight converter can already be seen in the spectrum. About 50% of power is consumed by the LCD backlight, and I estimated that switching to high efficiency regulators from linear ones would gain about 25% of battery life. It all depends on the LCD brightness used of course.
I was thinking more about multi-channel LDOs, but ended up with a bunch of LP2951/LP2931 LDOs. Maybe I will redesign the bottom board later, replace the LDOs and enhance the RF part.

The whole device was designed to fit into an aluminum Gainta G0124 case. I used FreeCAD a lot to check how it fits in. It could go even better if Gainta provided all the dimensions of the case(or even a 3D model). Why they don't is beyond my understanding  :-\.
As you see, IRL the boards fit perfectly!

Next I plan to enhance the software part. One cool feature would be to store some settings in the flash memory before the device is switched off. Also I'd like to try to decode RTTY, which seems to be easy done with a couple of bandpass filters.
Also the device can totally lock up once in half an hour, or not lock up at all. No idea how to debug this.  :-// Probably one of my QSys components creates a bad condition and locks the whole bus.
« Last Edit: December 15, 2017, 10:08:06 am by Sparker »
 

Offline daslolo

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Re: FPGA-based shortwave SDR receiver
« Reply #4 on: April 23, 2018, 06:31:16 pm »
Beautiful work, the aesthetic of waterfall spectrum is always  :-+
You would make many of us drool if you turned this into a pocket oscillo+spectroscope
 

Offline Sparker

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Re: FPGA-based shortwave SDR receiver
« Reply #5 on: April 24, 2018, 04:06:15 am »
Thanks!
The hardest part with the waterfall display was to choose the most beautyful dB->color conversion table.  ;D
Actually I thought of turning it into an oscilloscope. But the analog part will have to be redone, because now it doesn't pass anything below a few hundred kHz. Also the internal digital part wasn't designed to capture high speed 20 MSPS data, instead it downconverts it to 100 kSPS and then stores it into the SRAM. Maybe there are some internal SRAM blocks left to serve as a buffer.
 

Offline MasterT

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Re: FPGA-based shortwave SDR receiver
« Reply #6 on: April 24, 2018, 04:47:42 am »
Is it student's work?  Why FPGA, if sample rate gonna be shrink-ed down to 20 kHz?  Arduino with Si4825 can do better as a receiver.
Or like any SDR, down-converting RF with multiplexer /PLL  (RTL2832 style) to audio range.
The only reason for fast (and high price) ADC route I see, is to have 10 MHz real-time band-width coverage, but it looks like processing is the bottle neck. I made my arduino DUE running FFT with 300 ksps, arduino UNO may process 20 kHz FFT with one left hand.  No FPGA needed.
 

Offline Sparker

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Re: FPGA-based shortwave SDR receiver
« Reply #7 on: April 24, 2018, 07:39:43 am »
I did it to practice my (limited) FPGA and DSP skills. :)

"Why ADC+FPGA" is the question of analog vs digital downconversion, i think, in this frequency band of interest. I don't have experience designing analog freq. mixing chains yet, but what I know tells me that it will be hard as hell because:
1. The need of image-rejecting filters.
2. Need to properly design the mixer (double balanced is best) or find the proper IC for this.
3. Still need to synthesize the LO signal in wide frequency range.
Here I just put a cheap ADC, then I can do a nice downconversion with perfectly matched digital multipliers and sin/cos generators.

The spectrum bandwidth is actually only 200 kHz. I believe you can achieve nice FFT performance on a good ARM MCU, indeed. I'm also learning STM32 MCUs now and I'm impressed by their abilities. They easily overthrow the soft processor core I have in my FPGA.
But the FPGA gived me the ability to do the FFT in parallel with the processor core. Then the processor updates the LCD. It also does baseband demodulation. The FFT part runs with two buffers, so it doesn't have to wait till the processor grabs the results and draws them(the CPU also has to do some FFT averaging).

The FFT size also matters. Of course an Arduino Uno can do some FFT, but with its limited memory of 2kb the size will be also be limited, while I have FFT size of 16384 due to external memory.
 

Offline Navarro

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Re: FPGA-based shortwave SDR receiver
« Reply #8 on: April 24, 2018, 11:42:44 am »
That's a nice one!

Would you mind sharing the schematic and software?
PY1CX
34401A - DSOX2002A - 66332A
 

Offline Sparker

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Re: FPGA-based shortwave SDR receiver
« Reply #9 on: April 24, 2018, 08:14:50 pm »
Thanks, Navarro!
Yeah no problem: .zip archive at dropbox.
 
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Offline Mick2018

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Re: FPGA-based shortwave SDR receiver
« Reply #10 on: April 29, 2018, 09:32:14 pm »
Hello,

Geart Project :) :-+

Maybe You can sharing Gerber Files for boards and Source Code and Parts list ?

Best Regards
« Last Edit: April 29, 2018, 09:35:51 pm by Mick2018 »
 

Offline Scrts

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Re: FPGA-based shortwave SDR receiver
« Reply #11 on: April 30, 2018, 01:32:51 am »
Thumbs up!  :-+ Seems nice!
 


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