GAN power devices, EPC Vs Gan Systems Vs TI, what to choose?

[dmills]

Hi all,

Decisions, decisions.... For a 48V, 2kW class polyphase buck converter (Really a two quadrant supply) for envelope tracking, what would you choose?

EPC : Has lowest Rds, but 0.45mm BGA, yuck, and bare passivated die, so delicate and likely very picky about ESD protection, I can see soldering being a pain.
GAN Systems : Nicer package to work with, but three times the Rds value, however probably much easier to heatsink and no messing with bare die BGA packages, however only do single devices, no packaged half bridge components.
TI : Integrated driver!  Only 10A rated so I would need a few more phases, but the whole gate drive pain point goes away, somewhat expensive however and I worry about cooling them.   

Question is, does TIs 10A rating mean it in reality, or is it like most mosfet current ratings (measured in boiling freon)?

The reason to go GAN for what would ordinarily be a mosfet job at maybe 100KHz is that this is an envelope tracker, it needs to be able to swing that output terminal around between maybe 15V and 48V at 10s of Khz rates, into a capacitive load, while having nearly no switching residual on the output, so a high frequency is indicated. I am thinking in terms of maybe a 1MHz switching frequency and 3 Phases, or a 500KHz switching frequency and 6 phases, for a 3MHz output fundamental.

Could one of the power guys with experience with these devices comment please?

Regards, Dan.

[dmills]

So EPC in either naked or TI variant is the way to go then?
Damn I hate hand placing BGAs, but needs must I guess.

Do you know if the EPC parts cool in a useful way thru the top of the package? Mounting them on the bottom of the board and clamping to a heatsink holds a certain appeal.

Regards, Dan.

[owiecc]

They can be top cooled: http://epc-co.com/epc/Portals/0/epc/documents/product-training/Gallium%20Nitride%20Transistor%20Packaging%20Advances.pdf

[ransonjd]

I have experience with earlier generation EPC parts. The EPC packages are a bit of a nuisance to work with. If they're attached to planes, hand reworking them is no fun at all, but I've done it many times.

I used several of their earlier parts in 10MHz+ switchers, and there was very little gate drive margin between fully-on and damaging the gate. This may be improved with later revisions. Make sure that you don't have any ringing in excess of the Vgs absolute maximum limit. Measure it with a differential probe so you can see the actual waveform through any ground bounce.

Heat sinking them is feasible, but they're easy to crunch if you do something wrong. If you can get all of the power out through the bottom, I would endeavor to do so.

Also, and this is generally true of GaN, remember that the "body diode" of a GaN part isn't a standard junction diode, and can have very high forward voltage.

I can't compare them to the other GaN products.

[jbb]

48V 2kW is a bit of a monster for an RF amp.  Have fun with that. (And by 'have fun' I mean 'cower in fear of RF burns'.)

I haven't used the EPC devices, but a friend who has told me that yes, they do what they say. Provided that you carefully follow the layout and mounting guidelines.

It's apparently important to use a 4 layer board and really squeeze the loop area down. Using a 2 layer board, the return path is too far away and the loop inductance leads to extra switching losses.  I guess you'd want to use half bridge modules if EPC makes them.

[dmills]

2kW of DC, so given the nature of a broadband class AB RF power bit, probably about 1kW or so PEP and much less average (which is the whole point of envelope tracking!). Yea RF burns from that sort of thing do suck!

I will probably wind up going with the TI 80V part, looks easy to layout and it is not THAT much more expensive then the EPC part plus gate driver in Digikey sorts of quantities, and it makes that whole annoying gate drive loop go away.

4 Layers is pretty much my starting point these days.

Now if any one has a good idea for peak current sensing at MHz switching rates? My plan at the moment is to use average current sense at the OUTPUT of the converter stages, but that has less then ideal dynamics (Basically I would end up running the thing open loop CCM with small fiddle factors applied to balance the currents across the stages). Ideas would be welcome.

This thing is going to have some really fun learning I suspect.

73 Dan.

[T3sl4co1l]

48V 2kW is a bit of a monster for an RF amp.  Have fun with that. (And by 'have fun' I mean 'cower in fear of RF burns'.)

I haven't used the EPC devices, but a friend who has told me that yes, they do what they say. Provided that you carefully follow the layout and mounting guidelines.

It's apparently important to use a 4 layer board and really squeeze the loop area down. Using a 2 layer board, the return path is too far away and the loop inductance leads to extra switching losses.  I guess you'd want to use half bridge modules if EPC makes them.

The main downside to larger GaN devices is, at some point, the package physical dimensions exceed the minimum loop inductance required to use such a device, and the advantage evaporates.

Remember, loop inductance is proportional to size.  Basic physics.  There's not much you can do in the layout to help it.  You can bring layers closer and use more vias to help reduce it, but it will always be proportional to the overall length dimension.

You still have reduced Qoss and gate drive requirements, which helps keep efficiency high, but switching speed and therefore filtering components (L and C) don't shrink nearly as much as you'd like.

It's unfortunate EPC doesn't make high voltage parts.  Looks like most of the HV parts around right now are GaN Sys., and cascodes (from Transphorm, and ON Semi licenses them too).

Tim

[dmills]

Which is why I am going for a multi phase design, keeps the individual phase currents reasonable, and increases the effective switching speed.

Only problem is the current sensing because I really hate the notion of a current transformer in the high side drain connection!

Decisions, decisions.

73, Dan.

[T3sl4co1l]

Yeah, the future of high efficiency, compact converters would seem to be using a shitton of phases.  GaN at 10kW is going to be little different from an FM radio transmitter module, with a rectifier on the output, and more phase shift between modules.  Someone should cook up a controller that can be trivially connected in more phases and operates at high frequency...

Tim

[jbb]

For highest current sense bandwidth you’re probably looking at very careful shunt resistors. Obviously the inductance will be really important. Perhpas several 0402s in parallel would be appropriate?

A high side shunt and sense amp will be tricky in terms of sense amp bandwidth. But if you throw away thoughts of DC accuracy you might be able to swing it.

A low side shunt might actually work better (use valley current control), but would require special care for the VCC, HI and LI inputs.

Alternatively, you could try to use the on resistance of the low-side GaNFET as your sensor. This would not add leakage inductance (yay!) but does require a bit of cunning analogue work (and perhaps temperature compensation - maybe a thermistor near the device could do a good enough job) to sense 100mV on the switch node, but it should be possible (yay or boo, depending on your tastes).

[rx8pilot]

I have been experimenting with EPC devices - they seem to be the current leaders. Also the VP of sales and two very sharp engineers came to visit me, offered considerable help, and gave me one of their books about designing with eGan. It is a really well done book.

As the frequencies go up, the PCB parasitics all start to really have me scratching my head. It is so easy to make a mess with high frequency, high current, polyphase designs. My next effort is going to try blind/buried vias to tighten the layout up. My goal is to have high density and high efficiency but EMI is a real consideration too.

Hand assembly is not that difficult, although a few steps up from soldering 0805 resistors. I have machined heat spreaders and a thermal interface from Panasonic
https://www.digikey.com/products/en?keywords=p122034

The heat is concentrated in such a small area - the thermal interface needs to be pretty good.

OP - what are you using for control on this project?

[JohnG]

Having some experience with EPC's GaN FETs, I would caution one that current sensing in the power loop will add inductance, and this will both slow down switching, and increase turn-off ringing. It is best avoided.

That being said, I have had some luck with using multiple (4-5) 0402 resistors in parallel. I find that the Susumu RL series to be a good choice. Do not put them between the FET source and source return of the gate drive since this adds common source inductance that will slow things down.

Another issue is the tradeoff between loss and accuracy. Very fast edges contain high frequency content into the hundreds of MHz and higher. For accurate measurements of waveforms, it does not take much inductance in the shunt to dominate the resistance. For example, 200 pH and a 200 MHz equivalent BW switching edge gives about 0.25 ohms. These are ballpark numbers, but not unrealistic. To measure current reasonably well, you want the shunt resistance to be at least 5-10X higher, which puts you in the range of 1-2 ohms. That's pretty high if you are carrying 10s of A.

You can mount the resistors upside down and this can save more than 100 pH, which will help. Board assemblers really like to complain about this for some reason .

John

[JohnG]

Forgot to add, if you can use leading edge blanking on the current sense, you don't need to worry as much about the edge since you are ignoring it, and you can get away with lower value resistors.

John

[rx8pilot]

You can mount the resistors upside down and this can save more than 100 pH, which will help. Board assemblers really like to complain about this for some reason .

John

It would be fun to ask just to see the look on their face. :-)

[JohnG]

You can mount the resistors upside down and this can save more than 100 pH, which will help. Board assemblers really like to complain about this for some reason .

It would be fun to ask just to see the look on their face. :-)

It's especially fun when they realize you are seriously asking them  .

[T3sl4co1l]

That being said, I have had some luck with using multiple (4-5) 0402 resistors in parallel. I find that the Susumu RL series to be a good choice. Do not put them between the FET source and source return of the gate drive since this adds common source inductance that will slow things down.

Wide style resistors are also quite nice. If you need lower inductance, use two in parallel!

Another issue is the tradeoff between loss and accuracy. Very fast edges contain high frequency content into the hundreds of MHz and higher. For accurate measurements of waveforms, it does not take much inductance in the shunt to dominate the resistance.

Doesn't much matter, just follow the resistor with an R+C to the sense pin -- match time constants (L/Rs = R*C) and you're good to go.

This also eliminates the quasi-static error due to inductance, that blanking will miss.

Tim

[dmills]

Current sense:

How about doing the low inductance resistor thing in the high side drain and then using a voltage transformer across the resistor? That way I get the isolation from the transformer together with the desired large common mode rejection and the low inductance from what is basically a resistive shunt. Resetting the transformer flux will take a little thought, maybe a series cap so the flux resets thru the current sense resistors during the off time? Needs some Spice I think.

I am thinking that the control for this whole dogs dinner is likely to be a smallish FPGA, and that I can probably use the LVDS receivers as seriously fast comparators for the current loops. That part of the action is going on a separate board for obvious reasons. 

I can see the look on our assembly house guys face now "Note R1-R4 are to be fitted face down", sort of thing you can do on a prototype, but that is a fair bit harder on production units.

Regards, Dan.

[dmills]

Doesn't much matter, just follow the resistor with an R+C to the sense pin -- match time constants (L/Rs = R*C) and you're good to go.
This also eliminates the quasi-static error due to inductance, that blanking will miss.
Tim

The same thing you do when using inductor ESR current sensing (Actually that is not a horrible thought)?

73 Dan.

[JohnG]

Wide style resistors are also quite nice. If you need lower inductance, use two in parallel!

Another issue is the tradeoff between loss and accuracy. Very fast edges contain high frequency content into the hundreds of MHz and higher. For accurate measurements of waveforms, it does not take much inductance in the shunt to dominate the resistance.

Doesn't much matter, just follow the resistor with an R+C to the sense pin -- match time constants (L/Rs = R*C) and you're good to go.

This also eliminates the quasi-static error due to inductance, that blanking will miss.

Tim

My boards with the matched time constants are already queued up for a build, so I'm glad to hear it might work. I tried it on hacking up another board with so-so results, but it was also not pretty. Promising enough that I laid it out, so we will see in a few weeks.

Wide resistors are a promising idea, but I found that they are sometimes not a wide element. Some of them adjust the resistance by scribing the element in a line across the part, and this had a pretty large effect on the inductance. I found this out because I was trying out a Susumu PRL resistor with long side terminations and a face down element, i.e. the same as what mounting the resistor upside down would achieve - exactly what I was looking for. When the inductance was higher than expected, I scraped off the coating over the element, and it was scribed from the short side, on one side only! So, not only was the inductance higher, it was no longer symmetrical around the pickup point.

But, they are otherwise very nice resistors, and Susumu has another resistor worth looking at, the PRL series: http://www.susumu.co.jp/common/pdf/n_catalog_partition07_en.pdf?v=20170706. If you look at the picture on the data sheet, you will see that it looks like a bunch of RL resistors, but they dice them so that one substrate has multiple parallel elements. I have not examined one closely, though, so that's just speculation on my part.

John

[T3sl4co1l]

Doesn't much matter, just follow the resistor with an R+C to the sense pin -- match time constants (L/Rs = R*C) and you're good to go.
This also eliminates the quasi-static error due to inductance, that blanking will miss.
Tim

The same thing you do when using inductor ESR current sensing (Actually that is not a horrible thought)?

Yup.   Which is also something that can be done, but ESR varies with temp... ugh?

Despite the cruddiness of that method, there are plenty of controllers for it, probably including most motherboard Vcore supplies.

Hey, it's still better than voltage mode...

Tim

[dmills]

Hey, it's still better than voltage mode...

That is pretty much a given, and at least the tempco goes the right way for once!

Regards, Dan.

[jbb]

I could be wrong, but I think inductor DCR sensing needs so much filtering that it’s effectively average current sensing. And yes, the DC resistance change is a pain in the backside.

If inductor current sensing is sufficient, you could place shunt resistors between the inductor ‘output’ and the DC out filter caps. The sense amps would have to deal with some AC common mode (that’s the whole point of a tracking generator, right?) but there would have way less dV/dt to deal with. Bandwidth would still be a challenge (I guess > 10MHz BW required for peak current control).

Hmm...

How about grounding the SMPS control stage to the DC Out rail (so it has direct access to inductor current sense resistors) and using digital isolators to get the gate drive and communications signals out?

[T3sl4co1l]

I could be wrong, but I think inductor DCR sensing needs so much filtering that it’s effectively average current sensing. And yes, the DC resistance change is a pain in the backside.

Not quite. That would be a two pole filter, at least.

Integrating a square wave makes a triangle; integrating a triangle makes a parabola; and so on.  The amplitude goes down each time, the latter usually being good enough for average current mode controls without blowing the phase margin too badly. 

If inductor current sensing is sufficient, you could place shunt resistors between the inductor ‘output’ and the DC out filter caps. The sense amps would have to deal with some AC common mode (that’s the whole point of a tracking generator, right?) but there would have way less dV/dt to deal with. Bandwidth would still be a challenge (I guess > 10MHz BW required for peak current control).

Hmm...

How about grounding the SMPS control stage to the DC Out rail (so it has direct access to inductor current sense resistors) and using digital isolators to get the gate drive and communications signals out?

This works for controllers that are made for it, of course; or for discrete designs, like I've made a few all-transistor designs based this way.  (I used a low side current sink to program the high side current -- it's effectively a switching current mirror.)  It can be particularly attractive for more tightly integrated gate drivers, in higher power inverters where it's worthwhile to do.  Example, a multiphase buck, some kW, with isolated (high side) gate drive, current comparator and desat protection; you still need some kind of isolation to set the current threshold, but that's relatively easy (lower bandwidth than the inductor current directly).

Unfortunately, putting so much logic on a high frequency (GaN) driver circuit would be inconvenient.

Tim