The old-skool tricks that let you do serious debugging with a two channel non-storage delay timebase CRO were mostly based on making the CPU repeat a short sequence of instructions and generating ONE trigger pulse at a point within that sequence fed to the Ext trigger input. That meant that the scope trace X coordinate was locked to the instruction sequence timing, so you could probe a pair of signals, trace them onto tracing paper, then probe another two and repeat until you had all the signals you needed recorded on the paper, with correct relative timing. Nowadays, you'd photo them with a digital camera on a mount attached to the scope or from a mini-tripod so all the pictures are from exactly the same angle and distance.
Once you've set up a repetitive signal with stable triggering, the B timebase can be used for zooming in on a particular part of it. If you press the A INTENS button, it will use the B timebase for the sweep, and if the A timebase is set faster (lower time/div) it will bright up the trace, for a region controlled by the A timebase setting and the DELAY TIME POSITION knob just above the Ext input. Press the B button and the intensified region expands to the full width of the screen.
For the triggering from a particular logic pattern, one would typically use two banks of DIP switches, some magnitude comparators and pullup resistors on all the comparator inputs. One bank of switches would ground each bit individually of one set of the comparator data inputs, so switch open = '1' and switch closed = '0'. The other bank of switches would go between the signals being monitored for the logic pattern and the other set of comparator data inputs, so switch closed = active and switch open = Don't Care. With enough comparotors, switches etc. that would let you generate a trigger pulse on any single memory or I/O access.
However all the above is useless if you cant get the instructions to repeat fast enough to get a bright enough scope trace to read. If you were pushing the limits of trying to view a rare event, you'd have to darken the room to see the faint trace.
Nowadays, you'd stop faffing around with custom triggering a lot sooner than that, and just use it to establish that all the memory chips and I/O chips can be accessed with acceptable timing. One trick that can be used is to burn an EEPROM with an instruction sequence terminated by HALT. When it reaches the HALT, the Z80's /HALT pin will go low, and if its arranged to pull /RESET low once /HALT has been asserted for a short time, the CPU will reset and repeat the instruction sequence. You can then trigger the scope on the rising edge of /RESET.
Once you've got it basically accessing all the memory and I/O chips with acceptable timing, further troubleshooting is best done with a cheap logic analyser.