Ground planing for 8MHz SPI signals

[Pack34]

This is more of a best practice question. I'm working with some 32-MHz clock, 8-MHz SPI signals talking between a PIC and an ENC28J60 Ethernet controller.

http://www.microchip.com/wwwproducts/devices.aspx?ddocname=en022889

It's a two layer board with ground fills on both the top and bottom. Some ground plane stitching was required to get a good fill across the board. Anyway, at what frequency range would best practices require moving to a four layer board to ensure a ground return path directly below the data lines in order to improve signal integrity?

The signals in the attached scope print-outs are rather noisy and there seems to be some cross-talk going on, but the data is getting there. None of it seems to be approaching the threshold voltage to cause a bad read, just would appreciate a pointer or two to clean everything up.

[nfmax]

To me that looks suspiciously like a probing problem, judging by the ringing on the pulse edges, and what looks like coupling into some of the signals. How are you connecting your probe grounds to the circuit? You need a very short return path with edges that fast. The N2683B probes come with a grounding spring which is the right one to use here. If that makes the problem go away then your PCB is probably good.

[Carrington]

I think the rise time (and fall) is more critical.
For example for times under 1ns is recommended to use high speed connectors.

With respect to the ground plane and a four layer board, I will wait to see what others think.

[Scrts]

8MHz is a really low frequency and 2 layer board is fully sufficient for that. You should remember to route clock signal a bit further than the data pins, but proper GND polygons and stitching allow to achieve really good results.

[Carrington]

To me that looks suspiciously like a probing problem, judging by the ringing on the pulse edges, and what looks like coupling into some of the signals.

And the oscilloscope itself (cross-talk between channels).

[JJalling]

You should remember to route clock signal a bit further than the data pins, but proper GND polygons and stitching allow to achieve really good results.

The clock a bit further? Can you please elaborate? Do you mean the clock trace should be longer?
Well, while writing this I come to think that you mean that the trace should be placed a little apart from the data lines right?

BR Jonas

[Pack34]

Grounding of the Probes:
I soldered a grounding wire, about three inches, to a connector near the PIC.

Probing situation:
I'm using the SPI decoding feature of the Agilent, with each analog channel being used. I tacked on small probing wires to the series resistors between the PIC and the transceiver.

Trace Lengths:
Clock= 56.95 mm
MOSI = 49.77 mm
MISO = 51.33 mm


The reason why I'm asking all of this, is that the circuit seems a bit finicky. The transceiver is a 3v3 chip with 5v tolerant inputs. It worked fine on a couple designs and a dev board without any level shifting. On another prototype I needed to install an AND gate on the MISO line to bump it up to 5V and I do not quite have one board troubleshooted out. All of the MCUs used have a really wide opperating voltage of 1.8 to 5.5V. I'm thinking it's potentially a signal integrity issue.

Due to how compact this board is, the SPI lines are mostly grouped together (as shown in the trace widths above) and are spaced close enough that there is no ground fill in between. I was curious if it could potentially be some grounding issue because there isn't a clear and direct return path on this board. There's some signals going north-south on the bottom side of the SPI east-west traces. There's also an oscillator under one part of it.

The data from the PIC is obviously getting to the transceiver because it's responding to the PIC's SPI commands with values, but the PIC isn't responding to the MISO values. The conversation on the scope diagram is the status request from the PIC. In it is a read command asking the transceiver if it has any data. When the PIC sees that there's data it queries for what the data is.

[nfmax]

There's your problem! Your track lengths are in metric and your ground wire is in inches!

Seriously, 3" is too long a ground lead for this kind of signal. It also sounds like you need a ground return trace somewhere near your SPI bus signals: a full ground plane is probably overkill.

Can you post a picture of the circuit with your probes in place?

[Pack34]

I pulled a NASA!

I've attached my setup

[Alex Eisenhut]

I pulled a NASA!

I've attached my setup

Oh no no. That's no good. That'll show you the bits, but if you want to see the grunties you're gonna have to get a lot closer than that.

You need to find where these went:

[nfmax]

Looking at that picture, like Pack34 said, I think the probe connections are the main cause of the ringing and coupling between signals on your 'scope pictures (most clear on #4). Obviously the 'scope is able to decode the SPI bus despite this, but that doesn't guarantee that your circuit will. One thing that might be worth a try is to solder an extra 'ground track' wire onto your PCB, one end near each of the two devices on the bus, and routed close to the bus signals, to give a more direct return path. If that makes a difference you may need to modify your pcb layout.

[nfmax]

Sometimes a dual lead adapter like this is handy. Not as good as the spring ground, but you can solder a couple of square header pins to the PCB and the adapter plugs right in.

[Pack34]

Ya, the ringing looks like it was a probing issue. I've attached some printouts of the scope when using the spring ground on various signals. The ringing and crosstalk seems to go away when I use the attachment on that signal.

The bits seem really clean at their destination ports

[T3sl4co1l]

Seems like your ground is crap... which is probably a probing problem still?

Routes under say 10" long, with common HC CMOS / TTL level signals, unlikely to have problems.  A board that size, with stitched ground, should look a lot better than that, and any squigglies should be much shorter (~1ns).  None of your scope shots are nearly fast enough to be able to view that sort of stuff; you're seeing crosstalk from something, or maybe some really nasty supply bounce (not as well stitched as you thought, or bypassed?).

Signals on board are generally very clean.  It's hard to get much trash on anything routed within a PCB, unless it touches a connector, or runs at high speed (sub-ns edges -- needless to say, you need a scope with sub-ns risetime to pair with it).

The point where signal quality demands multilayer construction is going to be high speed (LVCMOS and faster, ECL, LVDS, etc.) and either high density (no room to stitch ground around the controlled-impedance traces, which have to be rather wide on a two-layer board), large area (e.g., backplanes, computer boards, etc.?), or both.  In such projects, routing demands almost always take priority -- an FPGA isn't much use to you if you only have two layers to fan out its pins on, for instance.

Tim

[Alex Eisenhut]

Say, I wonder if your probes are properly compensated for each channel? Hmm?

[Carrington]

I've attached my setup

Moreover I can see only one probe connected to ground! 
Some times a picture is worth a thousand words.

[Sebastian]

For this kind of stuff you have to connect all probes to ground (as short as possible).
Your method of only connecting one ground is only used for power electronics at low frequency because of the ground voltage differential at high currents.

[megajocke]

Are the MCU inputs expecting TTL or CMOS levels? 3.3 V levels from the transceiver chip would be out of specification if it expects 5 V CMOS levels.