Guesstimating schottky I(t_pulse) SOA

[Siwastaja]

Hi,

I'm using a PMEG2020 (www.farnell.com/datasheets/1817507.pdf) as a low-dropout, low-recovery-charge freewheeling extra in a synchronous buck converter (half bridge), in parallel with the FETs. The diode is specified for 2A average current; the peak I'm using it at is 25A, but only lasts for around 50-100 ns before the FET takes over. No blown diodes so far.

Another case is a failure mode where inductor saturation protection kicks in and disables both FETs. In this case, the peak current though the diode is the same, but lasts for considerably longer, like 20-30 us. I have developed safety shutdown code which manually asserts the right FET to discharge the inductor first to about 10 amps of residual current, so that the diode doesn't need to handle more than that for more than about 10 us.

Long story short, I'm prototyping this because the datasheet doesn't provide SOA curves for pulses. It only specifies non-repetitive peak current of 5A at Tj=25 degC (ridiculous Tj), pulse duration being 8 ms. Luckily, 8 ms is over two orders of magnitude longer than what I need even in the fault situation, or five orders of magnitude longer than the normal operation case. But this is why I have hard time guesstimating the peak current for 100ns (repetitive, duty = 1%) and 10us (non-repetitive) pulses I'm interested in. I'm already testing through prototyping, and it's working very well so far, but if anyone has direct experience on similar type schottkys, I'm all ears.

[tatus1969]

as long as you don't overheat the die during any transient, you should be safe at any current that you pump through it. I do not know if there are limits in dI/dt or dV/dt for Schottky diodes, maybe one of the experts can answer that.

You could try to estimate the die size from the duty cycle graphs, but maybe the simplest way is to crack one diode open and measure it. Take the thermal capacity of silicon, and you get a figure of the milliJoules that it can handle for a single burst during inductor saturation at given ambient and max junction temperatures. The idea is that the thermal energy created from very short pulses is entirely stored in the die, instantaneously heating it up. You only have to make sure the max junction temperature is not exceeded. This is not considering possible lifetime degradation due to thermal stress though. Anyhow, this strategy is frequently used for MOSFETs when it comes to calculating avalanche or UIS (unclamped inductive switching).

The 50-100ns peak should be safe in any case, as the amount of deposited energy is only in the microJoules range per pulse.

[MagicSmoker]

...the peak I'm using it at is 25A, but only lasts for around 50-100 ns before the FET takes over. No blown diodes so far.

It's quite possible that very little current is diverting to the external Schottky during the dead time between turning the buck FET off and the sync FET on because it is only the difference in forward voltages that is available to slew current through the stray inductance between the two devices.

Say, for example, there is 2nH of loop inductance, the current flowing through the buck FET just prior to turn off is 25A, the forward voltage of the sync FET body diode is 0.8V and Vf for the Schottky is 0.4V. The inductor equation says it will take 125ns for the current to completely transfer from the internal body diode over to the external Schottky.

Hence why FETs with co-packaged Schottky dies are so popular in this application. They tend to only come in very low Vds ratings, however.

[T3sl4co1l]

1. Don't worry about it.
2. It's futile anyway.

I laugh at the LTC3810 application because they recommend a puny 1A, 100V diode in parallel with a big fuckin' 20A+ MOSFET.  Under no condition will the schottky ever draw more current than the body diode.  It's completely superfluous, and works just as well without it (you can't tell the difference, of course).

3. If you have the option, set the dead time as close to zero as possible, or slightly negative (overlapping).  Add dI/dt snubber and V clamp to the supply.  This prevents forward bias of the body diode, which has very slow recovery and high losses.

Tim

[Siwastaja]

1. Don't worry about it.
2. It's futile anyway.

Actually, the diode does make a real difference!

There are some results:

Test #	Description	Input voltage	SW node peak
1	No diodes	8.89	18.0V
2	PMEG2020 on bottom	8.89	15.8V
3	Same as previous, but higher Vin and Iout	10.78	17.8V
6	Same as previous, but PMEG2020 on bottom AND top	10.78	14.3V
11	two parallel PMEG2020 on bottom AND top, RC snubber on bottom	10.78	13.0V
13	two parallel PMEG2020 on bottom AND top, RC snubber on bottom AND top	10.78	13.0V

Scope images of the tests available if anyone wants to see. (Actual peaks may be higher because the peaks are measured with the 100MHz Rigol.)

The measurement uncertainty hides the small differences in efficiency, there may be so little efficiency benefit that it doesn't matter, but the peak voltage reduction, reduced ringing and reduced EMI make the diodes worth it.

Adding common source inductance on the bottom FET Source leg also helped a bit with the SW node peaking. Currently, it's 1 cm PCB trace.

I tested some other diodes (VS-2EJH02-M3 and BYG22D-E3 - I was after soft recovery) on the top, but they offered less benefit than the PMEG2020.

I have minimized the inductance between the FET and the parallel diode, they are less than 1mm apart on the PCB, directly on big copper pours.

[Siwastaja]

I laugh at the LTC3810 application because they recommend a puny 1A, 100V diode in parallel with a big fuckin' 20A+ MOSFET.  Under no condition will the schottky ever draw more current than the body diode.

You mean the one on Page 1 ( http://cds.linear.com/docs/en/datasheet/3810fc.pdf )?

Let's see if I understand:
With Iout=6A, assuming a design current ripple of 2A, the maximum inductor current (and current through the bottom FET) would be around 7A.

The FET datasheet (http://www.vishay.com/docs/71603/71603.pdf , page 3) says that at 7A, body diode Vf is between 0.77V (Tj=25) and 0.52V (Tj=150), so at a realistic Tj=100ish, Vf would be roughly around 0.6V. (*1)

For the diode (http://www.onsemi.com/pub_link/Collateral/MBR1100-D.PDF fig 1), they say that at 7A, at Tj=100, Vf would be 0.72V. Realistically, because of the rather low losses at the diode, Tj would be less than 100 degC, so that Vf would be even higher.

So, you seem to be right; body diode Vf < diode Vf (0.6V < 0.72V), so body diode takes practically all of the current.

But maybe the diode is faster to turn on, providing the current path more quickly, even though the Vf is high enough not to prevent most of the current from finally flowing through the FET body diode.

*1) The figure on page 3 however contradicts the numerical data (0.8Vtyp 1.2Vmax at 4.3A Tj=25); the graph says 0.75V for the same data point! Under what conditions does the "maximum" happen?

It's impossible to do the identical datasheet analysis on my circuit, because the PMEG2020 datasheet stops plotting the Vf at 5A. I'm quite sure, however, that Vf exceeds the 0.7V of the FETs body diode at 25A (my FET: PSMN2R8-25MLC), so the positive effect I'm measuring must be related to the dynamics of the circuit. OTOH, the tests were run at Iout=10A, which means Ipk=13A; the positive effect from the diode may disappear when I go to full power operation. I haven't measured full output current without the diode!

[David Hess]

An estimate can be made based on the pulse SOA graph from another manufacturer's similar diode.  Measuring the diode's temperature rise in the circuit will also be informative.

If you want to spend the time and effort, a test setup which pulses the diode and then measures the change in forward voltage drop can reveal the rise in junction temperature.

[MagicSmoker]

...
The measurement uncertainty hides the small differences in efficiency, there may be so little efficiency benefit that it doesn't matter, but the peak voltage reduction, reduced ringing and reduced EMI make the diodes worth it.

I bet most - if not all - of the benefit you are seeing from the external Schottky is from its junction capacitance, and not so much because it is conducting. It might be interesting to try subbing in a low-pF NP0 capacitor for the Schottky and see if you get similar results.

...
I tested some other diodes (VS-2EJH02-M3 and BYG22D-E3 - I was after soft recovery) on the top, but they offered less benefit than the PMEG2020.

Both of those are conventional (pn junction) rectifiers which tend to have much lower junction capacitance than a Schottky of similar current rating.

I have minimized the inductance between the FET and the parallel diode, they are less than 1mm apart on the PCB, directly on big copper pours.

1mm of distance between components = ~2mm of trace length, and inductance of a trace in which the return current *does not* flow through a ground plane immediately below it can be approximated at 1nH per mm. Hence why I used 2nH as the estimated stray inductance previously.

[tatus1969]

as this is a MOSFET switching application at less than 20V, I would suggest not putting any effort in SW node peaking. The transistors will handle peaking at any level, you don't need to worry about that. Overvoltage will only trigger Avalanche conduction, the transistor acts like a Zener diode then. It will survive that forever as long as the die doesn't overheat. To be on the safe side, you may choose an UIS rated transistor, that is specifically qualified for this situation.

EMC should most probably also not be a concern. If your switching frequency is not in the MHZ range, you could reduce excessive ringing by increasing gate resistor values. I just had 30V / 25A / 30kHz BLDC controller in a certified test lab, no load though, and the analyser did not show anything above its noise floor up to 1GHz. The cable running to the motor was not even shielded. I was still surprised though.

p.s. there are many H bridge controllers that don't like negative SW voltages. Almost all IRF types fall into this, I once had a 150V / 25kW PMSM controller spitting fire because of that.

[T3sl4co1l]

Not exactly. A Schottky diode may not take full current for long time, but the purpose of it is to handle the time gap between low side FET turns on and top FET turns off.
In case dead time is long, the Schottky diode reduces body diode current, hence reduce injected carrier concentration, hence reduce reverse recovery loss when top FET turns back on.

I measured the dip during the dead time.  About 30ns wide, 1.1-ish volts below GND.  Identical before and after the schottky.  At around 5A output and 60V input, I think.

My response was perhaps a bit knee-jerky since the OP is working at much lower voltages (PMEGs are a little better than B1100s, too), but as the OP mentioned with datasheet values, it will definitely be close enough that it's no slam dunk.

The point about junction capacitance alone having a snubbing effect is an excellent point.  I'd like to see that comparison, too.

A group in our facility have invented this, and it works the exact same way, but in our case the Sckottky is a bit beefier. https://news.ncsu.edu/2015/09/paired-switches-boost-performance/
Another reason for using a Schottky (placed close to FET) is to reduce kickback voltage caused by parasitic inductance. I observed that at high di/dt, sometimes kickback EMF can propagate through Miller capacitance, then destroy FETs and gate drivers.

That's pretty nice, and you can tweak timing and parasitics so the MOSFETs slightly interfere and there is never downtime where junctions are allowed to forward-bias.  Which would be an exceptionally bad sin to commit at such high voltages and frequencies -- the recovery times will be low microseconds, no?

Tim

[Siwastaja]

Wouldn't junction capacitance alone, without any series resistance, be a bit more problematic, generating an LC circuit? I guess the RC snubber I do have should do this job already, so if the diode has noticeable extra effect in addition to the RC snubber, then it's probably because of the diode conduction. -- The order I worked with, however, was to first add the diodes, then the snubbers, so I don't have a datapoint with the snubbers but without the diodes. If I do find the time to do extra measurements just for the learning, I will add two measurements:
- Diodes replaced with a NP0 0402 cap emulating the junction capacitance.
- Snubbers like I have now, but no diodes


About not watching the SW node peaking; the previous iteration did blow some fets every now and then before I added the snubbers. I measured SW node peaking at about 24V (again with a 100MHz scope with 1:10 passive probe, so in reality, a bit more), 25V being absolute maximum for the FETs, so it was clearly going over, but not that much, and it did cause dead FETs. The ringing was also coupling to the analog control side. Snubbers were the solution. In my own experience, I don't quite believe the robustness of the FETs avalanching in practice...

With this design, I seem to have better layout and less ringing anyway.

[T3sl4co1l]

Wouldn't junction capacitance alone, without any series resistance, be a bit more problematic, generating an LC circuit? I guess the RC snubber I do have should do this job already, so if the diode has noticeable extra effect in addition to the RC snubber, then it's probably because of the diode conduction.

You already have an LC circuit, whether you choose to accept it or not!

Indeed, adding L is useful.  Please expunge it from your mind, the traditional concept of "minimize inductance"!  It should be optimize, not minimize. 

The optimal L is approximately that which gives Zsw = Zo.  That is,
Zsw = Vpp / Ipk
The switching impedance is the peak-to-peak voltage (for a buck, the supply voltage; for a boost, the output voltage) divided by the peak load current.  (In a practical converter, the load inductor is relatively small, so the peak load current is different during different parts of the waveform.  So you get a Zsw for turn-on, and turn-off.  This is fine.)

Zo = sqrt(L/C)
Where L is the total loop inductance in the switching circuit, C is the total capacitance across it (usually junction capacitance), and Zo is the characteristic impedance of that LC network.

Under the condition where Zsw = Zo, the ideal turn-off voltage overshoot (when switching on/off at Ipk) equals Vpp, i.e., the peak switch voltage is double Vpp.  This much excess is certainly inconvenient, but choosing a smaller Zo leads to proportionally lower overshoot, as does the application of a dV/dt or Vpk snubber.  Since it's proportional, you can tell at a glance, how much smaller it needs to be -- maybe 20% of this figure, perhaps, to get an acceptable overshoot level.

The most important factor for an efficient, low EMI synchronous converter, is the commutation time -- and any uncertainty in it.  This needs to be less than the switching time constant,
t_sw = pi*sqrt(L*C)/2
This is the time required for the load current to fully commutate from one switch to the other.

Most importantly, once you realize the position of all inductors and capacitors in the circuit, and the proportions of them (which gives the time constant and impedance), you can trivially apply anything else from linear network theory!  You can dampen the L with parallel R, or the C with series R, to reduce ringing.  (Usually, direct access isn't practical, so you add a R+L or R+C across the relevant components.)  You can apply a rectifier to divert the pulsed load current into a reservoir, and recycle the snubber energy.  Lots of good things!

There is no need to throw up your hands and panic at peak voltages and surge currents.  All these values are well defined, and in control of the designer!

About not watching the SW node peaking; the previous iteration did blow some fets every now and then before I added the snubbers. I measured SW node peaking at about 24V (again with a 100MHz scope with 1:10 passive probe, so in reality, a bit more), 25V being absolute maximum for the FETs, so it was clearly going over, but not that much, and it did cause dead FETs. The ringing was also coupling to the analog control side. Snubbers were the solution. In my own experience, I don't quite believe the robustness of the FETs avalanching in practice...

No, MOSFET avalanche is undesirable.  It leads to free charge carriers, which persist for some time -- the same reason the body diode reverse recovery is poor.  So the power dissipation, in a switching circuit subject to repetitive avalanche, is much higher than expected.

Applying external clamping, and suitable overrating (Vds(max) at least 20% more than needed), have never led me into any failures.

Tim

[aandrew]

I just want to say that this thread is a perfect example of why I love open discourse. I have no specific interest in the SOA of a diode, but the discussion on design and specifically the optimization of a circuit to achieve a better result is priceless.

Thank you for all the nitty-gritty analysis and explanation!

[Siwastaja]

Indeed, thank you for diverging from the original question. Since we are now discussing this more broadly, how about I post the layout in question? Here are some specs:
Vin=9...14V (typically: 10.8V)
Vout=1...5V (typically: 2.0..4.5V)
Iout=20A
fsw=150kHz
L=3.3uH
Bottom FET: PSMN2R8-25MLC
Top FET: PSMN9R0-25MLC

It's bidirectional, so in/out are named from the buck viewpoint. It's a li-ion cell charger and discharger. The PCB is 4-layer, the power switching components are on the bottom, control and FET driver on the top. Both mid layers are ground planes. Ceramic bypass caps (4.7uF 25V X5R 0805) are scattered on both sides, 7 on the bottom, 9 on top. Two 0.1uF 0603 caps are provided nearest the FETs. Four 680uF Panasonic FR series elcaps provide bulk storage and some dampening ESR. RC snubbers are 4.7nF + 1.3ohm, found by experimentation.

Indeed, I have learned (from T3sl4co1ls older posts, for example!) that minimizing the inductance is not how it should be automatically done. So how I understand is that, by default, we minimize inductance (in most places), then add inductance where it belongs. So I started by simulating this bridge in LTSpice, adding 2nH of inductance in every possible place I could think of, then minimizing each of them separately and finding when minimizing it helps, when it doesn't. I found that inductance indeed is beneficial in the bottom leg of the bridge (lot of papers can be found by googling "common source inductance").

So, I added this extra trace so that the bottom mosfet source is not directly connected to the ground plane, approximated to add about 2nH. I bypassed it in prototyping (I did leave a mask layer opening so it can be easily soldered directly to the adjacent ground plane), and saw that without this inductance, the SW peaking rose from 17.8 to 18.4V. I bet the positive effect would be greater if I still increased this inductance a bit more, but it's not easy at this point.

Overall, the circuit is working really well, and with both snubbers and diodes in place, the overshoot is only 20%, RC snubber loss contributing only 0.1% efficiency penalty at full load.

In addition to measuring SW peaking, I also started measuring Vin with AC coupling to get a rough idea of noise injected into the control side. RC snubbers reduced the p-p voltage in Vin node from 0.5V to 0.3V. I understand that spectrum analysis would have been more helpful than the amplitude alone.

[tatus1969]

how hard are you switching the transistors, i.e. what gate resistance do you use and what controller is in place? What switching time do you achieve? I ask because I have several comparable designs at higher frwquencies with absolutelyno peaking present. The transistors you use are modern low inductance soft switching types.

[Siwastaja]

how hard are you switching the transistors, i.e. what gate resistance do you use and what controller is in place? What switching time do you achieve? I ask because I have several comparable designs at higher frwquencies with absolutelyno peaking present. The transistors you use are modern low inductance soft switching types.

Driver is ADP3120AJRZ, with no external gate resistors. I have the footprints in place in case I want to slow it down to reduce peaking, but currently there has been no need to, because the peaking is in control with the diodes and the RC snubbers.

Switching time, as seen from the SW node, with RC snubbers and the discussed diodes in place, seems to be 6-7 ns for both rising and falling (see attachment. Cyan trace is AC coupled Vin to approximate the possibility and magnitude of EMI and interference to the control side. Probably not the best way to do it, but there it is.). Measurements are done with 10:1 passive Rigol probes, using a spring clip like direct connection to the ground plane.

[tatus1969]

that 7ns sounds reasonable, high side FET dissipation will be in the 0.5W region (ballpark estimate: 2*f*V*I*t_sw). Your design does not seem to be optimized to squeeze out all possible efficiency, because the chosen transistors have considerable conduction losses at 20A. My experience is that even a few ns more transition time help a lot in reducing ringing.

I see why you have done your layout like you did, but my concern remains, if it would not have been working better even without snubbers and diodes, if you had made it much more compact, eliminating stray indcutance as much as possible.

An EMI tip from my experience: make the switch node PCB area as small as possible, because this area acts as a capacitor emitting the high dV/dt transients as an E field. As you are switching as fast as possible here, and also take some ringing into account, you may run into EMI problems with that large switch node area.

[Siwastaja]

that 7ns sounds reasonable, high side FET dissipation will be in the 0.5W region (ballpark estimate: 2*f*V*I*t_sw). Your design does not seem to be optimized to squeeze out all possible efficiency, because the chosen transistors have considerable conduction losses at 20A. My experience is that even a few ns more transition time help a lot in reducing ringing.

I see why you have done your layout like you did, but my concern remains, if it would not have been working better even without snubbers and diodes, if you had made it much more compact, eliminating stray indcutance as much as possible.

An EMI tip from my experience: make the switch node PCB area as small as possible, because this area acts as a capacitor emitting the high dV/dt transients as an E field. As you are switching as fast as possible here, and also take some ringing into account, you may run into EMI problems with that large switch node area.

Thanks!

Conduction losses at 20A would be (approximately):

Top: 1/3 * (20A)^2 * 8.65mOhm = 1.15W
Bottom: 2/3 * (20A)^2 *2.8mOhm = 0.75W

Good thing is, when highest currents are expected (in boost mode), the typical duty cycle tends to go to and below 1/4, balancing the conduction losses between the transistors.

I have no more ideas how to make the layout any more compact to eliminate stray inductance . Of course, I have the bottom leg inductance, but it's there on purpose and it (measurably) helps.

I have especially tried to place ceramic input caps as close to the transistors as possible, even cutting holes to the Vin plane to have the caps "inside" the plane.
The large caps in the screenshot are 0805, and the snubber components are 0603. The distance between the FETs is <2mm.

Yes, using the heat sinking plane on the switch node has always bothered me, it will naturally act as an antenna and capacitively couple to everything. Because I need the heatsink, and cannot come up with any simple solution, I simply decided to ignore this issue; as it's often done so on commercial devices, I thought it cannot be that bad .

Mostly, the big SW plane with a ground layer beneath acts as a D-S capacitance in parallel with the bottom FET. I was also thinking about cutting this mid ground layer locally, then only using the another mid layer to provide the ground; it would be further away, minimizing the additional D-S capacitance, but still shielding. But I decided to have the ground layer near the SW plane, for maximum shielding.

For now, I don't seem to have any problems whatsoever, which is very surprising! The digital, software-defined control side is also nice to work with. I'm considering upgrading to a bigger inductor, because I'm inductor copper loss limited right now at 18A; but the FETs keep cool enough to touch.

[T3sl4co1l]

I have especially tried to place ceramic input caps as close to the transistors as possible, even cutting holes to the Vin plane to have the caps "inside" the plane.
The large caps in the screenshot are 0805, and the snubber components are 0603. The distance between the FETs is <2mm.

Aside from the GND side slot, I would guess the layout is around 5nH loop inductance.

Is that good enough?

We can apply the formulas I posted above and find out.

The switching impedance is:
(14V) / (20A) = 0.7 ohms

Coss is around 1nF (the inductance-weighted average is what matters here, which is not simply the arithmetic average of Coss from 0 to 14V; the representative figure is weighted towards low voltages, where more time is spent), which means Lstray needs to be on the order of:
Lstray = (0.7 ohms)^2 * (1nF) = 0.49nH

Which you'll have a hard time meeting, and I can guarantee, can never be met with the package inductance alone of those transistors (~2nH each, guessing??).

We can also apply another rule of thumb regarding:

Mostly, the big SW plane with a ground layer beneath acts as a D-S capacitance in parallel with the bottom FET.

It doesn't, and the reason is obvious: Coss is on the order of ~nF, while the pour is of the order ~10pF.  Alternately, the transmission line impedance of that pour won't be nearly low enough: some ohms perhaps, but certainly not less than 0.7 ohms.

For it to look capacitive, it must be strictly below 0.7 ohms, so this is something we can determine with great confidence!

Although you didn't provide exact dimensions of the source trace, it looks roughly like 3 x 12 mm (counting length from the pin/pad).  You didn't mention the stackup, but if the top prepreg is 10 mils (0.25 mm) (typical for a 1.6mm overall thickness, 4 layer proto fab?), that would be Z ~= 13 ohms characteristic impedance (see http://www.chemandy.com/calculators/coplanar-waveguide-with-ground-calculator.htm ).  With a 12mm length, we should expect an inductance of about:
L = l * mu_0 * Z / (Z_0 / sqrt(e_r))
= (12mm) * (1.257 nH/mm) * (13 ohm) / (377 ohm / sqrt(3.6))
= 1 nH

Which isn't very much, but is still quite a lot more than threshold for having it "minimized", in traditional terms.



So what can you do?

If you can't reduce L, you can increase C.

If Lstray is about 5nH, you need:
C = L / Zsw^2 = 10nF

Add 10nF (C0G) in parallel with each transistor, as close as possible.  Probably divide in half (use pairs of 4.7nF), so each one can flank the transistors.  You can't make a low inductance capacitor (an SMT chip is about 1nH, period), but you can put in more of them, at least where you have any room to place them at all...

But won't that increase switching losses?

Certainly.  How much?

The energy is E = 0.5 * (10nF) * (14V)^2 = 0.98uJ.  At 150kHz, this is 0.147W.

So it's not very much at all, in fact.  You could afford even more, up to maybe 40nF, before efficiency starts dropping grossly; the main benefit would be reduced voltage overshoot.

And indeed, this is a sign that your circuit, as shown, is very poorly matched.  When Zsw = Zo, the losses due to magnetic (current commutation) and electric (voltage commutation) transitions will be equal.


The switching time constant pi*sqrt(L*C)/2 will then be 11ns, which is plenty fast.  There's nothing wrong with pushing the transistors faster than this, but you need to handle the reactive energy induced by fast edges.  Otherwise it will exhibit spikes and/or ringing.  And with inductances this small, you stand little chance of snubbing it away -- the diodes will only have more ESL!

In any case, getting Zo down is a top priority, otherwise the dominant inductance will make big tall spikes all over.

BTW, about time scales:

The ~40ns deadtime the ADP3120 provides is a huge margin.  Consider the time scale this circuit operates at: 11ns for the switching loop, ~30ns for the gate driver (transition time into 3nF, though the drain waveforms will be sharper than this).

It takes a minimum time of:
dt = L dI / V
= (5nH) * (20A) / (14V)
= 7ns
to fully commutate the load current from +V to GND, and vice versa.  (The time constant, 11ns, is longer due to capacitances charging and discharging.)

Indeed, if you had a driver with 0 +/- 7ns of shoot-through, you could achieve perfectly overlapping switching waveforms, preventing any diode forward-bias (and removing any reason for schottky diodes).

More than 7ns of overlap might be undesirable, because your shoot-through current would become greater than your load current.  This isn't automatically bad, though: with controlled timing, you could set it so overlap occurs instead of (uncontrolled) hard switching.  Thus getting turn-off ZVS for both switches, even though their currents are asymmetrical (one sourcing, one sinking)!

For a generalized synchronous buck (i.e., one that allows negative current, i.e. boost operation), the timing needs to be adjusted, but for a unidirectional application (as with most supplies), a fixed setting could be used.

Yes, using the heat sinking plane on the switch node has always bothered me, it will naturally act as an antenna and capacitively couple to everything. Because I need the heatsink, and cannot come up with any simple solution, I simply decided to ignore this issue; as it's often done so on commercial devices, I thought it cannot be that bad .

BTW, this can be helped somewhat by placing pours on the inner layers as heat spreaders, with ground pour on the outer layers to act as shields (and more heat spreading).

If thermal performance is that critical anyway, you'll need a heatsink (and thermal pads), which means opportunity to apply grounding and shielding, so it's not that bad.

Tim

[tatus1969]

that 7ns sounds reasonable, high side FET dissipation will be in the 0.5W region (ballpark estimate: 2*f*V*I*t_sw). Your design does not seem to be optimized to squeeze out all possible efficiency, because the chosen transistors have considerable conduction losses at 20A. My experience is that even a few ns more transition time help a lot in reducing ringing.

I see why you have done your layout like you did, but my concern remains, if it would not have been working better even without snubbers and diodes, if you had made it much more compact, eliminating stray indcutance as much as possible.

An EMI tip from my experience: make the switch node PCB area as small as possible, because this area acts as a capacitor emitting the high dV/dt transients as an E field. As you are switching as fast as possible here, and also take some ringing into account, you may run into EMI problems with that large switch node area.

Thanks!

Conduction losses at 20A would be (approximately):

Top: 1/3 * (20A)^2 * 8.65mOhm = 1.15W
Bottom: 2/3 * (20A)^2 *2.8mOhm = 0.75W

Good thing is, when highest currents are expected (in boost mode), the typical duty cycle tends to go to and below 1/4, balancing the conduction losses between the transistors.

I have no more ideas how to make the layout any more compact to eliminate stray inductance . Of course, I have the bottom leg inductance, but it's there on purpose and it (measurably) helps.

I have especially tried to place ceramic input caps as close to the transistors as possible, even cutting holes to the Vin plane to have the caps "inside" the plane.
The large caps in the screenshot are 0805, and the snubber components are 0603. The distance between the FETs is <2mm.

Yes, using the heat sinking plane on the switch node has always bothered me, it will naturally act as an antenna and capacitively couple to everything. Because I need the heatsink, and cannot come up with any simple solution, I simply decided to ignore this issue; as it's often done so on commercial devices, I thought it cannot be that bad .

Mostly, the big SW plane with a ground layer beneath acts as a D-S capacitance in parallel with the bottom FET. I was also thinking about cutting this mid ground layer locally, then only using the another mid layer to provide the ground; it would be further away, minimizing the additional D-S capacitance, but still shielding. But I decided to have the ground layer near the SW plane, for maximum shielding.

For now, I don't seem to have any problems whatsoever, which is very surprising! The digital, software-defined control side is also nice to work with. I'm considering upgrading to a bigger inductor, because I'm inductor copper loss limited right now at 18A; but the FETs keep cool enough to touch.

My thought regarding making it more compact was to skip the common source inductance approach and try to make it compact and "stiff" enough so that you can live with the diode's reverse recovery induced current spike, and to limit its capability to turn this into an unwanted voltage spike at SW and/or Vbus. As your design is already double sided, how about placing both FETs back to back at the same position. You could collect all supply capacitance at the one end, and the inductor at the other. Snubber aside the two.

For bulk capacitance, I suggest to use the largest available value in your desired package (0603?), use capacitors with at least doubled voltage rating (X7R / X5R nonlinearity when going too close to its rated voltage). Don't mix small and large capacitance values, like 100nF + 10uF, as this adds a parasitic pole (resonance between the 100nF and ESL of the 10uF cap).

You say that you will run your circuit in two quadrants. In the (reverse?) boost direction you run into the problem that current through the inductor is reversed. This creates possible problems:
- the low side is now switching  "at voltage",  generating switching losses on top of its conduction losses
- you will have ringing below GND, do you have measurements?
- the diode reverse recovery problem jumps over to the high side switch

Regarding inductor choice: a good start is double overrating. The thermal figures mostly only account for conduction losses, depending on operating frequency you need to add a similar figure for magnetization losses. Maybe testing different series from a selection of manufacturers. High frequency capability in the datasheet is also a hint. I have good experience with Vishay IHLP series.

If a few bucks don't count in this hobby project, you could choose beafier MOSFETs, available parts for similar package / voltage combo go down into the micro-ohms range. For example PSMN1R2-25YLD, that is around 1mOhm. (It has also double recovery charge though...)

This would allow for a bigger margin for switching losses, you could maybe afford 1.5 watts, allowing you to increase switching time by a factor 3. That reduces dI/dt and the residual ringing could probably be caught by a snubber only.

Maybe transistors with integrated shottky diode are an option, but I have not used them yet and don't know if they are really effective against reverse recovery ringing.

You said that your transistors died in the past. I am still convinced that D-S overvoltage from ringing cannot be the cause. Possibly gate breakthrough, maybe add zener diodes parallel to the gate, close to the transistors.

I also checked the H bridge driver, and have some thoughts about it:
- they specify -10V absolute maximum negative ringing for the SW node. Not sure what happens beyond that. Is it possible that you exceeded this during boost mode?
- how do you drive the /OD pin when the supply voltage is decreasing? The chip has UVLO of  3.7V, which is too low for the MOSFETs. Does the PWM generator still work at this voltage? Can you have the situation /OD=high and IN=low (static, no PWM)? If yes, then the low side transistor will be permanently enabled. This creates an LC circuit that will oscillate around GND, possibly destroying all connected circuitry (!)

[Siwastaja]

Thanks for the analysis and comments! As you can see, even when having success designing a working circuit, my analysis skills are clearly still lacking, and as many other designers, I still design somewhat by trial and error when it comes to power layouts. I did run spice analysis beforehand to compare what happens when I place 2nH of parasitic inductances in different legs, and to some degree, tried to simulate parasitic capacitances from the ground plane. I also simulated the diodes, and they did have similar effect in simulation as they did in real world. In simulation, they also go in conduction (not only acting as capacitance).

Although you didn't provide exact dimensions of the source trace, it looks roughly like 3 x 12 mm (counting length from the pin/pad).  You didn't mention the stackup, but if the top prepreg is 10 mils (0.25 mm) (typical for a 1.6mm overall thickness, 4 layer proto fab?)

Well guessed .

Add 10nF (C0G) in parallel with each transistor, as close as possible.  Probably divide in half (use pairs of 4.7nF), so each one can flank the transistors.  You can't make a low inductance capacitor (an SMT chip is about 1nH, period), but you can put in more of them, at least where you have any room to place them at all...

I do have 4.7nF of capacitance there right now - but as the RC snubber. R is around 1 ohm. I was thinking that damping the resulting LC circuit with R would be a good idea, forming a traditional RC snubber. The snubber is as close as humanly possible, as you can see from the layout, but I can see that the resistor inevitably adds another 1nH or even more to the 1nH coming from the capacitor already.

The energy is E = 0.5 * (10nF) * (14V)^2 = 0.98uJ.  At 150kHz, this is 0.147W.

Currently I'm losing half of that in the RC snubber. It's not an efficiency issue. If I had to go to 22nF range and above, it would start hurting. But with 4.7nF RC snubber, the SW overshoot is kept below 20% which I consider good enough.

And indeed, this is a sign that your circuit, as shown, is very poorly matched.  When Zsw = Zo, the losses due to magnetic (current commutation) and electric (voltage commutation) transitions will be equal.

Am I reading you correctly that the way to "match" the circuit is to increase the capacitance from what I'm having from FET Coss alone, because reducing inductance any more is not practical? When the capacitance and inductance are in match, Zo is minimized.

Does the RC snubber serve some kind of double purpose here, acting to make the layout less inductive by adding capacitance, and also providing damping by using R?

The ~40ns deadtime the ADP3120 provides is a huge margin.

This is indeed more than enough, and unoptimally long. I still opted to use an integrated driver with deadtime generation. Maybe if I were more ambitious, I could have found and considered using a bootstrap driver without any kind of deadtime logic and crossconduction prevention; it's just I've never seen those. I went for the easy solution.

Driving the output stage with adjustable deadtime, or even on-purpose cross-conduction, would have really been easy from the control viewpoint (STM32F334).

It takes a minimum time of:
dt = L dI / V
= (5nH) * (20A) / (14V)
= 7ns
to fully commutate the load current from +V to GND, and vice versa.

This happens to be quite well in line with my measured switching time of 7ns  .

My thought regarding making it more compact was to skip the common source inductance approach and try to make it compact and "stiff" enough so that you can live with the diode's reverse recovery induced current spike, and to limit its capability to turn this into an unwanted voltage spike at SW and/or Vbus. As your design is already double sided, how about placing both FETs back to back at the same position. You could collect all supply capacitance at the one end, and the inductor at the other. Snubber aside the two.

This double sided solution would seem to have similar inductance to what I'm having now - going to the opposite side adds 1.55mm automatically, which is practically the same as the distance between the FETs currently.

I have tough about all kind of gimmicks. One crazyish idea I came with was that idea of FETs on the opposite sides, with ground plane and Vin plane on opposite sides as well, then placing 0603 ceramics in the holes, soldering the ends to the planes. This could be risky because the ceramic could crack, but this would reduce the extra inductance of going through a via first.

For bulk capacitance, I suggest to use the largest available value in your desired package (0603?), use capacitors with at least doubled voltage rating (X7R / X5R nonlinearity when going too close to its rated voltage). Don't mix small and large capacitance values, like 100nF + 10uF, as this adds a parasitic pole (resonance between the 100nF and ESL of the 10uF cap).

I'm using 4.7uF 25V Samsung X5R (X5R was chosen because of price, availability and because this will be actively fan cooled and used in lab environment) in 0805. I placed in two 100nF caps nearest to the FETs because this seems to be the general advice, and I even included this in my spice simulation (adding a smaller cap with less parasitic inductance), and it did help in simulation. Removing these 100n caps would be a good test; if they serve no purpose or are detrimental, they should be removed .

You say that you will run your circuit in two quadrants. In the (reverse?) boost direction you run into the problem that current through the inductor is reversed. This creates possible problems:
- the low side is now switching  "at voltage",  generating switching losses on top of its conduction losses
- you will have ringing below GND, do you have measurements?
- the diode reverse recovery problem jumps over to the high side switch

I don't have too many measurements of the boost operation right now! I have tested it up to 18A boost, and scoped it up to 10A, but didn't save the images . This is what you get when you test it in the middle of the night, and say: no problems in sight! There still might be some lurking.

Regarding inductor choice: a good start is double overrating. The thermal figures mostly only account for conduction losses, depending on operating frequency you need to add a similar figure for magnetization losses. Maybe testing different series from a selection of manufacturers. High frequency capability in the datasheet is also a hint. I have good experience with Vishay IHLP series.

Yes, the total lack of core loss specifications is bugging me; I also can't use super expensive inductors. About $3 is maximum. I went with SRP1265A-3R3M for prototypes ($1 price is great), DC loss specified to 18A, but with fan cooling in room temp environment, I'm getting 17A out of it without problems even AC losses included. Anyways, I'm considering upgrading to Vishay IHLP6767GZER3R3M01, DC loss specified to 28A, as the inductor is the weakest link right now, the FET planes are relatively cool to touch at 17A. This would allow me to go to about 22-23A, where the losses are rather well balanced; all the components used are starting to be limiting at the same time.

If a few bucks don't count in this hobby project, you could choose beafier MOSFETs, available parts for similar package / voltage combo go down into the micro-ohms range. For example PSMN1R2-25YLD, that is around 1mOhm. (It has also double recovery charge though...)

It's not a hobby project actually, and cost is somewhat important factor.

More importantly, lowering Rds(on) too much easily makes switching losses go up (also the PSMN**-YLD package you suggest has more parasitic induncance than the -MLC packaging option I'm using!).

You can already see the difference when you compare PSMN2R8-25MLC and PSMN9R0-25MLC; Qgtot is 16.3nC vs. 5.4nC; tr, tf are 25, 13 ns vs. 10, 6 ns.

Of course, if there was an imaginary PSMN7R5-25MLC part with it's static and dynamic properties linearly interpolated between PSMN2R8 and PSMN9R0, I'd be using it on the top side . Currently, on the top, there is a little bit more conduction loss than would be optimal, possibly. It's not limiting, however.

Indeed, using PSMN1R2 on the bottom and PSMN2R8 on the top, then reducing fsw to limit switching losses, then using a considerably bigger inductor, would allow me to increase the efficiency further from the current 94% to maybe 96%. Then again, much more losses are happening on wiring, fusing and connectors; 4mm banana lead connections used for outputs have 5mOhm of resistance, fuses create 3mOhm, inductor is 6.8mOhm (the replacement will be 3.9 mOhm) and so on. In this regard, combined FET Rds(on) 2/3*2.8mOhm+1/3*8.65mOhm = 4.7mOhm is well in line.

You said that your transistors died in the past. I am still convinced that D-S overvoltage from ringing cannot be the cause. Possibly gate breakthrough, maybe add zener diodes parallel to the gate, close to the transistors.

It's possible you are right; that earlier design did have the FET driver further away. Now the driver is on the top layer, as close as the FETs as possible. Earlier design also had more ringing and more overshoot, which could couple to gates, too. Removing this overshoot and ringing with RC snubber solved this anyway.

- they specify -10V absolute maximum negative ringing for the SW node. Not sure what happens beyond that. Is it possible that you exceeded this during boost mode?

I have seen negative spikes down to about -2.5V in my scope during boost, but have no records of this .

- how do you drive the /OD pin when the supply voltage is decreasing? The chip has UVLO of  3.7V, which is too low for the MOSFETs.

ADC converts Vin at 150 kHz continuously running; when it drops below 8V, an ADC-integrated watchdog quickly provides highest-priority ISR pre-empting any other ISR, this ISR overrides the PWM generation, asserts the FET driver for 7 to 14 microseconds to discharge the inductor in the right (decreasing) direction if the latest current measurement is over 14A, to make sure the small freewheeling diodes (the original reason for this topic ) can handle the pulse. Then the output disable pin is asserted. All of this takes little enough time so that the capacitors can supply it. The ISR even has time to print debug information to UART after the shutdown, using the Vin caps.

This continuous ADC with ADC watchdog functionality leading to safety_shutdown() ISR function was the first thing I implemented and tested, and I have only blown 1 FET during all the time doing lots of stupid things in both SW and HW side . It detects Vin<8V, Vin>14.5V, Vout>5V, ILpk < -26A, ILpk > +26A and works with less than a few microseconds of latency during any of these issues.

[T3sl4co1l]

I do have 4.7nF of capacitance there right now - but as the RC snubber. R is around 1 ohm. I was thinking that damping the resulting LC circuit with R would be a good idea, forming a traditional RC snubber. The snubber is as close as humanly possible, as you can see from the layout, but I can see that the resistor inevitably adds another 1nH or even more to the 1nH coming from the capacitor already.

Ah, yeah, and 1 ohm is a little high -- though enough to see the ringing well damped (a cycle or two), so your waveforms won't look like Christmas trees!  The main downside is an RC doesn't do much against spikes -- if, at the moment of switching, all the load current transfers to the resistor, you get V = (20A) * (1 ohm) = 20V peak.

The two will act in parallel to some extent, which helps.  Also helps with ESL, which will be several nH, probably more like 4nH total per RC.

Again, we can see the folly of trying to reduce inductance to the point where it doesn't matter.  Conventional advice was not created with modern switchers in mind!

The energy is E = 0.5 * (10nF) * (14V)^2 = 0.98uJ.  At 150kHz, this is 0.147W.

Currently I'm losing half of that in the RC snubber.

-- Literally -- since, when you charge a C through an R, they absorb equal amounts of energy.  The total energy absorbed is C*V^2!

Am I reading you correctly that the way to "match" the circuit is to increase the capacitance from what I'm having from FET Coss alone, because reducing inductance any more is not practical? When the capacitance and inductance are in match, Zo is minimized.

One way, yes.  And not to minimize Zo, but to bring it in line with Zsw (= Vpp / Ipk), give or take a suitable factor that depends on what you're doing.

This is the best reason why high current switchers don't use single stages.  PC motherboards use up to a dozen phase-interleaved converters, and have done this for some years!  It's the only way to crank a hundred amperes at about one volt.  A 10 milliohm equivalent load!  Doing it with comparable transition times (~10ns I would suppose; I haven't actually measured one), such a design would be asking for a loop inductance of 1.2nH.  While also needing enough copper to handle the current!

With 20A in a single channel, and the same voltage range (i.e., around a 12V input), you're also pushing the limits of reasonable layout.  You really should consider a two phase controller design.

Dunno if you have enough speed in that STM32F4 to pull off two phases, though.  If you're not doing anything too weird with the output characteristics, you should be able to drop in a controller and tweak that for your programmable output.

(Doing the controls in SW is impressive, but the magnitude of output doesn't really matter for a proof of concept.  It could be a 3.3V 50mA design that powers itself, for all that matters! )

Does the RC snubber serve some kind of double purpose here, acting to make the layout less inductive by adding capacitance, and also providing damping by using R?

Yes.  It's the least efficient way to do so, but if that's acceptable (which as you noted, is!), then it helps.  I'd just reduce R slightly, or maybe the parallel combination is doing its job already.

My thought regarding making it more compact was to skip the common source inductance approach and try to make it compact and "stiff" enough so that you can live with the diode's reverse recovery induced current spike, and to limit its capability to turn this into an unwanted voltage spike at SW and/or Vbus.

Tatus,

As I've noted earlier, the design is already at the limit.  A conventional "stiff" design is not possible, within the constraints of reasonably-sized transistors, enough copper [trace/pour] to handle the current, and cheap PCB tolerances.

Rather than trying to fight an unwinnable battle, that's not even for a good cause in the first place (suppose what the origin might be, of "minimize inductance"), construct a (slightly meta) argument against it: why is it impossible?

I think it would be just possible, using CSP FETs (possibly EPC GaN FETs, but*...), placed with near zero component clearance, making optimal use of layers (possibly going to 6 or 8 layers), and using as little trace clearance as possible (connecting to a solder-bump CSP will require better than cheap-proto-PCB tolerances).

*GaN chips are faster than they are smaller, so this doesn't actually help -- unless you actively make them worse by adding "too much" gate resistance.  (With the aim that they're still faster than Si, but not grossly so.)

But in any case, the effort is not worth it.  We're talking hundreds of dollars for the PCBs alone (in small quantity).

Splitting it into multiple channels is the best overall option, so that each channel can operate with a very reasonable switching impedance (over an ohm).  The second best option is optimizing the existing design (and, yes, the layout can still be optimized a little, there's no such thing as an ideal layout), loading it down with capacitors and dampening or clamping the reactive energy.

More importantly, lowering Rds(on) too much easily makes switching losses go up (also the PSMN**-YLD package you suggest has more parasitic induncance than the -MLC packaging option I'm using!).

This is another common folly, that comes from a lack of analysis, merely repeating rules of thumb.  Indeed, the extra Qg will slow it down (as I noted above, the design is currently somewhere between loop-inductance-limited and gate-driver-limited, in terms of switching speed limits), and increase losses.

There is indeed such a thing as too low Rds(on)!  Let that sink in for a moment!

You said that your transistors died in the past. I am still convinced that D-S overvoltage from ringing cannot be the cause. Possibly gate breakthrough, maybe add zener diodes parallel to the gate, close to the transistors.

It's possible you are right; that earlier design did have the FET driver further away. Now the driver is on the top layer, as close as the FETs as possible. Earlier design also had more ringing and more overshoot, which could couple to gates, too. Removing this overshoot and ringing with RC snubber solved this anyway.

By the way, do you have Kelvin connections for the gate drives?  It's not obvious from the picture.

Tim

[Siwastaja]

Thanks for the comments!

So this is a multichannel li-ion cell charger/discharger. The previous revision was up to 27A per channel, single phase, with fsw=70kHz, and the layout was worse than it is now; so we can see it was really at the limit as you describe. RC snubbers fixed it, but it was a percentage point or two of efficiency loss, many times more than I have now. It was kind of a nice design because I used analog self-oscillating hysteresis control, kind of a combination of valley and peak mode cycle-by-cycle limit done with two comparators and some fast logic gates to give the bridge the right state. Super slow MCU DAC generated those two comparator reference levels.

This new software-defined revision is "only" up to 20A per channel, with fsw=150kHz, and yes, it's actually interleaved four-phase in a sense. The channels are separately controlled, however, because they may be connected to different cells; so one channel may buck while one boosts, and sometimes some of the channels are off. But when they all are running, they are interleaved with 90degree phase shifts. One STM32F334 controls two channels, providing 180 phase shift between the channels, and another two-channel copy is synced to the first with 90 degree shift. But for many purposes, the user actually parallels the outputs for higher current output, in which case a single unit becomes a four-phase interleaved converter capable of 80A!

And of course, luckily, bucking 12V down to 3-4V 20A is way easier than bucking 12V down to 1V 100A like on a motherboard :-).

I couldn't be more happy on my choice to go digital. The STM32F334 has been keeping up well, I'm employing peak mode (valley mode in boost) cycle-by-cycle limiting. The ADC shares the comparator input pin; in the control ISR, I average eight ADC current samples per period, calculate the error, and finetune (using a PI loop) the current mode controller setpoint by applying the new setpoint to the DAC, which can output a new reference level for the comparator in a few us. This gives me a single-cycle transient response time to small changes, and a few cycles for larger changes for the inductor DC level to catch up while outputting near 100% or 0% duty; while producing accurate current by finetuning out the uncertainty in the offset between average and peak (or valley) current out using a PI loop which can remove the remaining <5% error in a dozen cycles.

Everything works, but it seems I have a lot more homework to do to really understand what's exactly happening in my power stage, why, and how I can further optimize it. Clearly, I also need more measurements to either prove or disprove that the diodes are doing anything else than acting as capacitances. Since the diodes are not too cheap, replacing them with 0402 NP0 caps would be a good cost optimization.

Re gate drive connections: the switch node has a Kelvinish connection from the top fet source pad directly to the SW node of the FET driver, routed very closely to the gate signal. The trace length for both SW and topfet gate, including the gate resistor footprint, are about 3mm.

Bottom FET has this Common Source Inductance, so that's kind of opposite of Kelvin connection, made on purpose