high clock rate data logger with a slow uC

[Ferroto]

I've been thinking of making a data logger nothing too fancy.

One of the problems I quickly noticed is that a 4mhz or even a 20mhz uC wouldn't cut it if I wanted to analyze say the bus going between my cpu and the northbridge (FSB) so I said to myself how could I build a data logger with the ability to record at such high clock rates but not requireing expensive FPGA's


The solution I'm considering is to use an SRAM chip, a binary counter to cycle through addresses 0x00 and 0xff and an array of AND gates to detect when 0xff is being transmitted and stop the binary counter by holding the CLK line low (assuming it transmits the address byte when CLK is low otherwise invert the last AND gate) Then the uC then holds down the bin counter' CLR line essentially disabling it and then the AND gates switch off re-enabling the address bus except the SRAM is in read mode without the bin counter active, then the uC could read the information at it's own clock rate by feeding it the address lines and receiving what's stored on the datalines.

I also included the schematic as a PDF and the absense of a uC is because this is a hierarchy block but all the control lines are in the upper left.

[jahonen]

What is your target clock rate? Some observations based on the schematic:

Don't forget that ACT08 has a propagation delay of something like worst case up to 10 ns, typically 5 ns however. So it takes 40 ns worst case from address settling to asserting the halt signal. That will severely limit your maximum clock rate not much more that you can obtain with high clockrate MCU.

Also since the 4020 is a ripple counter, it takes quite a while for the clock edge to propagate through the outputs. That will also reduce the max clock rate.

Why not use for example a synchronous FIFO for the capture memory, it makes your job much easier?

Regards,
Janne

[Simon]

you really need to understand what your dealing with here a uC is no match for the 0.1-1.6 GHz signals of todays FSB's

[EEVblog]

Aren't FSB's on modern computers like close to the GHz region? Is this what you are talking about?
Any way you look at it what you really need here is high end logic analyzer. Not to mention the probing which is serious business at those clock rates.
I hate to say it, but if you are asking this sort of question on a forum then your chances of getting something DIY working at these sorts of clock rates is going to be next to impossible.

BTW, the term "data logger" usually implies a fairly low sample rate system.

Dave.