High-Speed PCB layout challenges - Learning the dark art the hard way.

[Gribo]

What sort of inductors do you use?

[rx8pilot]

What sort of inductors do you use?

I chose Murata LQW and LQG series inductors.
https://www.digikey.com/product-detail/en/murata-electronics-north-america/LQW18AN4N7C80D/490-14722-1-ND/6606328
https://www.digikey.com/product-detail/en/murata-electronics-north-america/LQG18HN2N7S00D/490-1103-1-ND/584549

I was not entirely confident in the component choices since I had very little information about what is most important or what parameters need to be balanced in this application.

[rx8pilot]

I have finally returned to this project!

Arrrg, you are driving the +&- balanced output to 2 different track lengths... 

Thinking about this - there is no requirement for each output to be loaded at all and should not impact the adjacent 75 ohm output. Trying to get an answer from Gennum on this one.

One of the biggest unknowns for me was how the probe loading may be impacting the circuit. Keysight offered to let me demo an N2752A probe to do some probe loading experiments. This was huge as I did not want to spend the nearly $6k on a probe just to understand the loading. It seemed possible that the impedance mismatch and resulting reflections could have been introduced by the probe. Huge thanks to Keysight for helping in that regard!

As it turned out - the probe loading was measurable - but insignificant. A very happy moment to better understand that variable. Double probing the test point lowered the amplitude slightly (as expected), but had no meaningful impact on the ringing/reflections.

What I did today was to measure the input and output of each stage - the receiver, the re-clocker, and the line driver. They ALL have really pronounced reflections even though they are all unrelated. For example, the output return loss network has no impact on the 100-ohm differential pair between the receiver and the re-clocker or the re-clocker and the line driver. Yet, they are all a mess and look similar. Good enough to be received and decoded, but still not very good. That leads me to believe that I may need to consider the PCB may be the weakest link OR the calculators I have used are totally wrong.

The PCB's come from PCBway which most of you know is the bottom of the barrel in terms of quality. They do offer controlled impedance, but the prototypes would jump from $125 to about $650. I am willing to spend the money on a properly fabbed impedance controlled PCB - but would be disappointed if it made little to no difference. PCBway ensured me the published stack up is what I got, but I have no way to test that. I do not have a TDR or VNA rig to measure the PCB in any way. I can only cross my fingers. With that in mind - maybe it is a good idea to have the fab house verify the impedance, add in some test coupons, etc.

As a side note, I eventually need at least one more 6Ghz probe to work out timing between two separate signals.

[Rerouter]

Your boards are tiny, why is it costing you $150 via pcbway? It looks to me like it should be costing you $150 via them for a batch of 10 with hard gold and impedance control, even for the higher spec FR4 substrate.

Do you have screens of the reflections, the direction and magnitude will let you calculate how far off they are, you should then be able to bodge a terminator of the right value with smd resistors to confirm.

[rx8pilot]

I got 5 panels that were 3x5 plus a stencil in hopes that they would be ok and I could run 50 of them through the P&P line. 5 panels is about $170 (75 pcs), $20 for the stencil, plus shipping.

I would love to better understand how to look at the end result and estimate how far off it is. These are .4mm QFN's which make it hard to bodge in a termination test - but I think I could do it. I have a full kit of 1% 0402 resistors ready.

Image 1: 100 ohm differential output of the re-clocker measured at the pins of the QFN.

Image 2: 75 Ohm single ended terminated on the PCB at the BNC mount.

[rx8pilot]

Ok - another update:

I pulled the line driver QFN off the PCB and used 0402 resistors to terminate the 100 Ohm differential line going into it. I measured it open, and 200 Ohms. Other than the amplitude changing, the ringing is the same. That kind of rules out an impedance mismatch?

Stumped.

[Araho]

Maybe your layout needs more work? No clue about this, I just find it really interesting and want to design some HD-SDI-stuff myself in the near future Are you having any vias in one of the tracks in the diffpair that aren't there in the other, or something?

[AndyC_772]

What does the power supply to the driver IC look like?

Is it possible that the driver IC is actually just not very good in terms of SI? Have you seen the exact same IC work better on another layout?

[rx8pilot]

There is little question that this layout would pass detailed scrutiny by someone truly skilled in the art of high-speed design. I have done 3 iterations so far - each one making significant changes - but the end results appear similar. It feels like the design details I am studying and changing are not the dominant source of ringing / reflections.

The power supply is a 3v3 switcher that seems to be performing quite well. Very low ripple and very low noise. The chips are bypassed with 100nf and 10nf caps at each Vcc pin. The reclocker uses its own 1v8 LDO.

All signals are on the top layer so  I did not introduce any vias to my long list of design variables.

The original layout was all LDO power, but again, similar results. I am just not sure what to consider next.



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[Rerouter]

I sat down and had a go meddling with your design in Kicad (What i prefer), and my best guess for most of your issues is unintentional ground inductance on the supply capacitors, a number of them dont have a direct run between the negative of a supply and the ground of the cap for that rail, many passing through 2 vias to reconnect.

The zip file is the entire kicad project, if you want to play with it. I just started from scratch using what made sense to me, then went back and thought about why there where differences.

The references are the same as your original one,

In this case I places the ground vias where i could to create the least inductive circuit for each part of it.

The Traces for the signal path are 0.3mm wide, spaced by 0.4, which was the best happy middleground i could come up with, as being less sensitive to the height, while meeting as close to the specs as i could (ideally 100 ohms differential, about 55 ohms to ground, but the top layer ground pour should nudge it closer to 50.4) qnd all distances put it at under 1/10th of a wavelength, but i figured you would be wanting to match your original grouping, so planned out what the impedance likely needs to be.

I could actually see this being done on a 2 layer (0.2 or 0.3mm thick board), as the supply rails are quite easy to route around the signal path, and all your programming connections end up on the same side of the signal path. 

[rx8pilot]

Wow! That is an extraordinary effort to help! Thank you very much for the time.

The ground vias should be rather low inductance as they connect to a solid ground plane on layer 2, 9mils below the top layer. Attached is layer 1 (signal and GND fill), layer 2 (GND), layer 3 power 3v3 and 1v8, layer 3 GND and Programming Header. It is entirelty possible that a power integrity issue is the main contributor. I will take a close, mV level, look at the power rails at various points around the board.

For the brief moment that I have the Keysight probe on loan - I should do some timing comparisons to see if the ringing is time correlated at different stages of the signal.

[rx8pilot]

After a look at the power rails so far. Measured the 3v3 rail at the Vcc pin of the receiver chip GS6042 - across the bypass cap. The same with the 1v8 rail at the Re-Clocker chip GS6151. Both of them look very clean at full bandwidth with the differential probe - 5mV/div. No switching noise to speak of. I also ran an FFT on the rails and swept from 0 - 7Ghz and the noise is pretty flat - no noticeable spikes. If anyone thinks I should look at other power issues - I am all ears for sure. From what I see, the 3 chips in the design are being fed a steady diet of voltage. I could not see any evidence of too much inductance.

I also did a quick test to look at the signal chain at the beginning and the end. The yellow trace is the differential receiver output and the blue trace is the line driver differential input (temporarily terminated at 200 Ohms with resistors, chip removed). The ringing is nearly identical at both positions with one being properly terminated at 100 Ohms and the other improperly terminated at 200 Ohms. I did not expect that. My guess is that the 200 Ohm trace would look totally different.  If the termination being changed wildly does not impact the characteristics of the ringing - maybe I should not be looking for an impedance mismatch problem at all.

[rx8pilot]

Maybe your layout needs more work? No clue about this, I just find it really interesting and want to design some HD-SDI-stuff myself in the near future Are you having any vias in one of the tracks in the diffpair that aren't there in the other, or something?

Gennum (Semtech) is one of the top manufacturers of HD-SDI receivers, re-clockers, line drivers, and more. TI and Macom are also well established and good at what they do. There are countless successful use cases, so I am going to keep the blame machine aimed at me (the newcomer to highs-speed design). The level of detail is mind blowing and the test equipment and skills are not trivial.

[nctnico]

I'm wondering. The ringing is close to the maximum bandwidth of the oscilloscope. Can this be some issue with interpolation? Does the signal change when the scope is set to equavalent time sampling? Did you try to look at the signal with a spectrum analyser to see if you can see a spike at the frequency you get the ringing?

[Leo Bodnar]

rx8pilot,
I have noticed you are using power–IC–decoupling routing rather than power–decoupling–IC.
Not sure how critical this is for the design.
Have you played with decoupling capacitors choice?
They have amazingly low self-resonance. Low as in tens of MHz for a typical 100nF.
Leo

[Someone]

I have noticed you are using power–IC–decoupling routing rather than power–decoupling–IC.
Not sure how critical this is for the design.

Oddly U2 has the capacitors after the via and before the pins, but not the other two chips. Could be worth capturing the correlated ripple at the bypass caps on each of the different chips to see if there is any measurable difference.

[T3sl4co1l]

FYI, SRF is not an indicator of bypass capacitor performance.

Total PDN impedance is.

Tim

[rx8pilot]

I'm wondering. The ringing is close to the maximum bandwidth of the oscilloscope. Can this be some issue with interpolation? Does the signal change when the scope is set to equavalent time sampling? Did you try to look at the signal with a spectrum analyser to see if you can see a spike at the frequency you get the ringing?

I did look at the impact of using ET - no change.  I also did an FFT (I do not have an SA) and see a lump around 5Ghz - but all the fast edges mask the ringing tone so not much to see there (unless I am missing something). The test equipment and my own technique has not yet been ruled out. When Keysight offered to loan me a probe, that was a fantastic opportunity to eliminate the hypothesis that the probe may be introducing some inductance that would make the ringing or at least exacerbate it.

rx8pilot,
I have noticed you are using power–IC–decoupling routing rather than power–decoupling–IC.
Not sure how critical this is for the design.
Have you played with decoupling capacitors choice?
They have amazingly low self-resonance. Low as in tens of MHz for a typical 100nF.
Leo

I have not yet fiddled with decoupling caps, but it is an easy experiment just to see if it makes a measurable change. Maybe piggy back some small values - 2700p to 1nf to see what I see?


Another note - I got a response from the Semtech Application Engineer. He requested all the data - schematic, gerbers, etc. so I am hopeful that he will discover a smoking gun (hope he goes easy on the newbie, lol).

[Rerouter]

Keep us posted, would be nice to have an RF engineers insight,

[rx8pilot]

I have noticed you are using power–IC–decoupling routing rather than power–decoupling–IC.
Not sure how critical this is for the design.

Oddly U2 has the capacitors after the via and before the pins, but not the other two chips. Could be worth capturing the correlated ripple at the bypass caps on each of the different chips to see if there is any measurable difference.

I just realized that - not sure what I was thinking or why I would do that. U2 is the 1v8 part powered by the LDO.

FYI, SRF is not an indicator of bypass capacitor performance.

Total PDN impedance is.

Tim

I believe the PDN impedance to be reasonably low. The measurements I took around the PCB appear to be very clean while signals are passing through.

Keep us posted, would be nice to have an RF engineers insight,

Yes, it will be nice to have an RF engineers insight indeed.

[BrianHG]

After a look at the power rails so far. Measured the 3v3 rail at the Vcc pin of the receiver chip GS6042 - across the bypass cap. The same with the 1v8 rail at the Re-Clocker chip GS6151. Both of them look very clean at full bandwidth with the differential probe - 5mV/div. No switching noise to speak of. I also ran an FFT on the rails and swept from 0 - 7Ghz and the noise is pretty flat - no noticeable spikes. If anyone thinks I should look at other power issues - I am all ears for sure. From what I see, the 3 chips in the design are being fed a steady diet of voltage. I could not see any evidence of too much inductance.

I also did a quick test to look at the signal chain at the beginning and the end. The yellow trace is the differential receiver output and the blue trace is the line driver differential input (temporarily terminated at 200 Ohms with resistors, chip removed). The ringing is nearly identical at both positions with one being properly terminated at 100 Ohms and the other improperly terminated at 200 Ohms. I did not expect that. My guess is that the 200 Ohm trace would look totally different.  If the termination being changed wildly does not impact the characteristics of the ringing - maybe I should not be looking for an impedance mismatch problem at all.

When looking at your power supply signals, try locking 1 channel of you scope on the output signal at each stage while viewing the VCC & GND of each IC on a second channel on your scope.  Looking at the phase and amplitude of the source signals in time VS the supply signals might help you narrow in on a worst location culprit section of your design before you go swapping every bypass cap and making a mess of the PCB.

I know power supply noise will have a fraction the amplitude of the output, and the noise wont be due to regulation issues, but you may sniff out a slightly weak location in you PCB layout.

[Leo Bodnar]

FYI, SRF is not an indicator of bypass capacitor performance.
Total PDN impedance is.
Tim

Sure, I was highlighting the fact that parasitics are higher than most people (including me) expect.
SRF is easier to evaluate in an average lab given a set of alternative parts.
Leo

[AndyC_772]

I'd also question the importance of the SRF of a particular component when it's used in a design. In any practical circuit, there's additional inductance added in series with each decoupling cap by virtue of the traces that connect to it, which tends to dominate the component's own self inductance anyway.

There's quite a lot of confusion and bad science out there when it comes to talking about how best to decouple high speed designs.

The object of the exercise is always to provide an IC with a power supply with as low an impedance as possible across a wide enough frequency range, from DC up to the highest frequency at which the circuit operates (which, of course, depends on the edge rate in terms of dV/dt, and not on the number of switching cycles per second).

So, for example, it's often suggested that you should use caps of different values, because each has a SRF, and therefore a minimum impedance, at different frequencies, but this isn't really a good recommendation.

It may be that, say, a 100n 0402 cap has a lower SRF than a physically similar 10n cap, and so its impedance stops falling with increasing frequency (capacitance-dominated) and begins to increase again (inductance-dominated) at a lower frequency point than the 10n cap.

But: if the self-inductance of both caps is about the same (which it will be if they're of similar physical size), and the capacitance of the 100n cap is larger, then its total impedance is still less than that of the 10n cap at all frequencies. Using the 10n cap, when you can get 100n in the same physical package size, is pointless.

Instead, for high speed designs, I'd recommend

- use the physically smallest decoupling caps that you can
- add the absolute least possible series inductance between each cap and the device it's supplying that you possibly can
- remember that the lowest inductance path between any two points is almost certainly through a plane, not through a trace

There's quite a good discussion on the subject here:
https://www.eevblog.com/forum/beginners/how-much-noise-on-power-rail-is-normal/

[T3sl4co1l]

Don't bother trying too hard, either: past a few hundred MHz, it's impossible to provide extremely low impedances on a PCB, even to a BGA package on a multilayer board.  Chip designers must provide for that themselves (differential drivers are a fantastic boon, here, even if you only need the one output).

Do avoid stacking caps of different values: you'll end up with a peak impedance that's worse than using just one or two.  The impedance peak may not be noticeable unless you test your circuit at different clock frequencies, with PRBS data, or fuzzing at least.  Or test the PDN with a network analyzer.

You can very easily throw more caps at a design, and think smugly to yourself that you've done well, but it's only superstition until you've tested and verified it.

Do use damping: a ceramic with external ESR, or a lossy bulk cap with internal ESR (most often tantalum, which have stable ESR, and can be selected from a wide range of C and ESR).  You want ESR to dominate PDN impedance, so that no resonance peaks out from it, and the impedance is nice and stable.

Tim

[rx8pilot]

With the discussion of decoupling caps - I thought I would do a quick experiment - Just take it off and see what impact it has.

On U1 (the receiver chip GS6042) - the differential output driver has a dedicated Vcc that I am running from the 1v8 LDO supply. I have a 10n 0402 X7R cap to decouple. There was little consideration here, I just used the value from the manufacturer app note.

So on these scope grabs, you can see two traces both of them are the differential output of the GS6042 chip U1. The Orange is a REFERENCE saved that I took with the decoupling cap. The Yellow is the capture with no decoupling cap at all. Identical. I guess the internal on-chip decoupling is the only thing really working at these edge rates. I was kind of expecting to see a rise-time extension or some other impact by having no bypass at all.

So - I am thinking that even if the choice or routing on the decoupling caps could be improved - there is clearly something else making the ringing. The party shall continue......



EDIT:
I attached another image to show the impact of probe loading. The ORANGE trace is a single probe on a termination point (taken originally with the YELLOW probe). The BLUE/YELLOW are on the same point at the same time. It is very difficult to probe these extremely tiny points with two differential probes - so the blue probe is actually on the yellow probe which partly accounts for it's apparent attenuation. Since my hands were full and this was happening under a microscope - the voice control on the Keysight is VERY VERY useful.

The result is that double probing attenuates as expected but does not have an appreciable impact on the ring frequency or the dampening.