Author Topic: High-Speed PCB layout challenges - Learning the dark art the hard way.  (Read 36175 times)

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Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #25 on: April 21, 2017, 02:08:18 am »
Something I probably should have done first.......

I shaved a PCB and measured the stack up. Not what I asked for  :--
The L1 to L2 dielectric thickness is 4.5mils and I was planning for 9mils. This takes the diff pair from 100 ohms to about 75 ohms. The coplanar ground fill makes that number even lower - perhaps 65 ohms? Anyway, I can add that to the top of the fix list and make sure I get a stackup guarantee on the next one. That is a nasty one, but not too surprising.

When I started my EE journey....I never would have guessed that the dielectric thickness being 4.5mils thinner would trash the intended function. It is, however, a lot of fun to slowly see how the magic happens.

In addition to the layout fixes so far, I think I will add ENIG finish which has far less thickness variation and hardly costs anything compared to tin plating.  I will take another stab at the BNC footprint after I get some guidance from Samtec.

Onwards - hope to go for spin 2 tomorrow if possible.
« Last Edit: April 21, 2017, 03:16:28 am by rx8pilot »
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Offline TiN

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #26 on: April 21, 2017, 04:24:05 am »
Is you input bandwidth 6gigs too? Maybe replace BNC with something more suitable, like SMA or N, which even cheap ones usually better up to 8gigs or so.
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Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #27 on: April 21, 2017, 04:53:24 am »
Is you input bandwidth 6gigs too? Maybe replace BNC with something more suitable, like SMA or N, which even cheap ones usually better up to 8gigs or so.

Yes - the input is 6Ghz. The signal is HD-SDI High Definition Serial Digital Interface and is defined by SMPTE along with the connector and its return loss limits. The BNC connector is the only option and the TV business does not seem to have anything different on the horizon. There is a smaller BNC called HDBNC for 'High Density'. That connector is higher performance but regarded as too fragile and not compatible with existing systems. They generally only see deployments in routers and similar fixed infrastructure installations. The BNC manufacturers are killing themselves to go out past 12Ghz with BNC to meet the newest 12gbps standards. Most of them are being tested out to 18Ghz which is really crazy for that type of connector.

The connectors I am using are Samtec 'True75' specifically designed for 12Ghz applications. Amazing.

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Offline TiN

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #28 on: April 21, 2017, 05:05:29 am »
I see, excuse me my arrogance, I had back thought it's SDI, but didn't ring the bell.
Here's stackup calculation results with specified and 4.5 mil prepreg thickness  :scared:.

I don't think that huge plane void would help you with anything at these speeds.
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Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #29 on: April 21, 2017, 05:24:19 am »
Yep, I am curious how much that mismatch would contribute to the observed ringing seen in the circuit the capacitor placement was likely significant contribution as well. It is not clear to me what tolerances I should be hoping to hold.
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Offline AndyC_772

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #30 on: April 21, 2017, 06:26:46 am »
There's a clue that I don't think has been fully exploited yet. You said the ringing period was the same on both transmission lines (188ps) even though they're different lengths? Surely that must mean that the ringing isn't due to an impedance mismatch, which would result in reflections propagating up and down the transmission line, which would vary depending on the length of the line.

How, and where, are you connecting your probe? Could this just be a probing artefact rather than an actual SI problem when the scope isn't there?

Offline Pitrsek

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #31 on: April 21, 2017, 06:52:19 am »
look into TDR, way cheaper than vna, and fo your use probably better suited. you cen tell where is your mismatch located(if you spend enogh money..). I mentioned vna because that is what i have acess to...
if you have rf sig  gen, you might be able to find a trace resonance with your scope and calculate the impedance. (lastl link from my post, but use gener to sweep the frequency, instead of vna)
Its usually possible to have your stuff measure at local uni. Or you can ask here:https://www.freelists.org/list/si-list , if there is somenoe with TDR in your vicinity.  actually this is also one of the places where to ask for help with this kind of stuff.

if you find out that your design is sensitive to track thickness, you can ask your pcb house to do panel plating, instead of pattern plating. with panel plating, panel is plated before etching, so the thiclness is better controlled.
if you have board estate aviable, going with wider trace helps - coupling from the bottom is more dominant compared with coupling from edges, so thickness variance effect is smaller. also there is smaller discontinuity when you connect to capacotor pads.
 

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #32 on: April 21, 2017, 12:10:58 pm »
I was looking at VNA's and thinking that I could get somewhere with an older 6Ghz model with various used eCal, cables, and fixtures. That would not be helpful for long before I needed a 20Ghz system to effectively design clean 12gbps IO. At those rates, the test equipment, calibration, fixtures, and skills are quite a  serious journey. The cost of everything skyrockets. The precision needed for success skyrockets.
Thats all interesting when you're trying to build accurate RF designs but the nature of serial communications is a little more adaptable. If you're ok with the incremental build and test approach you can start with something much cheaper to validate the final result:
https://www.omnitek.tv/ultra
and worry about finessing the internal details if and when needed, but either way you'll still end up needing a protocol analyser and source to test against.
 

Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #33 on: April 21, 2017, 05:34:40 pm »
There's a clue that I don't think has been fully exploited yet. You said the ringing period was the same on both transmission lines (188ps) even though they're different lengths? Surely that must mean that the ringing isn't due to an impedance mismatch, which would result in reflections propagating up and down the transmission line, which would vary depending on the length of the line.

How, and where, are you connecting your probe? Could this just be a probing artefact rather than an actual SI problem when the scope isn't there?

Totally - I have been wondering about that. I was measuring on the AC coupling caps since they are so easy to probe relative to the QFN's they terminate into. The only way to get the bandwidth out of the probe is to hand place it on the test points, the solder-in probe heads attenuate way too much. I will try to see if I can get the probe directly on the QFN pads. I would expect the period to change with the different lengths of the transmission line and presumably different impedances from the geometry differences - although I am a beginner in wave theory.
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Offline MagicSmoker

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #34 on: April 21, 2017, 05:45:55 pm »
My 2cents:
Get a copy of Johnson and Graham's High Speed Digital Design, A Handbook of Black Magic.  This is one book every engineer designing high speed logic should read cover to cover.

On the way.....$30 is a no brainer. Thanks.

Just chiming in to say this is hands down one of the best EE books I own. It has lots of practical tips on how to make good measurements in it as well. Really can't recommend it enough.

 

Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #35 on: April 21, 2017, 05:50:14 pm »

Just chiming in to say this is hands down one of the best EE books I own. It has lots of practical tips on how to make good measurements in it as well. Really can't recommend it enough.

Sweet!
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Offline AndyC_772

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #36 on: April 21, 2017, 08:48:54 pm »
Totally - I have been wondering about that. I was measuring on the AC coupling caps since they are so easy to probe relative to the QFN's they terminate into. The only way to get the bandwidth out of the probe is to hand place it on the test points, the solder-in probe heads attenuate way too much. I will try to see if I can get the probe directly on the QFN pads. I would expect the period to change with the different lengths of the transmission line and presumably different impedances from the geometry differences - although I am a beginner in wave theory.

It's definitely worth reading up on how waves propagate up and down transmission lines, and how different kinds of termination (series vs parallel) actually work. The very short version goes something like this.

Suppose you have:

- a driver with low output impedance (let's assume 0R for the sake of simplicity), and zero rise time.

- a long 50 Ohm transmission line, with no termination, and a high impedance receiver at the far end

- logic levels denoted by 0V for a logic 0, and 1V for a logic 1

- initial condition is that the entire transmission line is settled at 0V, and we consider what happens when there's a rising edge at the driver.

At t = 0, the voltage at the driver output instantly changes from 0V to 1V. The wave begins to propagate away from the driver toward the receiver, at a rate determined by the inductance and capacitance per unit length. Energy is stored in the inductance and capacitance of the transmission line, and while the wave front is propagating, current is drawn from the driver. It's a 50 Ohm line, which means the current being drawn is simply given by Ohm's law, so I = V / R = 1 / 50 = 20mA.

At any impedance discontinuity, part of the wave will pass through and the rest is reflected back. Conservation of energy is, of course, maintained.

The wave reaches the receiver, where the 50 Ohm transmission line ends, and the impedance of the receiver input is effectively infinite. This means the coefficient of reflection is 1, so all the energy is reflected back toward the driver. The voltage at the receiver becomes 2V, which may even damage the receiver. Current continues to be drawn from the driver. The receiver's input impedance may change, since it's now seeing an input voltage that well exceeds the usual logic '1' level.

The wave then reaches the driver, and this time it sees an impedance of 0R. This again means that 100% of the wave is reflected, but the sign also changes, and the negative going edge now propagates back towards the receiver. At the receiver, the voltage drops from 2V down to 0V. The wave reverses direction and continues to travel up and down the transmission line until it eventually dissipates, and the entire transmission line eventually settles at 1V.

This, clearly, isn't going to work, and it may even damage the receiver. Bad idea.

Now consider what happens if you put a 50 Ohm resistor across the receiver input.

At t = 0, the voltage at the driver jumps to 1V and the wave begins to propagate. When it reaches the receiver, the impedance it now sees is equal to the characteristic impedance of the transmission line, so the coefficient of reflection is 0. All the energy in the wave front is absorbed by the resistor and turned into heat, and the driver sources 20mA indefinitely. The voltage at the receiver transitions cleanly from 0V to 1V and all is well.

Note also that the voltage at every point on the transmission line switches cleanly from 0V to 1V. You can probe it anywhere and you'll see the same thing.

As an alternative, now imagine a 50 Ohm resistor placed in series with the driver, located close to the driver end of the transmission line, effectively making the driver's output impedance 50 Ohms. (Some high speed driver ICs include this resistor, and may allow a choice of values to match different transmission lines).

The voltage at the driver output, therefore, is divided down by the potential divider: 50 Ohms output impedance, and the transmission line itself looks like 50 Ohms to ground. So a 0.5V step propagates from driver toward receiver.

At the receiver, the incoming wave sees a high impedance, so as in the un-terminated case, it doubles in amplitude and reverses direction. The voltage at the receiver switches cleanly from 0V to 1V, which is good. The wave propagates back towards the driver, where it sees 50 Ohms, and 100% of the wave is absorbed and turned into heat in the series resistor.

In this case, current is only drawn from the driver while the wave is propagating. In the steady state (after 2 transit times - there, and back again), no current is drawn, as the receiver is high impedance. So, series termination means less dissipation in the driver. I generally tend to prefer series termination for this reason.

But: the waveform you see depends on where you probe. You only get a clean 0-1 transition at the receiver. Everywhere else, the signal goes from 0V to 0.5V, then from 0.5V to 1V a moment later. How long it sits at 0.5V depends on the distance from the receiver.

That's the ideal case. Real drivers have finite rise time, real transmission lines are lossy, and even the most expensive probes will distort the signal - so what you see on your scope may not bear much relation to what I've described.

Series termination tends to be the better choice for point-to-point connections, where one end is always the driver and one end is always the receiver. Parallel termination is preferred on bidirectional links, because you can simply put a resistor to GND next to each transceiver, and the line will be correctly terminated for both directions. Parallel termination (resistor to GND at both ends) is also better for multi-drop buses which may be driven from any point on the bus, and received at any other point.

It might be worth fabricating a PCB with a driver, receiver, a very long transmission line, and sites for series and parallel termination resistors. Drive a square wave, and probe at different places with different resistors fitted to see the effect.

Read up on time domain reflectometry (TDR); it works by detecting reflected signals, so any good description of how it works should cover impedance discontinuities and their effect on forward vs reflected waves.
 
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Offline MagicSmoker

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #37 on: April 21, 2017, 09:46:57 pm »
A 3rd option for termination that is especially good for single transmitter, multiple receiver buses is to split the termination resistance into two resistors of double the characteristic impedance, one to Vcc and the other to ground. The loading on the transmitter is half that of parallel termination but signal fidelity along the bus is preserved.
 
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Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #38 on: April 21, 2017, 09:52:34 pm »
Nice write-up @AndyC_772 - thanks!

I am slowly gaining ground on wave behavior. Your write up is exactly what is hard to find in general. A lot of the text and video sources of information dive right on into deep math models where I need to back up and get more of an overview first before getting tangled in the smaller details. I found a few old films that were helpful in setting the stage with physical demonstrations....some real gems.

https://youtu.be/j2gOh39IyPM
https://youtu.be/DovunOxlY1k
https://youtu.be/I9m2w4DgeVk

Now, I need to step it up and dig into the details and how the math describes and predicts the behavior.


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Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #39 on: April 22, 2017, 05:50:23 am »
There's a clue that I don't think has been fully exploited yet. You said the ringing period was the same on both transmission lines (188ps) even though they're different lengths? Surely that must mean that the ringing isn't due to an impedance mismatch, which would result in reflections propagating up and down the transmission line, which would vary depending on the length of the line.

How, and where, are you connecting your probe? Could this just be a probing artefact rather than an actual SI problem when the scope isn't there?

I just did a quick experiment and probed the launch point - the coupling caps - and the receiver. The TX and RX were probed directly on the QFN itself - an interesting challenge. I am now very thankful for the voice commands on the Keysight scope. When you are probing .4mm QFN directly under a microscope without a probe positioner - it's nice to tell the scope what to do. The probe is differential and has adjustable width probe pins. Keysight N2752A. I only have one and wishing I had a second to double probe the circuit and see if the probe is doing much damage as a sanity check.

Anyway - I learned that there is little visual difference and I need to actually get a better setup to capture the data and compare more accurately.
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Offline Dago

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #40 on: April 22, 2017, 11:36:55 am »
My 2cents:
Get a copy of Johnson and Graham's High Speed Digital Design, A Handbook of Black Magic.  This is one book every engineer designing high speed logic should read cover to cover.

On the way.....$30 is a no brainer. Thanks.

I can also give a strong recommendation for this book. Very very practical approach to things and real world problems and not just theoretical stuff.
Just chiming in to say this is hands down one of the best EE books I own. It has lots of practical tips on how to make good measurements in it as well. Really can't recommend it enough.
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Offline Someone

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #41 on: April 22, 2017, 12:08:50 pm »
How, and where, are you connecting your probe? Could this just be a probing artefact rather than an actual SI problem when the scope isn't there?
I only have one and wishing I had a second to double probe the circuit and see if the probe is doing much damage as a sanity check.
Simulation says the probing should have a small but measurable impact on the signal, which should be visible clearly in the frequency domain and cause quite different looking eye diagrams at each probing point. Did you have a consistent test signal?
 

Offline Kalvin

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #42 on: April 22, 2017, 12:23:50 pm »
Another very useful and practical book on fast digital signal design: "motorola mecl system design handbook", 4th edition. Lots of oscilloscope pictures pointing out the effects of the PCB design and transmission lines. The book goes very well together with the "High Speed Digital Design: A Handbook of Black Magic".
 

Offline tggzzz

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #43 on: April 22, 2017, 02:09:56 pm »
How, and where, are you connecting your probe? Could this just be a probing artefact rather than an actual SI problem when the scope isn't there?
I only have one and wishing I had a second to double probe the circuit and see if the probe is doing much damage as a sanity check.
Simulation says the probing should have a small but measurable impact on the signal, which should be visible clearly in the frequency domain and cause quite different looking eye diagrams at each probing point. Did you have a consistent test signal?

There's a simple standard technique to see how much a probe is affecting a signal. You add a second probe alongside the first probe, and see the change in the signal measured with the first probe.
There are lies, damned lies, statistics - and ADC/DAC specs.
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Offline Kalvin

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #44 on: April 22, 2017, 02:51:00 pm »
The FR4 is not optimal choice for the PCB at gigahertz frequencies and wide bandwidth. The pulses will be distorted due to the frequency dependent dispersion as the different frequency components of the signal travel at different speeds and are attenuated differently (See chapter Layout Miscellany, pg. 286):

https://books.google.fi/books?id=MLzPNpJQz9UC&pg=PA286&lpg=PA286

The author of the High Speed Digital Design: A Handbook of Black Magic explains different probes and probing techniques:

http://www.sigcon.com/Pubs/straight/probes.htm
« Last Edit: April 22, 2017, 02:59:12 pm by Kalvin »
 

Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #45 on: April 22, 2017, 07:07:04 pm »
How, and where, are you connecting your probe? Could this just be a probing artefact rather than an actual SI problem when the scope isn't there?
I only have one and wishing I had a second to double probe the circuit and see if the probe is doing much damage as a sanity check.
Simulation says the probing should have a small but measurable impact on the signal, which should be visible clearly in the frequency domain and cause quite different looking eye diagrams at each probing point. Did you have a consistent test signal?

There's a simple standard technique to see how much a probe is affecting a signal. You add a second probe alongside the first probe, and see the change in the signal measured with the first probe.
I only have one high-speed probe. They are stunningly expensive with a list price of $5800.

I agree FR4 is not the best choice but there is a long term interest in making the design workable in that material. The chip manufacturers have optimized the EQ for FR4 in an effort to keep the BOM cost low. Just about every manufacturer has figured out how to use it with reasonable results. If I move to a higher performance dielectric and also have the low-volume on all parts - I don't stand a chance at being competitive.

Goal #1 is to work out a solid i/o on FR4
Goal #2 use that general scheme to feed FPGA's reliably to process the data and send it back out.
Goal #3 Make all of these skills marketable so I can add them to my business.

With goal 3 in mind, I am conscious of learning how to keep costs managed.

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Offline John_ITIC

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #46 on: April 22, 2017, 07:58:52 pm »
Talk to Lee Ritchey at Speeding Edge, he's the guru for high speed PCB design and layout. Get onto one of his training courses if you can, they're brilliant.

http://speedingedge.com/

I doubt Carlos can afford to hire Lee Richey since he (Carlos) is a one-man shop. BUT I can strongly recommend buying the speeding edge books (on speedingedge.com), which discuss all you need to know with regards to PCB design for high-speed power and signal integrity as well as PCB physical design issues like choosing PCB materials, using plane fills to maximize power plane capacitance etc.

I have a few high speed designs under my belt (2.5 Gbps PCIe Analyzer and 5 Gbps USB 3.0 protocol analyzer) and high-speed trace routing is not very complex at all as long as one follows some simple rules of thumb:

1) Make sure to match trace impedance - reflections will occur at the point where the impedances matches, which causes "ringing" (which in reality are reflections that die out as the reflected energy dissipates after a few round-trips).

2) Make sure to properly terminate, without stubs to termination resistors. That means; route past receiver pins and finish trace with terminator. Most HS receivers have built-in receivers these days so a non-issue, often.

3) If you cross board layers (top to bottom, for example) using vias, make sure to use ground vias close to the signal transition vias. This allows the return current to jump from the ground plane close to the originating layer to the ground plane next to the destination layer (assuming ground plane under each signal layer, of course). For diff pair, use one GND via on each side. If none are used then the return signal will have to take a long detour on the PCB until it finds some remote GND via, which allows the return signal to transition to the target ground plane. Such long path ads inductance and you'll end up with "ringing" (which is not reflections - reflections look like steps, while inductance looks like ringing, which is exactly why a scope probe with long ground wire causes the signal to appear to "ring" on screen).

Also note that proper POWER INTEGRITY Is required for HS design since HS ICs need proper PI design to work reliably. This subject is more complex since it needs advanced software such as Hyperlynx to simulate PI of the various power/ground plane layers. I have done such PI simulations for a few of my customers (on consulting basis) and it becomes more common that modern large ICs souch as SoC's and FPGAs don't work reliably due to incorrectly (under) designed power planes and decoupling capacitor placement. The speedingedge books explain this in detail but so do various app notes from Altera and other IC vendors. Bogatins and Peng Li's books also go into this subject ad nauseum...

Make sure to check out Dave's video on PI, too (decoupling caps etc). Use the search button, Luke...
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Offline hendorog

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #47 on: April 22, 2017, 09:01:14 pm »
GS6042 Datasheet says:

"The differential output can be DC-coupled to Semtech’s
reclockers and cable drivers, as well as industry-standard
CML logic by changing the voltage applied to the
VCC_O pin. In general, DC-coupling to any termination
voltage between +1.2V and +3.3V is supported."

VCC_O is 3.3V so you don't need the caps at all, or what am I missing?

I reckon there are still copper areas that are flapping in the breeze and need to be pinned down with vias.

 

Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #48 on: April 22, 2017, 09:35:35 pm »
The GS6151 is 1.8v which is why I AC coupled them. It may be software switchable with Gennums oddball interface, but I was hoping to use the default and not count on being able to change the configuration registers.

I think that fixing the ground planes and capacitor locations should make a drastic improvement. Meeting with Samtec next week about the BNCs

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Offline rx8pilotTopic starter

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Re: High-Speed PCB layout challenges - Learning the dark art the hard way.
« Reply #49 on: April 22, 2017, 09:39:48 pm »
oh wait..... I see what you are pointing out. Maybe you are correct, I may be able to simplify the caps out of the circuit altogether - getting rid of a bulky disturbance in the force.

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Factory400 - the worlds smallest factory. https://www.youtube.com/c/Factory400
 


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