High-Speed PCB layout challenges - Learning the dark art the hard way.

[rx8pilot]

I have finally arrived at some of my first practical high-speed PCB layout. This journey started about a year ago after winning the Keysight Test to Impress contest where I found myself with a very unique opportunity to learn a whole new set of skills. The last year was spent reading about high-speed digital and RF systems and saving money for the mandatory 6Ghz active probes to actually use the new scope to it's full potential. Well....I got the 1st probe a couple of weeks ago so here we go. I figured this is a good place to get me feet wet with the unique and detailed challenges in designing for high-speed signals. The industry is going toward 12Gbps serial data over coax with BNC connectors - crazy right? BNC connectors being tested out to 18Ghz.

The first project is only an experiment in signal integrity. It is a simple 1x2 serial digital distribution amplifier that will run up to 6Gbps. It has a 75 ohm single-ended input on BNC and 2 outputs that drive 75 ohm coax on BNC. Internally the signals are moved around on 100 ohm differential lines. The chips are Gennum (now Semtech) that handle EQ, clock recovery, and line driving. The assumption is that I would make a number of beginner blunders, so I wanted to get my first PCB done even before I had any real confidence. I believe that will speed the learning curve for me to build some intuition while learning what I need to learn to actually be successful.

Cable EQ: Semtech GS6042 http://www.semtech.com/broadcast-video/equalizers/gs6042/
Re-Clocker: Semtech GS6151 http://www.semtech.com/broadcast-video/reclockers/gs6151/
Cable Driver: Semtech GS6080 http://www.semtech.com/broadcast-video/cable-drivers/gs6080/

Semtech does not have too much detail on layout examples so I decided to just take a stab at it and see how far I have to go. PCB's are cheap and there is a lot of value in learning how far I have to go. The goal was to use standard FR4, 1oz, 4 layer, typical stackup with two 2116 prepreg and a .040" core. All signals on the top layer, layer 2 GND plane, layer 3 power, layer 4 GND2 with some low-speed control signals. The manufacturer indicates FR4 is no problem, especially with such a compact layout, assuming it is done well. The PCB is not impedance controlled by manufacture, so the trace impedance is only an estimate.

The schematic is attached along with the layers 1, 2, and 3 of the layout. One of my biggest unknowns is how the differential signals should be handled and just how sensitive they will be. I used an online calculator to determine the trace width and spacing (with no way to simulate it). There are 2 differential traces on this design and they are AC coupled to deal with the differing DC bias between the chips. Was scratching my head on the proper placement of the caps (0402). I initially blended the trace into the width of the cap, but then just used a straight trace. Some online conversations suggested putting the caps close to the TX, others the RX, and still others said it did not matter since the impedance of the cap is so low at multi-ghz frequencies. I put them in the middle. The short diff-line is about 10mm total - 5mm on each side of the AC caps. The longer diff-line is about 19mm total with the AC caps in the middle.

While the chips are capable of 6gbps data rate, I only have a 1.5gpbs signal generator on my bench at the moment. I assembled the first PCB yesterday, and to my surprise - it worked. It is not, however, working all that great. I made some quick measurements to get a sense of what was happening. The receiver is easily able to decode the data but there are clearly some impedance issues ringing the signal. The input measurement (before the equalizer) shows the expected amplitude and eye quality at the input of the GS6042. The differential output shows a rougher eye than I was hoping for. The output of the reclocking GS6151 is similarly distorted. Both have the expected amplitude so I guess the internal terminations are doing the right thing. I am not really sure what the most likely source of the distortions/reflections is. the AC caps? Return current problem? Something else?

This is such a steep learning curve, but is also a lot of fun and very fascinating. Thanks in advance to anyone willing to offer some insight and critiques. I have thick enough skin to deal with harsh criticism as long as it is specifically targeted at building an understanding of this topic.

[tggzzz]

A few thoughts, which are worth what you pay for them...

You have 100ps transitions, corresponding to 20mm on a PCB. Your lines have to be terminated correctly. I presume the termination is inside the receiving chip.

You have ~200ps ringing period, corresponding to ~10mm of unterminated (or poorly terminated) line; see http://www.edn.com/electronics-blogs/all-aboard-/4438918/What-is-the-ringing-period-on-an-unterminated-line--Rule-of-Thumb--26

The impedance of the capacitors should take account of their inductance as well as their capacitance. Personally I would put them at one end, so all impedance variations are concentrated in one place.

Which online calculator did you use, which models, what parameters, and what results? Many models don't have any "flood" groundplane nearby on the signal layer. If coplanar waveguide, I would expect to see many vias along the surrounding flood, providing the "fence" to the groundplane.

Have you done a quick-and-dirty spice model of the outputs, transmission line and capacitors, and inputs?

Did you consider having many more via connections "stapling" the flood to the groundplane all over the board?

[rx8pilot]

A few thoughts, which are worth what you pay for them...

You have 100ps transitions, corresponding to 20mm on a PCB. Your lines have to be terminated correctly. I presume the termination is inside the receiving chip.

You have ~200ps ringing period, corresponding to ~10mm of unterminated (or poorly terminated) line; see http://www.edn.com/electronics-blogs/all-aboard-/4438918/What-is-the-ringing-period-on-an-unterminated-line--Rule-of-Thumb--26

The impedance of the capacitors should take account of their inductance as well as their capacitance. Personally I would put them at one end, so all impedance variations are concentrated in one place.

Which online calculator did you use, which models, what parameters, and what results? Many models don't have any "flood" groundplane nearby on the signal layer. If coplanar waveguide, I would expect to see many vias along the surrounding flood, providing the "fence" to the groundplane.

Have you done a quick-and-dirty spice model of the outputs, transmission line and capacitors, and inputs?

Did you consider having many more via connections "stapling" the flood to the groundplane all over the board?

Yes, the terminations are internal to the chips.

I used:
http://www.multek.se/engelska/engineering/pcb-structures-2/differential-microstrip-impedance-calculator-2
With the settings in the attached image. At my early learning stage - I don't have enough understanding of whether or not this is good information.

I have not done any SPICE sims and honestly don't know how to model this one.

I have seen some other boards with ground stapling, but it seemed more common on longer traces. I guess it would help with any trace that is considered a transmission line? Do you suppose the top layer ground flood is a problem? Especially since it is not stitched to the ground plane.

I am going to take a quick look to see if I can pull off a micro-bodge of the caps. It won't be anything like ideal, but I am curious how sensitive the placement is.

[lem_ix]

The ground pour should probably be further away, if I remember correctly for a microstrip for example it was like 2-3 times the width of the controlled trace but don't take my word on it. Tggzzz linked an article by Eric Bogatin, if you search for more articles by him(Bogatin's rules of thumb) on EDN you'll find some simulations and recommendations. The pour stitching is there to reduce the inductance between the planes which is definitely significant for the frequencies you're playing at. There was a rule of thumb for the "stitching frequency" aswell. Doing my first rf board soon, so many things to consider 

[rx8pilot]

A quick observation....

I measured the ringing period on both of the differential pairs at the coupling capacitors, they both have the exact same period of 188ps. The short one is about half the length of the longer one so I would expect the ringing frequency to be different. I confirmed the termination schemes in the datasheets to make sure there was not an option to disable.

[rx8pilot]

The ground pour should probably be further away, if I remember correctly for a microstrip for example it was like 2-3 times the width of the controlled trace but don't take my word on it. Tggzzz linked an article by Eric Bogatin, if you search for more articles by him(Bogatin's rules of thumb) on EDN you'll find some simulations and recommendations. The pour stitching is there to reduce the inductance between the planes which is definitely significant for the frequencies you're playing at. There was a rule of thumb for the "stitching frequency" aswell. Doing my first rf board soon, so many things to consider 

I should take a look at Eric Bogatins other articles - I just read the one linked above. I always like the rules of thumb to help me get oriented in the general direction of success. Good luck on your first board. I am glad I did a PCB early on, I think it will be very helpful when I am neck deep in a signal integrity book by offering some real context to concepts.

Photo is from a commercial device using similar, but somewhat older chips. The diff pair is surrounded by a large, un-stitched ground plane. The trace length is substantially longer as well. Still reading, pondering......

[KE5FX]

Those expanses of ungrounded copper scattered all over the place are definitely a problem.  If you don't have good simulation capabilities, then whether they act as capacitors, antennas, or other unwanted circuit elements is a matter of luck.  You should use vias -- lots of vias -- to ground those islands to a solid plane immediately underneath.  It should look more like this:



Vias are fun.  They're your friends.  They're free.  We like vias.    They aren't without parasitic properties of their own, of course, but you have bigger problems with all that unattached copper lying around.

And yes, Bogatin's book is quite good... definitely put that one on your list.  Henry Ott's latest edition, too, maybe?

Finally, study board designs from places like Tektronix and HP/Agilent/Keysight, not whatever clown shop did the one in your photograph.  (Exception: they might be stitching their ground planes together with blind vias.)

[rx8pilot]

Those expanses of ungrounded copper scattered all over the place are definitely a problem.  If you don't have good simulation capabilities, then whether they act as capacitors, antennas, or other unwanted circuit elements is a matter of luck.  You should use vias -- lots of vias -- to ground those islands to a solid plane immediately underneath.

I cleaned up a few things, moved the AC coupling caps close to the TX pins, blended the traces into the 0402 footprint, fixed a few PDN issues, fixed an input termination mistake, and of course added a pile of guard vias.

Still trying to figure out if the differential pairs need more room to the top ground pours to maintain the 100 ohm impedance. Thanks for the input so far.

[hendorog]

These comments are based on my experience fiddling with GHz circuits without really knowing what I'm doing. As that is what you said you are doing I feel qualified to comment

I would have broken that circuit down into simpler modules first - e.g. connect eval boards together and use that as a reference to compare your own design with. Make single chip boards first and string them together and try to match the eval boards.

Can you remove the downstream chip, terminate the differential pair with a low inductance 100 ohm resistor and then re-test. Then play around with the caps and get an understanding of what is going on.

Other things:
Vias have already been covered, but KE5FX (guru) mentioned 'islands'. i.e. _areas_ of copper should also be grounded by multiple vias, not just the microstrip lines. If there are small areas that are hard to put a via in then remove the copper pour there.
One of the differential pairs takes a 90 degree turn, so the path length can't be the same for both lines in the pair unless you are doing something clever to correct for that. Maybe the difference is too small to matter.
The width of the microstrip lines to the two output connectors is not the same.

[T3sl4co1l]

Top side ground is not a problem, the impedance is just lower (for a given trace width).  It's called coplanar waveguide (CPW).

It does need to be stitched.  It looks like there's about half as many vias as there should be.

Tim

[Twoflower]

From the HS-Boards I see in the past I never saw GND pour below the devices. This could easily create jumps in the impedance. Also the inductors might have some playground for resonances.

If possible use smaller R/C/Ls that don't change the tracewidth for the pad.

I also would reduce the stubs for the biasing. Place the pad of the resistor directly on the HS-trace. Also try if you can place the parallel L-C combos closer together.

The length adaptation between U2 and U3 must be as close as possible to where the mismatch appears. This reduces the time the signals (as they're coupled) run mismatched on the PCB. And if possible do just one meander.

Also U2->U3 there's no ground-plane at parts of the trace. That most likely will hurt a lot.

Also the design shows on some places no GND pour around the HF-Parts (lower part of the board).

[AndyC_772]

Talk to Lee Ritchey at Speeding Edge, he's the guru for high speed PCB design and layout. Get onto one of his training courses if you can, they're brilliant.

http://speedingedge.com/

[lem_ix]

Should probably recalculate the impedance with a different model or move the pour. No idea how much of a difference this makes in practice, hopefully someone with more xp can comment.

Some commercial tool for Differential surface coplanar waveguide with ground


Maybe someone knows a free calculator for this.

[AndyC_772]

Saturn PCB toolkit?

[lem_ix]

Think it only has standard edge coupled microstrip under differential pairs (no top gnd). There is coplanar wave but not differential. Or am i missing something?

[T3sl4co1l]

Roughly speaking:

Oh, let me abbreviate microstrip = MS, and differential = D.

If you take the ratio of Z_CPW(d) / Z_MS(d), that will be the amount of impedance reduction due to the top side ground fill.

Set d = 2*w + s, the width of the pair.  (Gap D, height H, etc. all normal as shown.)

The reduction is usually 10-20%, i.e., the ratio is about 0.8-0.9.

Now apply half this ratio to the normal impedance of one trace in the DMS result.  That is, "half" in the percentage sense, or "half" in the logarithmic sense (i.e., use sqrt(ratio), or percentage/2).  That will be close to the impedance of DCPW.

This method isn't based on anything rigorous, just a wave-of-the-hands estimation that should be more accurate than taking the extreme of either case (i.e., CPW for single traces and assuming DCPW has the same normal impedance; or using DMS and outright ignoring the contribution from ground fill).

A more accurate answer seems unlikely to be necessary, given the gross tolerances we're concerned with in the first place (typically 20% for controlled impedance fabs).

Tim

[tggzzz]

I used:
http://www.multek.se/engelska/engineering/pcb-structures-2/differential-microstrip-impedance-calculator-2
With the settings in the attached image. At my early learning stage - I don't have enough understanding of whether or not this is good information.

I have not done any SPICE sims and honestly don't know how to model this one.

It is often worth using multiple calculators, since they sometimes have different situations (e.g. coplanar waveguide) and even different equations.

As for Spice sims, you can always use them for a simplified situation. In this case I would have:

• a signal source with internal resistance Z0=50ohms, risetime 100ps
• a length of perfect transmission line, Z0
• a capacitor
• a length of perfect transmission line, Z0
• a terminating Z0

And just see what you can see.

You won't get the same results that you will see on the PCB, but you will get a feel for whether you are in "here there be dragons" territory.

I'd then make a more sophisticated capacitor model, including parasitic inductances and capacitances - you could even nick them from resistors of the same size. There are suitable starting points in Vishay app notes.

You should also add in the parasitic capacitances in the receiver (and maybe even inductances). You should be able to get these from the data sheet and/or IBIS models.

[TiN]

What is your CAD? Isn't there integrated tools for differential pair routing?
Currently it looks like you have manually done everything, and that might be more effort than should be. When routing HSD you need to maintain running skew (phase) and impedance.
6Gigs is not much.

If you want to go bit extreme - find somewhere dead not so old motherboard (one with PCIe Gen3 at least) and sand layers on my one, to see some good ideas .
Modern USB 3.0/3.1 routing examples can be helpful too, and DEZ is around similar what you have. Make sure you have correct termination (enabled and set properly if it's onchip, populate termination components if it's external).
Pay attention to coupling mode, sometimes differential are AC coupled, sometimes DC coupled, depends on your design. Try to avoid any reference plane voids under high-speed routing, maintain return currents.

Vias are friends, but too much friends can ruin the party, so need to be careful, not to turn your planes into a swiss cheese.

If you can give us your exact stackup (I guess 4 layer PCB?) and your PCB material, I can help to rougly check line parameters.

[dmills]

One thing to watch with SDI which I am guessing you are playing with (Genum, 12G, 75 ohm, BNC, gives the game away) is that it does have pathological conditions so those caps typically need to be **MUCH** bigger then you would really prefer (4.7uF springs to mind for some reason, tends to make for interesting parasitics so place the caps right next to one end of the line is favourite).

Why they did not do 8b10 or 64b66 or something similar is a legacy issue from the days of 270Mb SD that somehow never got fixed.

My favourite approach is to observe that tracking you don't have does not give impedance problems, there is something to be said for getting the silicon close to the connectors and close together to minimise the problems.   

Going for a thin layer spacing is also helpful as is using high Tg FR4 (It tends to be better behaved).

Regards, Dan.

[rx8pilot]

One thing to watch with SDI which I am guessing you are playing with (Genum, 12G, 75 ohm, BNC, gives the game away) is that it does have pathological conditions so those caps typically need to be **MUCH** bigger then you would really prefer (4.7uF springs to mind for some reason, tends to make for interesting parasitics so place the caps right next to one end of the line is favourite).
Why they did not do 8b10 or 64b66 or something similar is a legacy issue from the days of 270Mb SD that somehow never got fixed.
My favourite approach is to observe that tracking you don't have does not give impedance problems, there is something to be said for getting the silicon close to the connectors and close together to minimise the problems.   
Going for a thin layer spacing is also helpful as is using high Tg FR4 (It tends to be better behaved).

Yes - this is HD-SDI as defined by SMPTE. Yes, the ac coupling caps are recommended to be 4.7u.

What is your CAD? Isn't there integrated tools for differential pair routing?
Currently it looks like you have manually done everything, and that might be more effort than should be. When routing HSD you need to maintain running skew (phase) and impedance.
6Gigs is not much.

Sadly - EAGLE CAD is the tool. The support for differential routing is comedy gold - useless and hilarious. My strategy is to manually fight the marginal routing tools and then measure the length. If I end up going further down this road - Eagle is out. I can't imagine doing this type of design regularly with it.

If you can give us your exact stackup (I guess 4 layer PCB?) and your PCB material, I can help to rougly check line parameters.

The stackup is 4 layer, .062, FR4, 1oz. 2116 prepreg with .040" core. (chart attached as image). I did not specify impedance control and curious if the fab house just uses whatever prepreg/cores they had that day (PCBway, cheap-o service). In a production world, I wonder if this type of design will only see success with exotic high-speed dielectrics and impedance control. It makes a significant difference in price over FR4.

Roughly speaking:
Oh, let me abbreviate microstrip = MS, and differential = D.
If you take the ratio of Z_CPW(d) / Z_MS(d), that will be the amount of impedance reduction due to the top side ground fill.
Set d = 2*w + s, the width of the pair.  (Gap D, height H, etc. all normal as shown.)
The reduction is usually 10-20%, i.e., the ratio is about 0.8-0.9.
Now apply half this ratio to the normal impedance of one trace in the DMS result.  That is, "half" in the percentage sense, or "half" in the logarithmic sense (i.e., use sqrt(ratio), or percentage/2).  That will be close to the impedance of DCPW.
This method isn't based on anything rigorous, just a wave-of-the-hands estimation that should be more accurate than taking the extreme of either case (i.e., CPW for single traces and assuming DCPW has the same normal impedance; or using DMS and outright ignoring the contribution from ground fill).
A more accurate answer seems unlikely to be necessary, given the gross tolerances we're concerned with in the first place (typically 20% for controlled impedance fabs).

Tim

Curious if there is any practical reason to have the diff pairs setup as a DCPW at all. Do you suppose it will simplify the challenge to just lose the top ground fill (around the differential pairs)? I dug up some other designs using the same signals and chips at 12gbps and they have isolated diff pairs and use CPW only for the single ended 75 ohm. With that in mind - if a CPW configuration can improve the signal integrity in the long term, I will stick with it and deal with the learnig curve.

[rx8pilot]

Maybe this layout will have easier to predict the behavior of the differential signals?

[Pitrsek]

Talk to Lee Ritchey at Speeding Edge, he's the guru for high speed PCB design and layout. Get onto one of his training courses if you can, they're brilliant.

http://speedingedge.com/

Wholeheartedly agree!

For micro strip calculations I use TNT field solver https://sourceforge.net/projects/mmtl/files/

You can sweep variables, see how much it moves with spacing, width, er...
If you bother with measuring your material beforehand, it's actually very capable/accurate. Beware of asymmetry ratio problems(see manual). Another free field solver is http://openems.de/start/index.php, but i have not tried it yet. Actually I received boards today 46.5R, caclulated for 50. In a rush job prototype service(absolutely not "controled impedance"). It's not spectacular, but I can live with it. Er from manufacturer spec sheet, I did not made my own material specification this time. 

Biggest problem is getting right numbers from the PCB vendor and If you can trust them that they'll use same stuff. IMHO it's well worth spending time and money to make some test coupons to measure er/ verify your microstrip design. Actually it's a very good idea to put test micro strip on every pcb, so you can verify that your board is manufactured properly. If you are not space constrained, I very much recommend it.

I don't think your BNC footprint is maintaining 75R.
https://www.smtnet.com/library/files/upload/optimizing-bnc-pcb.pdf

Also check for stack-up - if it is really what you specified. Problem with controlled impedance traces on prepregs is that the thickness is quite variable. It depends on pcb processing and pcb itself(how much resin is going in between traces). You need your fab house to tell you how thick the prepreg will be in the end. Or you can design your design over core - there is no curing, thickness is precisely defined (compared to prepreg). Furthermore, if your trace is on core burried inside of the pcb, copper plating thickens is also very precisely defined. If you route on outside(top/bottom), you get thickness variance due to plating (a LOT of it actually). So if your trace design is sensitive to copper thickness this is something to keep in mind.  Also having close track/plane spacing(thin prepreg) makes your design very sensitive on track width - so under etch/over etch hurts... If you increase your spacing/make your tracks wider, it's way better(relative change of width and thus impedance change is way smaller). 

You need to be able to measure it, otherwise you are just poking in with a stick, not really knowing what are you doing. Any chance to test it on TDR/VNA?
With your high speed scope and some RF generator you might be able to to "check it", it won't be really accurate, but better than guessing.
https://www.google.cz/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahUKEwj4jPW87LPTAhUBfRoKHdRwBVkQFggoMAE&url=http%3A%2F%2Fwww.edn.com%2FPdf%2FViewPdf%3FcontentItemId%3D4435822&usg=AFQjCNGN-cfl0fUGHrbISBJC9srE5y2YOQ&sig2=SDGr3hhWfir7C_7K3lld6g
 




 

 

[rx8pilot]

For micro strip calculations I use TNT field solver https://sourceforge.net/projects/mmtl/files/

You can sweep variables, see how much it moves with spacing, width, er...
If you bother with measuring your material beforehand, it's actually very capable/accurate. Beware of asymmetry ratio problems(see manual).

Interesting tool, I will check it out. I just downloaded Sonnet Lite and Saturn toolkit to have a look around.

Talk to Lee Ritchey at Speeding Edge, he's the guru for high speed PCB design and layout. Get onto one of his training courses if you can, they're brilliant.

http://speedingedge.com/

Wholeheartedly agree! 

Looking into that one.....I suspect it will prevent countless re-spins if I actually do it.

Biggest problem is getting right numbers from the PCB vendor and If you can trust them that they'll use same stuff. IMHO it's well worth spending time and money to make some test coupons to measure er/ verify your microstrip design. Actually it's a very good idea to put test micro strip on every pcb, so you can verify that your board is manufactured properly. If you are not space constrained, I very much recommend it.

I could go with a controlled impedance PCB and let the fab do the TDR on coupons they generate. As for T&M, I am very limited in both equipment and the delicate skills to use them. When I first decided to go down this path, I was hoping to get started at bandwidths that were attainable as a business experiment. The problem is that in the TV industry 1.485gbps has been standard and 3gbps was the fancy high-speed option. 3Gbps serial data is now considered slow with 6gbps quickly becoming normal. 12G is already becoming a standard thing even though there is not yet much use for it. In the end, I need to be willing and able to design with 12G serial IO. That is like drinking from a 6inch fire hose. I was looking at VNA's and thinking that I could get somewhere with an older 6Ghz model with various used eCal, cables, and fixtures. That would not be helpful for long before I needed a 20Ghz system to effectively design clean 12gbps IO. At those rates, the test equipment, calibration, fixtures, and skills are quite a  serious journey. The cost of everything skyrockets. The precision needed for success skyrockets. 

To finance that education and test gear, I am hoping to get through some relatively simple products that I can integrate into my existing products that are 6gbps max capable. My only real option is to make solid guesses based on simulation-intuition-best practices-online calculation, and expect a number of re-spins to get into spec using the only high-speed tool I have - an oscilloscope. The good news is that the Keysight scope has an excellent color graded eye application and jitter analysis. It does not tell me all that much about what exactly is wrong - but at least I can see if it is right or wrong. With that in mind, I did contact Samtec and they are able and willing to help with tests, footprint design, etc. They have a fully configured lab for practical testing. However much they charge for that, it will be a LOT less than me buying the gear and hacking through a long and very challenging learning curve. If that actually happens, I suspect I will learn a whole lot just as an observer of the process. Samtec will not help with the whole system, however, just the connectors.

I am looking at the BNC footprints a lot closer now. Samtec engineers will be at a trade show next week where I can meet them.

[basinstreetdesign]

My 2cents:
Get a copy of Johnson and Graham's High Speed Digital Design, A Handbook of Black Magic.  This is one book every engineer designing high speed logic should read cover to cover.

[rx8pilot]

My 2cents:
Get a copy of Johnson and Graham's High Speed Digital Design, A Handbook of Black Magic.  This is one book every engineer designing high speed logic should read cover to cover.

On the way.....$30 is a no brainer. Thanks.