Homebrew digital computer system

[xygor]

Here's an interesting article on the first person to build a transistor based computer in Europe (1955).
http://news.slashdot.org/story/14/07/18/0253245/heinz-zemanek-passes-at-94
I'd never heard of that one before.

Also wiki article.
http://en.wikipedia.org/wiki/List_of_transistorized_computers

[GK]

As promised, photos of the front panel (which arrived this morning). It will look a lot prettier once I have the LED PCBs installed. All switches are Multicomp "snap in" series.

[mamalala]

Very nice looking!

Greetings,

Chris

[Dave Turner]

Wow! Do I detect PDP11 overtones?

[bwat]

Love it.

[GK]

Yeah, I was a bit apprehensive about the blue, but it turned out really nice.

[GK]

Finally getting back to this project. Today I completed and tested and tweaked the 1st assembled, plug-in card:



This is the low frequency "system clock" card. The computers operating (clock) speed is LED-indicated and user-set from the control panel, from 2 uS to 200 mS in discrete 1/2/5 steps. There will also be a high frequency clock source (selected by "EXT") that will operate at the highest frequency permissible (which will be finally determined once the whole computer is operational).

Being able to control the computers speed will be very useful when I'll eventually use the machine to automate processes on my (simultaneously under construction) analog computer.

This card provides 50% duty cycle clocks of 500 kHz (2 uS), 200 kHz (5 uS) and 100 kHz (10 uS). These are all derived from a 2 MHz, heated-crystal oscillator. Here is the schematic:

https://www.eevblog.com/forum/projects/homebrew-digital-computer-system/?action=dlattach;attach=111834

Q1 through Q10 form the calibrated 2 MHz heated-crystal reference (probably got a little carried away here).
Q11 through Q14 form a pair of cascaded toggle flip-flops which divide the 2 MHz down to the 500 kHz reference.
Q15 to Q23 form a three stage ripple counter which is reset on count 5 (decoded by NAND gate Q24) by a triggered reset pule produce by the ~120 nS monostable formed by Q25-Q27. This complete divide-by-five counter derives a 400 kHz clock from the 2 MHz master which is then divided down to 200 kHz and 100 kHz by a pair of further cascaded toggle flip-flops based on Q28 through Q31.

Transistors Q32, Q33 and Q34 are three open-collector-output NAND gates having their outputs commoned to form the actual clock output. Select lines to the NAND gates determine the output clock frequency.

A series of further multiplexed decade divider cards will provide the LF reference clocks for the 20 uS to 200 mS system clock settings. Then in addition to this is the actual selector card comprised of a decimal-decoded 1-or-16 BCD counter, user set by the control panel buttons for selecting the "system clock frequency". That will complete the computers LF clock. These cards are the next in line to be etched...................

I had originally planned to build a linear supply for the computers 15V 20A logic supply. However I eventually decided against this as the heat sinks took up too much rack panel space (and card frame access). I've now designed a switch mode supply for the 15V rail instead. Here is the control board:



I decided to have a little fun here - this is actually a discrete TL494. The six (identical) TO-126 transistors bolted together are the comparison transistors for the Brokaw-style bandgap 5V reference regulator. 5 of the 6 transistors are connected in parallel to effectively give one transistor of a pair having an "emitter area" five times that of the other. With some heatsink compound between the transistor packages and the bolt through the middle keeping them all in close thermal contact, it actually turned out quite well and more than adequately stable. (about 20 mV drift to the +5V for a 20 deg C change in room temperature).

I'll have the companion power board for the 15V 20A rail loaded and operational once some parts on back-order arrive.

[GK]

Made a start on the decade divider card for the programmable system clock. The 81 transistors and 228 diodes are soldered in place, and a few of the 138 capacitors. There are 5 stages of decade division on this card. Each decade divider consists of a divide-by-5 counter followed by a divide-by-2 toggle flip-flop. This gives decade division with a 50% duty cycle logic signal output. Then there a six individual DTL inverter stages acting as clock-in and clock-out signal buffers. The counter circuitry is a duplicate of that I've already posted for the system clock card. I've retained the high-speed, clamped-logic-level circuitry throughout, to the 200mS clock output, to ensure that all clock signals have the lowest practical jitter. I'm pleased with the component packing density I managed on this card. Tomorrow evening I'll get the 244 resistors soldering in and maybe some of the caps too. 

[GK]

Finally got the decade divider card finished.

The wee-little schematic diagram (the serious logic assembly hasn't started yet) here: https://www.eevblog.com/forum/projects/homebrew-digital-computer-system/?action=dlattach;attach=113615



Unfortunately I wasn't able to make a decent jitter measurement for the full five decades of division on my Rigol scope. The first stage of decade division triggers on the positive edge of the clock input. These scope photos (with infinite persistence) show the clock input (yellow trace) and the first decade (/10) clock output:





In both photos I'm triggering on the divider output and in the lower photo viewing the active edge of the clock input. There appears to be ~5nS of peak-peak jitter.

In the following photo I'm viewing the active edge of the clock input again, but this time against the /10,000 clock output. The clock input is 500 kHz and the output therefore 5 Hz (note the delay between the trace clock edges is greater than before as each decade divider has a ~40nS clock in-out delay):
 


The screen is only updating a several times per second due to the low frequency of the divided down output, but I would have though that given enough time, with infinite persistence enabled, I still should have gotten a plot of the net, accumulated peak-peak jitter of the five series-connected stages of decade division. However, as shown in the scope screen photo, no so at all. There should be at least a full horizontal division of peak-peak jitter there. It's getting onto midnight here and I have had a long day, but what am I missing?
 

[deephaven]

I'm enjoying following your progress.

On a specific, regarding your 2MHz crystal oscillator, I can understand how most of it works, but could you explain the function of Q7?

[GK]

Q7 is just a cascode that helps mitigate the Miller effect of Q5. It gives the amplifier a little extra bandwidth and less phase shift, although the benefit is only small as the base of Q5 is already driven from a low impedance source (unity gain buffer pair Q1 and Q2).

[deephaven]

Q7 is just a cascode that helps mitigate the Miller effect of Q5. It gives the amplifier a little extra bandwidth and less phase shift, although the benefit is only small as the base of Q5 is already driven from a low impedance source (unity gain buffer pair Q1 and Q2).

Thanks for the explanation. Does that configuration of oscillator have a name? I usually just use a Colpitts.

[GK]

Pierce oscillator.

[TonyStewart]

@GK phase noise is additive only if there is threshold error, supply noise , Non-flat group delay or non-linear phase shift in detector or scope trigger.

Normally synchronous counters add no jitter to output unless skew in rise/fall time.
Whereas impulse harmonic multipliers add phase noise xNth harmonic.

Asynch or ripple counters will accumulate prop delay and jitter however.

[coppice]

The bad news is that the PDP-8/S did not do well in the marketplace.  It was not quite completely capable of running straight 8 programs, and was too slow.  In fact, it was so slow that it could not successfully operate certain common DEC mass storage peripherals (e.g. TU-55 DECtape transport).

The PDP-8/S may not have done well, but there were numerous specialised bit serial machines in the 60s and 70s. There were also massively parallel single bit architectures, like the MPP and ASPRO, which could be extremely effective in certain applications.

[GK]

@GK phase noise is additive only if there is threshold error, supply noise , Non-flat group delay or non-linear phase shift in detector or scope trigger.

Normally synchronous counters add no jitter to output unless skew in rise/fall time.
Whereas impulse harmonic multipliers add phase noise xNth harmonic.

Asynch or ripple counters will accumulate prop delay and jitter however.

OK, but I'm looking at asynchronous ripple counters performing the frequency division. With an infinite persistence display the peak-to-peak clock-in-clock-out jitter through successive stages should roughly add as given enough time there will be coincident peaks, it's just that the DSO appears to mask the effect. I've repeated the tests on a 500 MHz LeCroy scope with the same results. I get ~5nS of p-p displayed jitter for the 1st (decade divider) stage and successively less p-p displayed jitter as I probe down the chain of cascaded decade dividers.

The attempted jitter measurement was just a curiosity, it has no real bearing on the commissioning of the clock circuitry.

[GK]

Another card comes fresh from the etch tank. This is the control card for the programmable frequency system clock. It will look a lot prettier one it is drilled and then buffed up with steel wool prior to lacquering. The card contains a 4-bit binary counter with control logic that is set by the control panel buttons for system clock period/frequency selection. The card contains LED drivers and the 4-bit binary is (1-of-16) decimal decoded for the clock period LED indication on the control panel. The binary counter is also decoded to provided the control signals for the decade divider multiplexers (on another card) and the 1/2/5 multiplexer on the clock card.

Right now I'm laying out the Instruction Register and Decoder card. Then it will be either the bit-serial arithmetic logic unit card or the major state generator. I'm not progressing in any particularly logical order.......

[SeanB]

http://omegataupodcast.net/2014/11/159-analog-computers/

[GK]

Thanks, that podcast looks interesting, but unfortunately I'm almost out of download quota for the month, so will have to wait a little while.

As for the digital computer project, two additional PCB's emerged from the etch tank this afternoon. One is the instruction register and decoder card and the other is a 3-stage bi-directional, serial-in, serial/parallel-out shift register building block, 5 duplicates of which (plus 2 other cards containing the remaining two register stages plus associated control logic) will form the complete circuitry of the the Accumulator+Link registers.

[GK]

... and the other is a 3-stage bi-directional, serial-in, serial/parallel-out shift register building block, 5 duplicates of which (plus 2 other cards containing the remaining two register stages plus associated control logic) will form the complete circuitry of the the Accumulator+Link registers.

Have that card loaded and tested now:



The shift register that forms the accumulator register (plus the link bit register - the carry for multiple precision arithmetic) needs to be bi-directional so that both the RAR (rotate accumulator right) and RAL (rotate accumulator left) microinstructions can be executed. Except for the RAL microinstruction, the AC ordinarily operates as a right-shift storage register only.

I still have 4 duplicates of this card and two others to assemble before I have a complete and operational AC+L register, but for testing purposes, for this 3-stage card, I just looped the "right-shift serial output" to the "right-shift serial input" and the "left-shift serial output" to the "left-shift serial input" so that the 3-bits just keep circulating around the loop with a master (synchronous) clock applied.

Prior to applying the continuous clock the register was pre-loaded with binary 1 0 0. Here it is in right-shift mode. The traces from top to bottom are QA (also the left-shift serial output), QB, QC (also the righ-shift serial output) and master clock.



Here it is in left-shift mode:
 


 

[GK]

Here is a (simplified) logic diagram for the complete Accumulator and Link register. When the RAR.L and RAR.L control signal inputs are both high, the sixteen Q15 through Q0 flip-flops simply act as 16-bit serial-in, serial/parallel-out shift register that operates completely independently of the single bit Link register. In this state the master clock is disconnected from the Link register flip-flop and the Link register has 2 active control inputs independent of the Accumulator register.

The control inputs are complement_link, set_link and clear_link. The link bit is complemented (toggled) by the control circuitry associated with the binary full adder part of the arithmetic logic unit whenever there is a carry after executing a TAD (two's complement addition) instruction. The Link bit is also complemented when the CML microinstruction (of the OPR main instruction) is executed. Microinstruction CLL (clear link bit) resets the Link bit to 0. There is no specific microinstruction to set the Link bit. To set the Link bit CLL and CML are simply programmed/executed in succession. My hand-drawn logic diagram shows a set.L input for the Link flip-flop, but this is not used in the final circuit as it is redundant.

The logic gets a little messy because the bit-shifting operations treat the Link and Accumulator as a single 17-bit register. When the RAR.L control input is asserted low by the instruction register and decoder card during an execute machine state, a clock input will rotate the entire contents Link and Accumulator of the one bit to the right:

Link>Q15
Q15>Q14
Q14>Q13
Q13>Q12
Q12>Q11
Q11>Q10
Q10>Q9
Q9>Q8
Q8>Q7
Q7>Q6
Q6>Q5
Q5>Q4
Q4>Q3
Q3>Q2
Q2>Q1
Q1>Q0
Q0>Link

When the RAL microinstruction is executed the same sequence of events occur, but the steering gates to the individual D-inputs of all 17 flip-flops switch over to the proceeding Q outputs rather than preceding, thus causing the register bit to rotate left instead:

Link>Q0
Q0>Q1
Q1>Q2
Q2>Q3
Q3>Q4
Q4>Q5
Q5>Q6
Q6>Q7
Q7>Q8
Q8>Q9
Q9>Q10
Q10>Q11
Q11>Q12
Q12>Q13
Q13>Q14
Q14>Q15
Q15>Link
 
The "Type C" circuit card of the AC+L, containing the AC register Q0 flip-flop also carries a 16-inout NOR gate which provides an Accumulator=0 output. This is used to execute the microinstruction SZA (skip on zero Accumulator).



EDIT: The forum software shrinks the (much larger than shown) image to fit on screen. You'll have to click the link below and download the file to view it at a readable scale.
 
 

[dfmischler]

I believe the way the original single accumulator DEC PDP-4, 7, 9, 15 machines handle operates is as follows: a combinatoric network detects skip conditions, and a multiplexer selects the input to the adder (which is only used to increment the accumulator during operate instructions).  The output of the adder enters the shifter.  This way the order of the functions is: skips, clears and complements, increment, then rotates.  So CLA CLL IAC RTL gives a constant result of 4.

The skips are performed on the original contents of the accumulator and link.  Note that these bits and their inverses are available (from the opposite transistors of each flip-flop).  SMA should skip if the high order bit of the accumulator is non-zero.  SZA can be tested by simply wire-anding the inverse of the accumulator bits together (diodes will do fine): if the result is zero then one of the bits in the accumulator is non-zero (so SZA should not skip).  SNL skips if the link is non-zero.

The CLA and CMA bits select one of 4 possible inputs to the adder: CLA=0 CMA=0 gives the accumulator bit; CLA=1 CMA=0 gives zero, CLA=0 CMA=1 gives the inverse of the accumulator bit, CLA=1 CMA=1 gives one.  The same thing is done for the link with the CLL and CML control bits.

The adder is fed the AC bits and a zero except that the IAC bit is used as the low-order bit (so 1 is added if IAC is set).

The shifter can perform one of five operations (six in late PDP-8's) based on the 3 control bits RAR RAL <rotate 2>.: pass-through (all 0), rotate right 1 bit (RAR=1, RAL=0, rotate 2=0), rotate right 2 bits (RAR=1, RAL=0, rotate 2=1), rotate left 1 bit (RAR=0, RAL=1, rotate 2=0), rotate left 2 bits (RAR=0, RAL=1, rotate 2=1).

The output of the shifter is clocked back into the accumulator at the end of the cycle.

[GK]

I believe the way the original single accumulator DEC PDP-4, 7, 9, 15 machines handle operates is as follows: a combinatoric network detects skip conditions, and a multiplexer selects the input to the adder (which is only used to increment the accumulator during operate instructions).  The output of the adder enters the shifter.  This way the order of the functions is: skips, clears and complements, increment, then rotates.  So CLA CLL IAC RTL gives a constant result of 4.

The skips are performed on the original contents of the accumulator and link.  Note that these bits and their inverses are available (from the opposite transistors of each flip-flop).  SMA should skip if the high order bit of the accumulator is non-zero.  SZA can be tested by simply wire-anding the inverse of the accumulator bits together (diodes will do fine): if the result is zero then one of the bits in the accumulator is non-zero (so SZA should not skip).  SNL skips if the link is non-zero.

The CLA and CMA bits select one of 4 possible inputs to the adder: CLA=0 CMA=0 gives the accumulator bit; CLA=1 CMA=0 gives zero, CLA=0 CMA=1 gives the inverse of the accumulator bit, CLA=1 CMA=1 gives one.  The same thing is done for the link with the CLL and CML control bits.

The adder is fed the AC bits and a zero except that the IAC bit is used as the low-order bit (so 1 is added if IAC is set).

The shifter can perform one of five operations (six in late PDP-8's) based on the 3 control bits RAR RAL <rotate 2>.: pass-through (all 0), rotate right 1 bit (RAR=1, RAL=0, rotate 2=0), rotate right 2 bits (RAR=1, RAL=0, rotate 2=1), rotate left 1 bit (RAR=0, RAL=1, rotate 2=0), rotate left 2 bits (RAR=0, RAL=1, rotate 2=1).

The output of the shifter is clocked back into the accumulator at the end of the cycle.

That's basically how my machine works / what I described. The only major exception is that I have a simplified/reduced microinstruction set which only includes two bit-shifting operations: RAR=1 - one bit right, RAL=1 - one bit left. RAR=1 & RAL=1 is invalid. If you want two bit shifts to the right you just have to program two RAR commands in succession.

[GK]

The skips are performed on the original contents of the accumulator and link.  Note that these bits and their inverses are available (from the opposite transistors of each flip-flop).  SMA should skip if the high order bit of the accumulator is non-zero.  SZA can be tested by simply wire-anding the inverse of the accumulator bits together (diodes will do fine):

Oh, BTW, well spotted. I should note that the simplified logic diagram I posted, while still showing the actual logical function, differs from the final design in that the inverses of the AC register outputs are not provided by 16 inverters (with their OC outputs OR-ed) as drawn. I simply used a single 16-input DTL NAND gate which performs an OR function with the NOTQ outputs of the flip-flops.

Since those familiar with the 6-gate master/slave DFF shown and with keen eyes might also notice that I appear to have the Q and NOTQ outputs mixed up, I should point out that this is account for the fact that the D-input steering gates are inverting. In my hand drawn logic diagram the D-input is shown as being active-low.

Four more days at work and then I'm free for 5 whole weeks - then I'll be able to apply myself to this project almost full time. I've already registered a domain name specifically for the projects write up / documentation / exposition. www.educ16.com (registered but not yet linked to a host).

EDUC16 = Educational micro computer, 16 bit ; to give due respect to the EDUC8 "Educate" discrete TTL logic computer project described in Electronics Australia magazine, which was mostly the inspiration for this design.


 

[GK]

Still loading and soldering bits for the remaining accumulator+link register cards, but in the meanwhile I have gotten the Program Counter register card loaded/tested/verified.

This unlike the AC+L, the 16-bit PC register only needs to be unidirectional (right-shift) and it has a parallel load function. The PC is parallel loaded from the Switch Register (the bank of 16 data-input toggle switches on the control panel).

I manged to fit four stages on a single card, so a total four of these cards make up the PC.

Here is the logical block diagram of the complete register:

https://www.eevblog.com/forum/projects/homebrew-digital-computer-system/?action=dlattach;attach=122053

Here is the schematic diagram:

https://www.eevblog.com/forum/projects/homebrew-digital-computer-system/?action=dlattach;attach=122054

After conducting a series of measurements with prototype discrete DFF's, I found it unnecessary to add the R-C delay networks (that I detailed earlier in this thread) to increase propagation from clock-in to Q-out. SPICE was overly optimistic in the estimation of the MPSH10-based gate turn off (output going high) time and the propagation delay through the DFF is more than long enough to avoid any synchronous clocking issues due to clock skew between cards.

Now I just have another 3 of these cards to etch and assemble and that will take care of the PC register. Here is the card under test, wired to a PIC microcontroller (and yes, the crystal oscillates fine on the breadboard without any additional parallel load capacitance):