How to alter the duty cycle of this SMPS?

[theleakydiode]

Well, looks like I've had a bit of success for once  . I inserted a 1k resistor between Q4 and R10, C7. That seems to "chop" off the dithering about at the start of the gate drive waveform and shift it back a little.

It does increase the switching frequency by a few khz and plays with the duty cycle a little (can't remember which way) but it could be worse I guess, I made sure it was below 50% just in case.

I also decreased the gate resistor to 300 ohm to speed up turn on, don't want to reduce it too much or else the losses in the pull up resistor will get silly.

Maybe if I reduce R7 and R10 I can get the frequency down a bit?

[T3sl4co1l]

Oh hey, you've managed to get class E operation. Don't touch it!

Tim

[theleakydiode]

Oh hey, you've managed to get class E operation. Don't touch it!

Tim

I know but I kind of need a lower frequency, the LOPT won't jump gap with it that high.

[xavier60]

That looks good. Increasing C7 should lengthen the on time. It will also delay the turn on time.

[xavier60]

Also if you look at the Gate waveform now, you will notice that the Miller Plateau at turn on has gone. MOSFETs turn on quicker when the Drain voltage is near Zero.
https://electronics.stackexchange.com/questions/66660/why-is-the-gate-charge-curve-miller-plateau-of-mosfets-dependent-on-vds

[T3sl4co1l]

How many turns are on that primary?

Tim

[theleakydiode]

That looks good. Increasing C7 should lengthen the on time. It will also delay the turn on time.

Anything after the new 1k resistor (now 910 ohm) has no effect on delaying the turn on cycle, adding a 470pF across C7 now results in a lower frequency (47khz) but a duty cycle of about 60% which is too high I think.

What would be the maximum duty cycle I could safely get away with? I blew Q4 a few days ago by accidentally making the duty cycle too high.

How many turns are on that primary?
Tim

8 wound around an exposed leg of the core of a CRT LOPT.

Hmm anyone know how I could reduce the frequency without upsetting the duty cycle? Also I'm guessing this is technically phase locked loop now as its the falling of the flyback pulse what triggers the turn off of the MOSFET.

[theleakydiode]

Also if you look at the Gate waveform now, you will notice that the Miller Plateau at turn on has gone. MOSFETs turn on quicker when the Drain voltage is near Zero.
https://electronics.stackexchange.com/questions/66660/why-is-the-gate-charge-curve-miller-plateau-of-mosfets-dependent-on-vds

Ah I was wondering about that! Thinking it had something to do with a capacitive divider somewhere as the middle part was always half the supply voltage.

Still need to get the frequency down really, its just too high for the LOPT.

[xavier60]

That looks good. Increasing C7 should lengthen the on time. It will also delay the turn on time.

Anything after the new 1k resistor (now 910 ohm) has no effect on delaying the turn on cycle, adding a 470pF across C7 now results in a lower frequency (47khz) but a duty cycle of about 60% which is too high I think.

What would be the maximum duty cycle I could safely get away with? I blew Q4 a few days ago by accidentally making the duty cycle too high.

How many turns are on that primary?
Tim

8 wound around an exposed leg of the core of a CRT LOPT.

Hmm anyone know how I could reduce the frequency without upsetting the duty cycle? Also I'm guessing this is technically phase locked loop now as its the falling of the flyback pulse what triggers the turn off of the MOSFET.

When you say that something has no effect on the delaying the turn on time, how are you observing this? After the flyback pulse has finished, the voltage will stay near zero, actually about 0.5V negative for some time on its own. The MOSFET can be turned on at any point during this time. There is some efficiency advantage in turning on the MOSFET just after the pulse is finished.
 Because the period on the flyback pulse is mostly fixed, you only have control of the ON part of the waveform, where the voltage is at zero. When you change this ON time, you can't help but alter the duty cycle and the repetition rate/frequency. 
 The duration of the flyback pulse can be altered by changing the LC resonant frequency, either changing the value of the flyback tuning capacitor, C3. Or by changing the number of turns. Reducing the value of C3 will shorten the pulse period and increase the peak voltage. Decreasing the turns will have the same affect plus the change in turns ratio to other windings which will increase the EHT voltage even further, but this risks saturating the core.
 

[theleakydiode]

That looks good. Increasing C7 should lengthen the on time. It will also delay the turn on time.

Anything after the new 1k resistor (now 910 ohm) has no effect on delaying the turn on cycle, adding a 470pF across C7 now results in a lower frequency (47khz) but a duty cycle of about 60% which is too high I think.

What would be the maximum duty cycle I could safely get away with? I blew Q4 a few days ago by accidentally making the duty cycle too high.

How many turns are on that primary?
Tim

8 wound around an exposed leg of the core of a CRT LOPT.

Hmm anyone know how I could reduce the frequency without upsetting the duty cycle? Also I'm guessing this is technically phase locked loop now as its the falling of the flyback pulse what triggers the turn off of the MOSFET.

When you say that something has no effect on the delaying the turn on time, how are you observing this? After the flyback pulse has finished, the voltage will stay near zero, actually about 0.5V negative for some time on its own. The MOSFET can be turned on at any point during this time. There is some efficiency advantage in turning on the MOSFET just after the pulse is finished.
 Because the period on the flyback pulse is mostly fixed, you only have control of the ON part of the waveform, where the voltage is at zero. When you change this ON time, you can't help but alter the duty cycle and the repetition rate/frequency. 
 The duration of the flyback pulse can be altered by changing the LC resonant frequency, either changing the value of the flyback tuning capacitor, C3. Or by changing the number of turns. Reducing the value of C3 will shorten the pulse period and increase the peak voltage. Decreasing the turns will have the same affect plus the change in turns ratio to other windings will increase the EHT voltage even further, but this risks saturating the core.

I mean the only thing I found that delays the point where the gate turns back on is the addition of the resistor, other things below it all change duty cycle and frequency but it seems I can't change one thing without messing up something else. I think the new resistor changes the divider on the base of Q5, hence why it seems a bit backwards at times.

Do you think 8 turns might be pushing it for 12v? I guess I could try a smaller LC capacitor but its only a 75v mosfet, avalanching may have saved it during the 90% duty cycle incident but I don't think its a good idea to run it near the maximum breakdown voltage. The required arc gap is only about half a centimeter so its not like I need 30kV like it originally gave in the CRT TV.

Does it act like a constant power load with the short (arc) on the output and fixed drive frequency and duty cycle?

[xavier60]

What does the transformer normally belong to?

[xavier60]

When a LOPT/EHT transformer is used in a TV there is a big difference. Most of the energy storage happens in the deflection yoke inductance. I could do some experiments here if it is a colour TV type EHT transformer.

[theleakydiode]

When a LOPT/EHT transformer is used in a TV there is a big difference. Most of the energy storage happens in the deflection yoke inductance. I could do some experiments here if it is a colour TV type EHT transformer.

Oh yes please, it is a colour TV type LOPT that's black and has the big red lead coming out the top.

So a solution could be adding a big inductor across the transistor? Any idea what kind of inductance the deflection yoke would have?

[T3sl4co1l]

What is your basis for wanting a lower frequency?

The FBT does not need to operate at 15.7kHz.  As mentioned before, the secondary is usually resonant at some harmonic thereof, convenient for refresh purposes.

If it's from a multisync computer monitor, the resonance will be even higher (thanks to some clever internal design!).

Lowering the frequency will only give you a thinner, weaker spark, assuming the coupling factor is good (which it isn't, in this configuration -- so it's hard to say which direction is best, aside from finding the nearest resonant harmonic).

I think it more likely you merely need to reduce the primary turns and/or increase supply voltage.  To keep the same waveform, of course, you need to increase the capacitor in parallel with the transistor, proportionally with the square of the ratio of turns (so, going from 8 to 4 --> ratio of 2^2 = 4, increase C by 4x) to keep the primary resonant frequency the same.

Tim

[xavier60]

There is no need for the extra inductor, the EHT transformer can store enough energy on its own, any more would destroy the EHT transformer sooner.
I did a mock up with 10 turns and a 0.22uF flyback tuning capacitor.  I drove an IRFP460 MOSFET with a signal generator which has frequency and duty cycle control.
The flyback pulse width was 10us, ideally should be 12.5us, but it's not critical. At 15Khz, the flyback peaked at 110V. I estimate the EHT at about 20KV.
Although varying the duty cycle over some range made no difference with the EHT unloaded, it makes a huge difference to the EHT output current and power draw when it's arcing.
 Because the EHT voltage is stored in capacitors built into the EHT transformer, the arcing is actually a series of high energy discharges. I don't think it would last long doing this.
 Be careful with test equipment when working with EHT. I used a X100 probe with my DS0 for extra protection. High voltage spikes can end up anywhere.

[theleakydiode]

What is your basis for wanting a lower frequency?

The FBT does not need to operate at 15.7kHz.  As mentioned before, the secondary is usually resonant at some harmonic thereof, convenient for refresh purposes.

If it's from a multisync computer monitor, the resonance will be even higher (thanks to some clever internal design!).

Lowering the frequency will only give you a thinner, weaker spark, assuming the coupling factor is good (which it isn't, in this configuration -- so it's hard to say which direction is best, aside from finding the nearest resonant harmonic).

I think it more likely you merely need to reduce the primary turns and/or increase supply voltage.  To keep the same waveform, of course, you need to increase the capacitor in parallel with the transistor, proportionally with the square of the ratio of turns (so, going from 8 to 4 --> ratio of 2^2 = 4, increase C by 4x) to keep the primary resonant frequency the same.

Tim

I've noticed the opposite, using a different driver with adjustable frequency and duty cycle I found that for a fixed duty cycle going lower in frequency allowed the secondary voltage to be much higher. With just 12v and a frequency in the hearing range I could get a continues arc that jumped a 7cm+ gap whilst at 24v it was well over 10cm but just made the LOPT flash over. The MOSFET was a 650v .03mohm type that could take some ridiculously high current, I made sure to keep the peak drain voltage below 500v as they were about £12 each!

I've also driven them in half-bridge too where resonance was used as a form of FM slope detection in combination with an audio signal injected into the RC timing section of the drive IC, it actually sounded pretty good and loud as a plasma speaker!

This was using LOPTs from CRT TV's, the PC monitor ones didn't work nearly as good and the massive internal capacitors would "snap" over if the voltage got too high. Internally what makes the monitor LOPTS different from the TV versions? Are they driven differently inside a monitor?

There is no need for the extra inductor, the EHT transformer can store enough energy on its own, any more would destroy the EHT transformer sooner.
I did a mock up with 10 turns and a 0.22uF flyback tuning capacitor.  I drove an IRFP460 MOSFET with a signal generator which has frequency and duty cycle control.
The flyback pulse width was 10us, ideally should be 12.5us, but it's not critical. At 15Khz, the flyback peaked at 110V. I estimate the EHT at about 20KV.
Although varying the duty cycle over some range made no difference with the EHT unloaded, it makes a huge difference to the EHT output current and power draw when it's arcing.
 Because the EHT voltage is stored in capacitors built into the EHT transformer, the arcing is actually a series of high energy discharges. I don't think it would last long doing this.
 Be careful with test equipment when working with EHT. I used a X100 probe with my DS0 for extra protection. High voltage spikes can end up anywhere.

Very nice! Was that LOPT out of a monitor or TV? What duty cycle would that 12.5us be at 15.7khz? Low I'm guessing.

Yeah I need to get some better probes, the ones that came with my DS1052E are falling apart and the 1x/10x switch is in a stupid place where you can easily switch it by mistake. I think mosfet breakdown voltages and avalanche capability's have saved my ass a couple times in the past 

What would be the maximum safe duty cycle in this circuit? At some point I guess the core is going to stop resetting.

[xavier60]

Very nice! Was that LOPT out of a monitor or TV? What duty cycle would that 12.5us be at 15.7khz? Low I'm guessing.

Yeah I need to get some better probes, the ones that came with my DS1052E are falling apart and the 1x/10x switch is in a stupid place where you can easily switch it by mistake. I think mosfet breakdown voltages and avalanche capability's have saved my ass a couple times in the past 

What would be the maximum safe duty cycle in this circuit? At some point I guess the core is going to stop resetting.

The one in the photo is from a small colour TV. It has built in rectifier diodes and filter capacitors.   It would never be able to produce a continuous arc, only a rapid series of high energy discharges, sounds like a loud buzz.
The duty cycle thing is getting tricky to explain. It will make more sense if you research how CRT horizontal deflection works. In TVs, the duty cycle of the drive to the Horizontal Output Transistor was simply set to 50% because the Collector voltage  stays low for the first half of the scan line anyway. The current flow gets reversed during the flyback pulse and actually flows back into the supply rail during the first half of the scan line.
 Ill take a photo of this happening in my mock up tomorrow.
 Older TVs had LOPTs that needed a separate rectifier block to rectify and filter the HV AC from the HV winding on the transformer. The HV AC would produce a continuous arc with a hissing sound.  I'm wondering was sort of LOPT you are using?

Extra: I'm starting to suspect that my transformer might be from a computer monitor after all. It was new in its box.  Ill try to find something else.
 

[theleakydiode]

It looks like this one (pic related). I did find the datasheet at one point and it had no internal capacitors, it came out of a colour TV.

I've also got a PC monitor LOPT and that has a big cylinder on the side containing a capacitor, that one doesn't work as well. Still haven't found an AC LOPT yet and CRTs are getting very hard to find around here. I think most people got rid of them years ago and the local recycling place doesn't let people take stuff.

Very nice! Was that LOPT out of a monitor or TV? What duty cycle would that 12.5us be at 15.7khz? Low I'm guessing.

Yeah I need to get some better probes, the ones that came with my DS1052E are falling apart and the 1x/10x switch is in a stupid place where you can easily switch it by mistake. I think mosfet breakdown voltages and avalanche capability's have saved my ass a couple times in the past 

What would be the maximum safe duty cycle in this circuit? At some point I guess the core is going to stop resetting.

Extra: I'm starting to suspect that my transformer might be from a computer monitor after all. It was new in its box.  Ill try to find something else.
 

Can I see the front side where the dials are and bottom pin arrangement? As I can normally tell where it came from, if its got a sticky out bit on the side and lots of extra pins on the bottom along the one side then its most likely from a monitor.

[T3sl4co1l]

I've noticed the opposite, using a different driver with adjustable frequency and duty cycle I found that for a fixed duty cycle going lower in frequency allowed the secondary voltage to be much higher. With just 12v and a frequency in the hearing range I could get a continues arc that jumped a 7cm+ gap whilst at 24v it was well over 10cm but just made the LOPT flash over. The MOSFET was a 650v .03mohm type that could take some ridiculously high current, I made sure to keep the peak drain voltage below 500v as they were about £12 each!

OK, so what you're seeing is most likely normal flyback behavior.

More on time --> more average current draw.  At constant D (and assuming saturation never occurs in the transformer), power output is inversely proportional to frequency.

The waveform likewise shows increasing peak voltage following turn-off (when current peaks), but since it's less frequent, it's not as powerful as it would be simply increasing D instead.

In class E, the peak voltage typically isn't too much greater than the supply voltage.  Ideally, you'd have fixed off-time and adjustable on-time, which has the effect of increasing D and decreasing F at the same time -- giving better control over the output. 

Primarily, though, you'd want to control a class E driver by varying its supply voltage.

Maybe you don't need/want an output that hot -- that's fine.  Then you need some way to adjust off-time much longer.  Which, you really need a different circuit for, it seems.

I've also driven them in half-bridge too where resonance was used as a form of FM slope detection in combination with an audio signal injected into the RC timing section of the drive IC, it actually sounded pretty good and loud as a plasma speaker!

This was using LOPTs from CRT TV's, the PC monitor ones didn't work nearly as good and the massive internal capacitors would "snap" over if the voltage got too high. Internally what makes the monitor LOPTS different from the TV versions? Are they driven differently inside a monitor?

Possibly a combination of lower voltage ratings, with high frequency construction.  Instead of one big winding (as the old CRT FBTs had), it's wound one layer at a time, with a HV diode per layer.  This is done so that each layer can have the same AC voltage along its length -- so that inter-layer capacitance doesn't pile up, severely limiting the self resonant frequency.

HV tracks tube size, usually, so a big (30"+) TV might use 30kV, while a 17" monitor might use only 20kV.

Tim

[theleakydiode]

I've noticed the opposite, using a different driver with adjustable frequency and duty cycle I found that for a fixed duty cycle going lower in frequency allowed the secondary voltage to be much higher. With just 12v and a frequency in the hearing range I could get a continues arc that jumped a 7cm+ gap whilst at 24v it was well over 10cm but just made the LOPT flash over. The MOSFET was a 650v .03mohm type that could take some ridiculously high current, I made sure to keep the peak drain voltage below 500v as they were about £12 each!

OK, so what you're seeing is most likely normal flyback behavior.

More on time --> more average current draw.  At constant D (and assuming saturation never occurs in the transformer), power output is inversely proportional to frequency.

The waveform likewise shows increasing peak voltage following turn-off (when current peaks), but since it's less frequent, it's not as powerful as it would be simply increasing D instead.

In class E, the peak voltage typically isn't too much greater than the supply voltage.  Ideally, you'd have fixed off-time and adjustable on-time, which has the effect of increasing D and decreasing F at the same time -- giving better control over the output. 

Primarily, though, you'd want to control a class E driver by varying its supply voltage.

Maybe you don't need/want an output that hot -- that's fine.  Then you need some way to adjust off-time much longer.  Which, you really need a different circuit for, it seems.

I've also driven them in half-bridge too where resonance was used as a form of FM slope detection in combination with an audio signal injected into the RC timing section of the drive IC, it actually sounded pretty good and loud as a plasma speaker!

This was using LOPTs from CRT TV's, the PC monitor ones didn't work nearly as good and the massive internal capacitors would "snap" over if the voltage got too high. Internally what makes the monitor LOPTS different from the TV versions? Are they driven differently inside a monitor?

Possibly a combination of lower voltage ratings, with high frequency construction.  Instead of one big winding (as the old CRT FBTs had), it's wound one layer at a time, with a HV diode per layer.  This is done so that each layer can have the same AC voltage along its length -- so that inter-layer capacitance doesn't pile up, severely limiting the self resonant frequency.

HV tracks tube size, usually, so a big (30"+) TV might use 30kV, while a 17" monitor might use only 20kV.

Tim

Yeah in this application a less intense arc is preferred as the electrodes are less than a centimeter apart and I don't want them overheating, I've been there done that got the tee-shirt with massive arcs and whilst its impressive there are limited applications for them. Biggest arc I ever drew was over 1ft long and just pure white hot plasma around 1 inch thick (ZVS driver 48v).

I guess in the case of the other circuit it would have been regular flyback mode since the capacitor across the primary wasn't fully resonant, it was just to keep the peak drain voltage down. First pic is the schematic if you want to try it, I just replaced the MOSFET with a higher voltage one and decreased the capacitor on the primary to allow moar output voltage (use high impedance RCD snubber to monitor peak drain voltage with an inexpensive voltmeter). I had to put a resistor in series with the gate resistor diode or else it wasn't stable.

The capacitor across the +35v needs to be low esr and very close to the top of the primary and low end of the current sense resistors since the peak current demands can get high, keep loop areas small.

Second one is the plasma speaker, use the "better output stage", put the output electrodes close so it doesn't flash-over unloaded and tune it using the frequency pot and at some point you'll hit resonance with the biggest output voltage (if your power supply can handle it). Tune it again with music playing to get the best sound (use an old phone/audio source just in case!).

I didn't design any of these circuits btw but have tested them both. Its easy to turn a DC LOPT into an AC one with this if the output voltage rises high enough, the internal diodes just short and you can end up measuring the secondary winding resistance with an ohm meter. Keep the gap in the core as it prevents saturation and stops the output diode from biasing the core. MOSFETs will run a bit hotter like this but its the price to pay for an open loop design.

The second one can have clear sound with careful electrode design, I found vertical with a point for the bottom and larger rounder surface for the top worked well and the arc was silent.

[T3sl4co1l]

Ooh, that first one is really nice: peak current mode operation, quasi-resonant snubber even.  Transistor is inappropriate for the driver (UC3844 can only deliver about 1A, IRFP260 has a fuckoff big gate; a modern equivalent with 1/3 or less Qg and the same Rds(on) would have much lower switching loss), probably hence the heatsink.  Then a smaller gate resistor (maybe 10 instead of 27 ohms) can be used.

The other one is pretty typical, but it doesn't have any protection, it's just a full wave AC source.

Tim

[theleakydiode]

Its the miller capacitance that messes with the first one once the drain starts swinging to a decent level, I've been experimenting with miller clamp gate drive IC's recently to go between the fet and PWM IC.

Problem is you need both a high voltage and low rdson fet which drives the parasitic capacitances of the device up.

What kind of protection would you put on the second one?

[xavier60]

What do the ultrafast diodes do in the UC3844 driven design?
I tried a few more of my transformers and all had capacitors inside. I took a photo of the voltage and current waveforms anyway with no load.
At the end of the line, the current reaches 10A. After flyback, the current flow is reversed and is a bit under 10A. The current crosses zero a bit before half way along the line.
 I didn't want to make any sparks while the DSO was connected. I figure that at 50% duty cycle, the final current will stay about the same at 10A when the EHT is loaded. With a higher duty cycle, the current would increase with load, and the possibility of saturation.
  No wonder why the rail bypass eletros have to be low ESR with +/- 10A flowing. I had to use 2 capacitors. One on its own got hot.

[theleakydiode]

Did you build the UC3844 circuit or is that using the signal generator? The diodes are part of a non dissipative LCD snubber and I don't think they actually see more than the supply voltage so no idea why the designer spec'd them at such a high voltage.

See method 3 https://www.daycounter.com/Calculators/Snubbers/Snubber-Design-Calculator.phtml

Is it safe to view the gate whilst arcs are being drawn? I've done it in the past and haven't have any problems yet.

Edit: I think these open loop drivers are constant power in a way with the energy being dissipated somehow or returned to the supply rails via the capacitor and mosfet body diode, the peak current limit on the UC3844 only kicks in once when the frequency is turned low enough as is (I personally think the sense resistor is too low). People used to run these things without any capacitor and that would avalanche the mosfet until it popped.

[xavier60]

Did you build the UC3844 circuit or is that using the signal generator? The diodes are part of a non dissipative LCD snubber and I don't think they actually see more than the supply voltage so no idea why the designer spec'd them at such a high voltage.

See method 3 https://www.daycounter.com/Calculators/Snubbers/Snubber-Design-Calculator.phtml

Is it safe to view the gate whilst arcs are being drawn? I've done it in the past and haven't have any problems yet.

No, I'm still using the signal generator.
 It possibly is safe to use a DSO while arcing. The main precautions would be to ground the probe close to where the measurement is being taken. The arc current path should be as direct as possible and avoid being shared with other circuitry. You are likely to be already taking these precautions if you have had no trouble.
 I always put a 15V zenner between Gate and Source of MOSFETs  when experimenting.