I should know this but..

[tron9000]

I'm building a constant current source and am trying to figure out exactly what its maximum ratings are:

http://tron9000.blogspot.co.uk/2015/05/current-source-update.html

so I've worked out if i use 4x FDP6670 in parallel (unlike the 2 in the schema in the link above) and bolt it to a heatsink I'm thinking of buying, I can put out a maximum of 38.9W ~ 40W if I'm cheeky and have fan going, in the MOSFET's.

I'm using a 1R 25W aluminium clad resistor bolted to the enclosure as the shunt (out on J1-2 & J1-3) which means I can pass 5A through it.

the FDP6670AL can take a maximum V_DS is 30Vdc and a max I_D of 80A!  - https://www.fairchildsemi.com/datasheets/FD/FDP6670AL.pdf

The reason is that I have loads of these FETS floating around, so I thought I'd put them to good use!

SO the max ratings of my design (using 4x FDP6670) is:

30V_max, 5A_max, 65W

correct? I feel a bit daft for asking but a different set of eyes on it might call out a stupid mistake.

[dom0]

Paralleling MOSFETs in the linear region with no source resistance will result very quickly in magic smoke.

Also, note that you'll need higher resistance on the source than with comparable BJTs.

Also, driving the FET gates with >1 k? series resistance and 1 µF(!!) gate capacitance will result in pretty crappy transient behaviour, if not outright instability (just think about the phase shift this RC element introduces into your control loop).

Edit: Actually I'm surprised that this is stable ... uh, you did check with a scope, right? Or only DC measurements? The latter usually don't show oscillations, unless the loop breaks completely.

[tron9000]

ahh so i have overlooked something.

Unfortunately I've only done the latter (using a DMM) actually I did use a scope and that's why I put in the RC network due to ripple on the U1:A output, I didn't observe transient behaviour though, like I said: fresh set of eyes!

However I used a ammeter in series with one of the FETS on the breadboard and did observe this "unbalancing" effect: the current through the FET started to decrease and the other FET got more hot. I just put this down to the series resistance of the meter, but doing a quick google search on balanced MOSFET circuits, its starting to look like I've wandered into a mine-field!

I've basically taken this design and am attempting to beef it out to try and at least reach my spec: http://paulorenato.com/joomla/index.php?option=com_content&view=article&id=91:constant-current-load&catid=4:projects&Itemid=4

but achieving my spec of 7A is looking out of reach with the components I have.

[dom0]

The linked schematic exhibits certain properties that are reminiscent of "yeah it kinda works but not well and it can't do what the specs say"-class designs.

So, for example, the construction with resistance on the FET gates inside the loop can work, yes, but needs heavy compensation (C5) to be stable. Dynamic performance suffers accordingly.
The better way around this is to reduce the output resistance of the OP (i.e. a buffer, a simple complementary emitter follower will do), which makes the phase shift introduced by the output resistance and the gate capacitance smaller.

but achieving my spec of 7A is looking out of reach with the components I have.

Absolutely not: You just won't get 7 A at 30 V out of them. But there's no issue really with higher currents at lower voltages. Of course, 80 Amps are quite impossible at any voltage, with these FETs.

This is the reason why electronic loads are usually specified with voltage, current and power: it says "you can do XX Volts, max, and XX Amps, max, but you may not exceed XX Watts in doing so".

[tron9000]

The linked schematic exhibits certain properties that are reminiscent of "yeah it kinda works but not well and it can't do what the specs say"-class designs.

So, for example, the construction with resistance on the FET gates inside the loop can work, yes, but needs heavy compensation (C5) to be stable. Dynamic performance suffers accordingly.
The better way around this is to reduce the output resistance of the OP (i.e. a buffer, a simple complementary emitter follower will do), which makes the phase shift introduced by the output resistance and the gate capacitance smaller.

but achieving my spec of 7A is looking out of reach with the components I have.

Absolutely not: You just won't get 7 A at 30 V out of them. But there's no issue really with higher currents at lower voltages. Of course, 80 Amps are quite impossible at any voltage, with these FETs.

This is the reason why electronic loads are usually specified with voltage, current and power: it says "you can do XX Volts, max, and XX Amps, max, but you may not exceed XX Watts in doing so".

Thanks dom0, been a help!

Just to clarify when you say reduce the output resistance of the op, do you mean op amp?

Yes, considering this is my first cc source project, I'm coming to terms with some limitations to what I can design, whilst remaining within my original goal, so far I've spent £5 on parts!

You have confirmed for me how to describe my designs rating.

Lol, I'd never expect these FETS to sink 80A! Love to see one try! Destruction video?

So 2 things to research & test: parallel fet balancing and observing the effects of reducing the output impedance of the op-amp (if that's what you mean)

[dom0]

Just to clarify when you say reduce the output resistance of the op, do you mean op amp?

Yep

[hlavac]

Paralleling MOSFETs in the linear region with no source resistance will result very quickly in magic smoke.

You are probably thinking of BJT thermal runaway, MOSFETs parallel just fine.

[Marco]

It's not likely but if one has minimum Vgs-threshold and the others all have max it's gonna burn.

Current sharing is going to be pathetic regardless.

[SeanB]

MOSFET's parallel nicely when switched hard, but they still need ballasting resistors for linear use, as they do have modes which are going to lead to thermal runaway.

[dom0]

MOSFET's parallel nicely when switched hard, but they still need ballasting resistors for linear use, as they do have modes which are going to lead to thermal runaway.

Precisely, MOSFETs only exhibit a positive RDSon tempco in the saturated region. In the linear region they suffer the same negative tempco just like BJTs.

MOSFETs also have something called the Spirito effect, which could be compared to the second breakdown of BJTs. The difference here is that both concern the current sharing in one device, while the main issue here is current sharing between devices. (Although one could argue that they are very similar, especially for MOSFETs, since all power FETs are constructed from a number of smaller FET cells).

[DanielS]

You are probably thinking of BJT thermal runaway, MOSFETs parallel just fine.

Rds has a positive temperature coefficient but Vgs has a negative coefficient, so a significant nominal or tempco mismatch between FETs may cause magic smoke. Adding a small current-sharing resistor to provide negative feedback on Vgs reduces sensitivity to these mismatches and drift. The larger the source load-balancing resistor, the more even the balancing will be, so you want to use the largest value your design can accommodate.

[tron9000]

oops have I started something?

just a thought, I have more than enough LM324's, so what's to say I could just have an op-amp for each FET?

[DanielS]

just a thought, I have more than enough LM324's, so what's to say I could just have an op-amp for each FET?

While having individual control loops and sense resistors for each FET would be ideal, the LM324 has horrible offset voltage and current drift. If you want to go down this route, you may want to pick more stable opamps. I tried putting together a simple differential amplifier using a LM324 and had to re-zero the DC offset before nearly every measurement.

[tron9000]

http://www.irf.com/technical-info/appnotes/an-941.pdf

breifly:
It states that

The device with the lowest on-resistance will carry the highest current. The positive temperature coefficient of the on-resistance tends to compensate this unbalance and equalize the currents.

so that's interesting...

scrolling down to page 10:

• use individual gate resistors - check
• ensure devices have tight thermal coupling- intending to use a strip of thermal padding and in the configuration in figure 2A
• Equalize common source inductance and reduce it to a value  that does not greatly impact the total switching losses at the frequency of operation - erm keep traces as short as possible to reduce inductance?
• Reduce stray inductance to values that give acceptable overshoots at the maximum operating current. - as above
• Ensure the gate of the MOSFET is looking into a stiff (voltage) source with as little impedance as practical - so as dan0 said low output impedance from op-amp, emitter follower.
• Capacitors in gate drive circuits slow down switching,thereby increasing the switching unbalance between devices and may cause oscillations - right well mine are coming out anyway
• Stray components are minimized by a tight layout and equalized by symmetrical position of components and routing of  connections - so long as everything is routed sensible this should also help

just a thought, I have more than enough LM324's, so what's to say I could just have an op-amp for each FET?

While having individual control loops and sense resistors for each FET would be ideal, the LM324 has horrible offset voltage and current drift. If you want to go down this route, you may want to pick more stable opamps. I tried putting together a simple differential amplifier using a LM324 and had to re-zero the DC offset before nearly every measurement.

LT1014? would that be better? I think I have one in my parts box.

[dom0]

When people talk about switching and conduction losses it ain't about linear / ohmic mode operation of FETs.

--

What I did last time was a 5532 for every BJT (didn't use FETs) + sense pair and a 442 (or 412, can't remember) and his own (summed) shunt closing a control loop around the couple 5532's and their FETs. Worked very well. Was cheap.
Could be done better (e.g. differential sum of all the individual sense resistors instead of an additional sense resistor).

[DanielS]

LT1014? would that be better? I think I have one in my parts box.

Yes, much lower drift so once you are done adjusting them, you won't have to worry as much about that.

[Siwastaja]

http://www.irf.com/technical-info/appnotes/an-941.pdf

breifly:
It states that

The device with the lowest on-resistance will carry the highest current. The positive temperature coefficient of the on-resistance tends to compensate this unbalance and equalize the currents.

so that's interesting...

scrolling down to page 10:

No no no! Forget the document; it only discusses paralleling switching mosfets (most common case today); your case of linear operation is completely different, as already stated by others multiple times.

To rephrase, the control (gate) voltage is not simple: the individual FETs have different gate voltage characteristics, and temperature affects it in the non-desired way. In switching, the problems are avoided by quickly using extreme enough gate voltages so that all FETs are either fully on or fully off (with several volts of headroom), regardless of differences.

Rds(on) only states the resistance of a FET that is fully on.

[tron9000]

of course, why does that fact keep escaping me!

[tron9000]

http://www.ixys.com/Documents/Articles/Article_Linear_Power_MOSFETs.pdf

i believe this is more relevant?

[tron9000]

Sorry for the triple post; but I've done some research on this and I'd like to share:
http://tron9000.blogspot.co.uk/2015/07/constant-current-source-back-to-drawing.html

comments are always welcome. Many thanks!

[dom0]

So why does this work - well I haven't done much research, but it looks like larger current gain by employing Q3, essentially making Q1 & Q3 a hybrid BJT-FET Darlington pair.

If I remember my control systems correctly, larger gain = faster response/sensitivity (https://en.wikipedia.org/wiki/Control_system#Proportional_control - paragraph 2) - which rings true with the vastly improved overshoot we see.

Not quite. Since this is a system with voltage feedback the additional current gain does not contribute to loop gain. Instead it reduces the phase shift in the control loop, because the emitter follower (although a push-pull /complementary follower will likely work even better) has a lower output resistance than the op amp. This output resistance forms the usual 1st order RC low-pass with the gate capacitance (caution: non-linear), which introduces phase shift. Lower resistance => lower phase shift => better loop response / larger phase margin / larger gain margin / better stability.

[tron9000]

ahh of course, that makes more sense now.

I'm assuming then if I did use a push-pull stage, I would need to have a split rail supply for the op-amp?

[dom0]

Single supply case: depends on the Ids of your FETs with ~.7 V Vgs. The op will also saturate it's output (depending on the DS channel leakage he might already do that anyway), which is likely not good for transient response, especially the transient response of the rising edge out of saturation will be rather sluggish.