LT1619 SMPS controller - Vc Help?

[Poe]

I'm trying to incorporate the Linear Tech 1619 PWM controller in a boost SMPS.
http://cds.linear.com/docs/Datasheet/1619fa.pdf
Unfortunately I do not fully understanding the RC network attached to the 'compensation pin' (Vc) of the Error Amplifier. 

The datasheet appears to be completely missing information on this topic.  For some reason, it quickly skims over this (IMHO complicated) detail while posting a formula and circuit to calculate Rsense!

Their "Typical Application" circuits not only have wildly different values for this RC network but also different connections. 

Could anyone shed some light on choosing the correct connections and/or calculating the correct values for my circuit?

Thank you.

[PSR B1257]

The datasheet appears to be completely missing information on this topic.

See page 5: Pin functions

VC (Pin 3): Compensation Pin for the Error Amplifier. VC is
the output of the transconductance amplifier. Overall loop
is compensated with an RC network from this pin to the
ground.

[AndyC_772]

You're in good company, and you're quite right - most data sheets completely gloss over this essential information.

The problem is that calculating the correct values for these components is very complicated, and depends a lot on the load, the output capacitance, the switching frequency and other parameters. There's no 'right' answer either, just trade-offs between stability, complexity and transient response.

Since you're using an LT part I'd highly recommend downloading and using LTSpice to simulate your design, and you can see the effect of various compensation components for yourself. Expect quite a bit of trial and error. Experiment with varying each part individually and see what effect it has on the stability of the circuit; once it's stable under all input voltage and load conditions then check the transient response.

If you find a quick way to get it "right" then do please let me know - but I normally start with an educated guess and then keep running simulations until I know the supply will be stable.

Then expect to have to change your values when you actually build the circuit, because no simulation is going to be 100% accurate!

[Poe]

Thanks Andy. 

That's what I was afraid of.   

Just the thought of trial and error (in regards to stability) gives me goose-bumps.  This is for a commercial product so I need some degree of assurance. 

I didn't even think of LTSpice.  Thanks for that.

It's a shame there's not an easy way to calculate these values.  If I find one I'll be sure to post it.

[AndyC_772]

Once you've discovered LTSpice, the long winter evenings will just fly by....

[Poe]

So we finally got back to this project.  I used LTSpice for the loop compensation values, then cut a board. 

Unfortunately I discovered around 300uS after enabling the LT1619, it starts to drive the gate at ~2MHz (~50% DC).  Because of this HF oscillation it takes ~10 seconds for the output voltage to rise up to acceptable levels.  At this point, the system goes into burst mode operation and operates fine (no load).  The slightest load causes the gate drive to once again oscillate.

Based on the block diagram, it couldn't be the ramp compensation or switch current limit because they are tied into an SR latch.  If they trigger prematurely, the cycle remains at 300KHz. 

That leaves only the Under Voltage LockOut or Burst Mode comparator or Vc itself causing an issue.  I placed a 1uF cerm cap directly across the IC pins.  The board layout is almost identical to the recommended layout in Figure 14 of the datasheet.  Since the device operates fine in burst mode, I can only suspect Vc?

Has anyone experienced this before? 

[jeroen74]

Some datasheets have a more thorough explanation about its function, or how to find optimal values. For example the LTC3530 and design note 186.

In nutshell, the capacitor determines how long it takes to return to the correct voltage after a disturbance (load transient), and the resistor how much it deviates from the correct voltages. Could be the other way around

Have you looked at Vc with a scope? It should stay at a certain voltage with a constant load. Have you tried filtering the Rsense?

[Poe]

Thank you.  I'll look into that. 

The Vc line gradually ramps up during start-up.  Once it gets to almost 1V, that's when it oscillates the gate.  As I increase load from Mohm to Kohm, the Vc gradually increases from 0.7V to 1V.  Once again the gate starts to oscillate.

I have tried a large range of values at Vc with really no effect other than how long before it happens.  I have tried replacing all the parts for new as well.

When I tried to attach various Rsense low pass filters, the only thing that happened was that the circuit no longer went into burst mode (as it should) and the Vc level increased (as it should).  The Vc level exceeded the 3V listed as the maximum and I was uncertain if I damaged the part, so I eliminated the filter and replaced the IC.

It's quite odd.  Purely based on the block diagram only the UVLO and Burst Mode Comparator have the ability to toggle the gate at frequencies above 300KHz.  Although Vin is rock solid at 4V and it only works during Burst Mode.

[megajocke]

Could it be decoupling/input bus filtering that is inadequate, with the circuit disturbing itself through the sync or power supply input?

[Poe]

Could it be decoupling/input bus filtering that is inadequate, with the circuit disturbing itself through the sync or power supply input?

Found it.

Turned out to be the "S/S" line and a rise-time issue.  "Table 1" in the datasheet lists acceptable rise times.  When my gate capacitance was being (dis)charged, there was a 0.2V, 10nS transient on the S/S line.  This was enough to cause a re-sync event.  I placed a one ohm resistor in-line with my gate to reduce the current pulse from 5A to 1A.  Next board layout, I think I'll also add a ~1k resistor between the uP's I/O line and this S/S line .. maybe improve the layout if possible..