Inverter/Buffer Tri-state?

[David Chamberlain]

Hi, New here.. love the videos on You Tube.

Just wondering if any one can assist in finding a part.

A chip with a single buffer and inverter with tri-state (Enable on both outputs) like this

http://www.nxp.com/documents/data_sheet/74AUP2G3404.pdf

I have come up with a solution using the below single inverter and double buffer + some diode logic on the outside but would prefer a single chip solution.

http://www.nxp.com/documents/data_sheet/74AUP3G3404.pdf

The problem is given be the following truth table.

A/B   En   Out A    Out B
0       0       0           0
1       0       0           0
0       1       1           0
1       1       0           1

The goal is to enforce a rule in hardware that only one chip is selected or the other but never both and with the ability to disable all.

Thanks

[macboy]

Back to basics. 7400 (74HC00, 74LS00, 74ACT00, etc.), quad 2-input NAND. The NAND gate is a great building block because it combines two inputs and inverts, giving lots of flexibility. You can realize any combinational logic using only NAND gates.

Edit: just noticed that my A and B may be reversed compared to yours.

[T3sl4co1l]

Did you mean the disabled states to be "Z" instead?

Rather than strict boolean logic, circuits are typically designed with "strength" levels.  The IEEE 1164?? standard has six states, if I remember right: X (don't care, can be synthesized to any of the others without concern), Z (undriven, floating, high impedance/Z), H/L (weak pull up/down) and 1/0 (hard pull up/down).

The reason for this is conflict resolution.  Two outputs should never drive a common bus at the same time, at the same drive strength.  Thus 1/0 at the same time is a conflict, or H/L at the same time is a conflict.  But 1/0 dominates over H/L, which dominates over Z.

For example, a wired-AND circuit consisting of a passive pull-up and open-collector drivers (e.g., I2C bus) can be described as default 'H' (the passive pull-up), and active '0' (when any one or more drivers asserts the line).  The drivers, in turn, are default 'Z' (open circuit), active '0'.  The default-high state arises because 'H' is stronger than 'Z', and the active-low state arises because '0' is stronger than 'H'.

Tim

[macboy]

Did you mean the disabled states to be "Z" instead?
...

The OP mentions "tri-state" but in reading the problem description, I don't think that this is really what he wants. My interpretation of the problem is that he wants an Enable line that, when LO, will enforce that both chip select outputs (A and B) are LO, regardless of the A/B input. I don't think you'd ever want to actually tri-state the signal driving a chip select!

[T3sl4co1l]

Yes, confusing.

And to throw another on the fire...aren't most CS pins active low?

The usual way to implement decoder/enable logic is with a N-to-2^N decoder/selector chip.  The 74HC138 is a 3-to-8 line decoder, active low outputs.  The '238 is active high.  '154 is 4-to-16 line.  All of these come with one or more enable pins, so you can mix and match whatever logic control you need.  But their outputs will never go tristate, so be careful what you mean by "enable"..

Tim

[Kalvin]

Dual 4-to-1 analog multiplexer would also be one solution. It would provide the HI-Z possibility as well. 

[macboy]

Yes, confusing.

And to throw another on the fire...aren't most CS pins active low?
...

Now, that would be a /CS pin, not a CS pin, right 
Anyway, the circuit I gave realizes the truth table given by the OP. If the CS lines are indeed active low, then the two NAND gates wired as inverters can be removed from the circuit.

[SL4P]

Let's throw the option of 'OPEN COLLECTOR' / 'OPEN-DRAIN'  in there as well - to create a minimal tri-state output capability.

[David Chamberlain]

Hi all.

Macboy is spot on. Appologies I did not include all the details that would have avoided confusion.

The reason I want TRI-STATE is I will have appropriate pull up or down resistors on the outputs

Yes I will be using several of the same chip to drive pairs of chips with CS active high and active low.

I understand that it can be solved with nands and while that may still be a single chip solution it would have a larger foot print then the ones I linked to and require a rewire depending on the CS logic.

At any rate if no one has seen a single chip JUST LIKE the ones linked to then the NAND solution is the best presented .. Thanks Macboy.

[ajb]

The tristate requirement narrows your options considerably.  Can you do without it as long as the CS lines are driven to the appropriate levels?  If so you can probably do what you want with a three-input configurable logic gate.  There are about four standard configurations, one of them should be able to  give you the behavior you need.