This is about using 68010 in an otherwise 3.3V LVCMOS board without breaking compatibility with 68HC000. 68010 is a 5V NMOS chip that has LSTTL logic levels, and 68HC000 has 5V CMOS logic levels. Also I want to retain the signal I/O type while level translating from 5V LSTTL to 3.3V LVCMOS - when the CPU tristated the 3.3V dude get tristated for example.
SN74ALVC164245 is so far the only logic level shifter that, on the B side, has 5V LSTTL-compatible input logic levels and outputs 5V CMOS levels. (A side is 3.3V LVCMOS.) For most of the outputs (everything that would be tristated on either HOLD or bus yield) and the bidirectional data bus I have implemented the logic level shifting using three SN74ALVC164245. The input signals of the CPU can use 5V CMOS levels so I used a SN74LVC8T245 for that. Now I have four remaining signals: nRESET, nHOLD, nBG and E. nRESET and nHOLD are both open drain signals, while nBG and E are both outputs from the CPU not subjected to bus release control.
The original plan was to use TXB0104, two channels for the open drain since that chip is automatic bidirectional, and two channels just to bring out the two outputs. However there is a problem for that: TXB0104 has a 3.5V VIH while 68010 has a VOH capped at 2.4V. I can use 74HCT2G04 in the 5V zone to level shift the two output-only LSTTL signals to 5V CMOS, bring it into the 3.3V zone and invert it back using 74HC00 (two gates, the other gates are used to recreate the tristate control for the level translators) but that is hardly an elegant solution, and it does not handle the logic level problem with the two remaining lines at all.
Do you have any suggestions? Is there a two-channel or four-channel version of that LSTTL-compatible CMOS level shifter?