Jow jitter clock multiplication/division

[AlessandroAU]

I have a project where I am doing a digital down-conversion of a modulated signal at around 200 kHz.

The signal is generated by a Rigol DG1032Z and sampled by an AD7760 (24bit 2.5MSPS ADC), now the problem is there is clock drift between the two devices so when I do a digital zero-IF down conversion the the carrier from the signal generator does not quite match the IF freq.

So I guess the solution would be to have a common clock reference for both devices?

Now the AD7760 has a 40MHz reference OSC and the signal gen has a standard 10MHz reference input, so either I take the 40MHz and divide it down to 10MHz or have an external 10MHz reference which is then multiplied by 4.

Now, I would assume that phase jitter is going to be a big problem, I need all of the bits I can get out of my ADC and the stock OSC is spec'd to 0.7 ps RMS phase jitter (MXO45).

I assume using some flip-flops to divide the 40MHz by 4 would not give adequate performance?

Does anyone have any suggestions?



 

[David Hess]

The Rigol DG1032Z almost certainly phase locks to the external reference so its high frequency jitter is determined by its internal oscillator and there is nothing to be done about that.

If CMOS logic is used to divide, then all that is likely to be required is a clean and low impedance ground and power to prevent ground and power bounce.  If TTL is used to divide, then pattern dependent jitter would be a problem unless special precautions were taken with the power and ground.

One trick which I doubt you will need with CMOS is to reclock the output of the divider with the high frequency clock which removes all of the jitter from the divider; that leaves just one D flip-flop worth of jitter.  Just keep any power supply modulation from the divider out of the reclocking flip-flop.

Differential logic like ECL avoids the power supply modulation issues because the switching threshold is independent of the power and ground.

[AlessandroAU]

Thanks for the reply David,

So, in your opinion it would be completely fine to take the 40MHz and divide it down to 4 with some CMOS flip flops like this one http://www.ti.com/lit/ds/symlink/cd74hct74.pdf and feed it into the DG1032Z?

With regards to proper grounding, what if I took the output of the divider circuit and passed it through a 1:1 isolation transformer before sending to the DG1032Z, would that be acceptable?

Thanks for the help, this is not my area of expertise.

[coppercone2]

there are division chips that may offer better performance

i think they are called prescalers or something

ti has some that are pin set

[David Hess]

So, in your opinion it would be completely fine to take the 40MHz and divide it down to 4 with some CMOS flip flops like this one http://www.ti.com/lit/ds/symlink/cd74hct74.pdf and feed it into the DG1032Z?

It will be fine as long as you take some precautions.  See below.

With regards to proper grounding, what if I took the output of the divider circuit and passed it through a 1:1 isolation transformer before sending to the DG1032Z, would that be acceptable?

That is not a bad idea but what I was getting at is that changes in the ground and supply potentials at the logic IC causes changes in the switching thresholds which causes jitter.  So the logic IC needs to have low impedances at these points which generally means ground plain construction with plenty of high frequency decoupling.

It is not a big task.  Mount the 74HCT74 over a ground plane and thoroughly decouple it.

[Benta]

At 0.7 ps jitter spec, you're going to need something a h*ll of a lot faster than HCMOS.
Knowing your supply voltage and signal level would help a lot.

[coppercone2]

they have RF chips from hittite that do this but their real small expensive and I think too fast.

[AlessandroAU]

Thanks for the clarification David

@Benta, I'm not sure how 'read' jitter spec, is this OSC particularly good?


https://www.ctscorp.com/wp-content/uploads/MXO45.pdf