Loop stability in a boost/buck converter LM5175 design

[rx8pilot]

I have designed a test circuit for the TI LM5175 boost/buck conttroller for a VIN 10-35 / VOUT 16.5V-10A application. I referred to the eval design, Webbench, and of course the datasheet to get started. The circuit runs, but is unstable. I can operate it at about 5A steady state but it loses control as I go higher current. Changes to VIN can also disturb the stability. When running it is reasonably quiet and just a pinch under 98% efficient - very similar to the calculated performance.

I examined the loop gain/phase manually with a scope and injection transformer and see that the gain passes below 0db at about 700hz (I was expecting 4-6Khz or so) and the phase margin is very low - around 15-20 degrees. I started with the datasheet calculated slope and comp values and adjusted/measured to see if I could experimentally push it in a better direction. The various changes did not have much impact. The loop gain drops with frequency as expected, but it starts so low that it drops out of measurment range rather quikly as frequency is increase.

I measured with VIN=14v and VIN=22v with Iout=1 to 3A.

Schematically, it is nearly identical to the TI evaluation board and the layout is also very similar. I have reviewed the schematic and layout for a couple of days looking for simple mistakes, but have not yet found anything that seems like it would be a problem for loop gain/phase/stability. Since I have not seen a considerable change after adjusting SLOPE and COMP - I am guessing I may have some other contributing factor.


Not sure where to look next. Any ideas what mistakes would cause the loop gain to plummet?

[dmills]

I am just a little suspicious of C3 being so very much smaller then C4, are you sure C4 was not supposed to be 3n3 or so?

Other then that, layout!

Regards, Dan.

[rx8pilot]

Some layout reference images as well......

Power components on one side, control on the other.
4 layer, 2oz Cu.

[rx8pilot]

I am just a little suspicious of C3 being so very much smaller then C4, are you sure C4 was not supposed to be 3n3 or so?

Other then that, layout!

Regards, Dan.

Good question - the documentation only provides a modest description of that.
Suppressing SW noise.

[dmills]

High frequency loop area on the Vout side is **NASTY** being as the HF decoupling caps have now way to get back to the power ground plane without going half way across the board...

Add some stitching vias next to each of those caps.

Also, not sure I would have routed anything directly under the inductor, those flat wire things are not that well screened.

Ah, I figured it to be the other cap of a lead/lag compensator?

Regards, Dan.

[rx8pilot]

High frequency loop area on the Vout side is **NASTY** being as the HF decoupling caps have now way to get back to the power ground plane without going half way across the board...

Add some stitching vias next to each of those caps.

Also, not sure I would have routed anything directly under the inductor, those flat wire things are not that well screened.

Ah, I figured it to be the other cap of a lead/lag compensator?

Regards, Dan.

The pads have a 12ga solid Cu wire tying them together in lieu of vias, image attached. Perhaps not ideal, but does not seem bad enough to crater stability. 

There is a ground plane between the inductor and the gate traces. The unductor is sheilded as well. Maybe that is still not enough. Even if there was some unintended coupling, I am not sure why the loop gain would drop so dramatically. I am definitely NOT a control system expert either, but I would think that the gain/frequency relationship would be defined by the loop design and not impacted by noise on the gate drive traces.


EDIT: Nevermind.....the gate drive traces are indeed on the bottom layer under the inductor.

[rx8pilot]

Perhaps noise on the FB pin would cause the gain to be reduced?

EDIT: Yes, this appears to be a problem. I added a 200pf cap on the FB pin and the loop gain is much closer to what I would expect, probably too high. I am going to  calculate a more appropriate value to see if it will overcome the layout issues.

[rfbroadband]

most likely layout. Download this appnote form Linear Tech on layout strategies for switching regulators.
Identify the 'hot loop' of your circuit (topology) and apply what is described in this appnote to your circuit and layout.

http://www.analog.com/media/en/technical-documentation/application-notes/an139f.pdf?Domain=www.linear.com.cn
 

[Siwastaja]

The ground loop you already realized yourself is definitely bad. Definitely add those GND vias, right next to the ceramic caps, 2-3 vias per cap if possible.

For manufacturability / reliability, you should add thermal reliefs to the ceramic cap GND pads; most ceramic cap appnotes absolutely require this, although with experience, and a preheated board, it's possible to handsolder them properly without applying too much heat/stress, but it's still a risk. (I have had an MLCC failure after 1000 hours of operation in exactly this case, no thermal reliefs, too much stress while manually soldering all the caps to the shared big plane!) I know, it makes inductance a bit worse, but with the vias close, it's still much better to what you have now.

Is this a 2-layer design? 4-layer would provide you a solid ground plane, your caps would all have solid low-inductance connection easily. I'd not do a design like this on 2 layers. I guess this doens't need to be optimized to the last cent? 4-layer is not that expensive nowadays.

[rx8pilot]

It is a 4 layer design with a solid power ground plane for the high di/dt section and an island ground plane for the analog control - connected at a single point.

The original design used blind/buried vias but the cost skyrocketed and I wanted to shake down the circuit before bothering with a very expensive PCB. That is when I decided to make the compromise to use a wire bus to provide a path for the capacitors. Standard through vias would run into the MOSFETS underneath and it was easier to 'fix it' with a wire (riunnung our of time to move parts around). I think a production approach will be useing a 4 layer PCB for control and stacking that on a totally seperate 2 layer heavy copper board with the power stage. That approach is lower cost than the blind/buried via appraoch. In the end - size is the driving factor over cost. The final solution needs to be small in the end.

For manufacturability / reliability, you should add thermal reliefs to the ceramic cap GND pads; most ceramic cap appnotes absolutely require this, although with experience, and a preheated board, it's possible to handsolder them properly without applying too much heat/stress, but it's still a risk. (I have had an MLCC failure after 1000 hours of operation in exactly this case, no thermal reliefs, too much stress while manually soldering all the caps to the shared big plane!) I know, it makes inductance a bit worse, but with the vias close, it's still much better to what you have now.

I have read and observed the opposite in SMPS layouts to avoid the inductance penalty. The soldering is definitely more challenging, but I have a nice JEM310 convection oven for the primary build and hot air for changes/re-work. In the end, I only need this board to provide a design education over a short period of time - longevity is not important. I will likley over load it to death before the caps have a soldering related destruction.

So, going back a few steps.....

Are the caps the only significant issue in the power stage? I am still looking at control issues and trying to figure out if I just need to optimize component values or if there is a more fundemental issue. I single control loop that covers such a wide range seems to make it quite sensitive relative to a simpler boost only or buck only design.

[dmills]

I am not sure that placing the chip and all of its related small signal stuff right under the inductor rates as a particularly sane choice, but I would bet that stray inductance is the elephant in the room here.

Does the (Particularly) low side current sense resistor need to be so physically huge? It will not exactly be helping matters. 

There are generally good layout guidance in the datasheets.

This is not a place for HDI design, that gets stupid expensive, and yea thermals on the MLCCs if you want reliability, a 4 spoke thermal adds little inductance and makes both soldering easier and reduces thermal stresses on the part in operation (Fixing two corners of a ceramic chip to a heatsink then dissipating power in the bulk material, what could go wrong. 

Also, for physically large MLCC (Maybe 1206 on up) the automotive 'soft term' or whatever your vendor calls it are well worth the cost if you want a reliable product.

Regards, Dan.

[rx8pilot]

Most app notes and evaluation PCB's avoid thermals......

There is little question that the sense resistors can be smaller. I had them in stock and all setup in software to just drop them in.

Texas Instruments provided me an Excel application that helps design the converter. It is much more thorough than what I was able to setup from the data sheet. That allowed me to get much closer, but I still damaged something while swapping components. The last of controller chips stopped working and I have to wait for more.

I think I can patch this PCB up enough to get full current out of it. I still think the final design will have totally separate control and power PCB's that are stacked. That should allow me to best isolate the control signals, the keep the size down, and avoid HDI PCB's that will blow the budget.

[Siwastaja]

Most app notes and evaluation PCB's avoid thermals......

Yet, they are explicitly required by most capacitor manufacturer appnotes I have looked at, sometimes with exact same style images but opposite annotations (right image: forbidden).

And, forbidden by the part manufacturer usually overrules the "desired" status by an example application engineer.

I think that in this kind of contradiction, you need to look what the capacitor manufacturer says about it.

Most likely doesn't matter if your soldering style is suitable, but just sayin' because I have been hit by exactly this, and now I try to follow the ceramic cap manufacturer's instructions as closely as possible to avoid fires.

A "shorted" ceramic cap is particularly nasty because it becomes a nice low-resistance part which can dissipate watts, glowing bright yellow for quite some time and emitting a lot of smoke from surrounding material, without any fuse or overload protection acting. Good heatsinking by the direct plane soldering keeps it from desoldering itself even though its surface temperature may be over 1000 deg C.

In any case, your layout loop produces maybe about 10nH of excess inductance, if not more. Adding the thermals would add maybe 0.5nH, which is insignificant compared to your huge loop, which just needs to be fixed.