Low noise amplifier.

[GK]

Just a play in SPICE for now. I am using a model for the BF862 that seems to gel well with reality (IDSS at around 14mA which is typical of tested parts, ~800pV noise @ 1kHz with the 1/f corner at ~1kHz.

12 in parallel return theoretically 800pV / sqrt12 = 231pV@1kHz. For the other active components I just used parts available in the LTspice library. LT1022 is a noisy op-amp, there still could be a small benefit from a quieter device in position U3.

Q1 through Q3 is a current source load for the common source, parallel- JFET input stage. U3 is the feedback amplifier, gain is set at 60dB (1000 Av). The other LT1022 is a servo that stabilizes the operating point of the JFET common source stage - to 3VDC at the common drain.

Circuit:



Closed loop gain:



Noise performance, input-referred (noise at output divided by the 60dB closed loop gain):



Feedback amplifier loop gain and phase (70 degrees phase margin at 1MHz bandwidth):



Servo amplifier loop gain and phase (approx 60 degrees phase margin):


 
 

[Kleinstein]

The simulation models of many of the OPs do not include noise. So do a check on this.

Also the zener reference for the constant current source might not include noise. This could be a problem in the 1/f noise region.

The servo amplifier looks a little odd with the divider before the amplifier. I would have an divider after the amplifier, to reduce that noise contribution. The shown configuration might cause quite some noise at the lower frequency limit.

The 1/f noise limit of JFETs shows a lot of scattering. AFAIK this is especially true for the BF862 with different values depending on the batch / fab.

[bobaruni]

Try LT1028 for low noise OPA at U3, it is included in the STD library.
Just to repeat what KleinStein said about noise analysis and perhaps the lack of it with some models.

[Kleinstein]

The noise from U3 should not be such a big problem. This OP sees a relatively high source impedance - so an LT1028 would a an not so good choice - an Lt1007 might work though.
Anyway noise of this OP should not be that critical, as it's noise is reduces by the voltage gain from the JFETs. The LT1022 is not that bad, though there are better one available.

The more critical OP should be the one for the servo loop - at least near the lower frequency limit. Here it needs to be a JFET type.

[snarkysparky]

Just a couple of quick thoughts.

Seems like R24  2200K  would be a very noisy resistor on the gates of the FET's. 

The output opamp is fed with low impedance so it's voltage noise should be low.  LT1022 doesn't seem to be a low noise part.

The gain plots are very impressively flat.

If I may ask what is the purpose of the gate inductors. 

[bobaruni]

If I may ask what is the purpose of the gate inductors.

It's a trick used to reduce the noise induced by the resistor.

[Kleinstein]

R24 is not such a big problem. One will see the noise of this resistor only at the low frequencies near the lower band limit. At higher frequencies it is shunted by the input capacitor. At these very low frequencies the 1/f noise from the JFETs and maybe from the servo OP will be the bigger problem.

The drain side of the JFETs are not a really low impedance source. Typical value is something like 5 K ohms per JFET  (180 µS common source output impedance) - though it could be a little less due to lower voltage.

The inductor are there to stop possible high frequency (e.g. 100 MHz range) oscillations, without adding significant noise.

[MK]

try stepping the source resistance from 0-150 ohms and see what happens to the stability... try 1, 2, 5,10 steppings.

[amspire]

The circuit is not very practical unless you select a matched set of FETs. A seperate source resistor for each FET would help balance the current.

The BF862 looks like a small junction FET and you are using a lot in parallel. I am wondering if there are any single large junction FETs you could look at instead. Something like a Process 58 FET such as  2N5432/3/4. It has a 6nV noise voltage but that is at 100Hz and not the 100KHz noise spec of the BF862. It is not hard to get a low noise figure at 100KHz.

[GK]

The circuit is not very practical unless you select a matched set of FETs. A seperate source resistor for each FET would help balance the current.

The BF862 looks like a small junction FET and you are using a lot in parallel. I am wondering if there are any single large junction FETs you could look at instead. Something like a Process 58 FET such as  2N5432/3/4. It has a 6nV noise voltage but that is at 100Hz and not the 100KHz noise spec of the BF862. It is not hard to get a low noise figure at 100KHz.

Fortunately there is a fair amount of prior art here already. There isn't much that can match the BF862 in the combined terms of input C and price and the 1/f noise corner of 1kHz or less (better) has been very well established.

One (now defunct) forum I was on a member paralleled 64 of these FETs. There is little to be gained from matching devices.

[GK]

try stepping the source resistance from 0-150 ohms and see what happens to the stability... try 1, 2, 5,10 steppings.

I was wondering if someone would be astute enough to bring that up. Phase margin is reduced due to Miller effect feedback reducing the bandwidth of the input stage. Source impedances above 100 ohms begin to cause HF peaking ~ at the unity loop gain frequency (~1MHz). Several k-ohms and things begin to look scary.

This can be fixed with a BJT cascode to the FET input stage.
 

[GK]

The simulation models of many of the OPs do not include noise. So do a check on this.

Also the zener reference for the constant current source might not include noise. This could be a problem in the 1/f noise region.

The servo amplifier looks a little odd with the divider before the amplifier. I would have an divider after the amplifier, to reduce that noise contribution. The shown configuration might cause quite some noise at the lower frequency limit.

The servo amp noise isn't a consideration when there is a 2M2 resistor coupling its output. But as I said in the opening post, this was just a starter sim. I've since refined the servo to a two (dual) op amp design, which was brings another benefit not yet brought up.

[GK]

Some refinements. The added BJT cascode to the JFET stage dramatically reduces Miller effect feedback and now loop gain and phase margin of the amplifier loop is for all practical purposes independent of source impedance. Servo has been improved.

Of course this is still a simulation and and not all component selections are the most optimal. The real life prototype will have additional supply rail filtering (separate RCs for the op-amp rails and maybe a capacitance multiplier for both rail at the board input as well).

[Kleinstein]

The servo loop still has the problem with OP 1/f noise. A simple passive divider (and than unity gain in the inverter) after the OPs would reduce this. Also keep in mind noise of the ref voltages - many models don't include noise.

[MK]

The simulation models of many of the OPs do not include noise. So do a check on this.

Also the zener reference for the constant current source might not include noise. This could be a problem in the 1/f noise region.

The servo amplifier looks a little odd with the divider before the amplifier. I would have an divider after the amplifier, to reduce that noise contribution. The shown configuration might cause quite some noise at the lower frequency limit.

The servo amp noise isn't a consideration when there is a 2M2 resistor coupling its output. But as I said in the opening post, this was just a starter sim. I've since refined the servo to a two (dual) op amp design, which was brings another benefit not yet brought up.

That will help with the motorboating of the loop at the bottom end of the frequency scale

[T3sl4co1l]

Slick.

Have you been following any of Phil Hobbs's work?  This looks like something he would be quite fond of...

For anyone wondering what the heck a 150n inductor is for (aside from the explanation given above), it's approximately the inductance of a "100 ohm" ferrite bead.  The 100 ohm resistance, of course, is its resistance.

Cheap insurance to avoid unintentional grounded-gate oscillators.

Also useful for driving power MOSFETs, because the ferrite bead saturates, potentially sharpening the drive waveform, while providing considerable dampening in steady state.

Tim

[GK]

The servo loop still has the problem with OP 1/f noise. A simple passive divider (and than unity gain in the inverter) after the OPs would reduce this. Also keep in mind noise of the ref voltages - many models don't include noise.

I don't care about the models, I can do the sums. A decent FET-input op-amp for the servo won't will be less noisy than the 2M2 resistor above about 0.1 or 0.2 Hz.
When the flat white noise from the resistor is summed with the 1/f contribution from the op-amp the total increase in noise is a mouse fart in a gale at frequencies well below interest. Though a passive divider is only two additional resistors, so not a great expense.
 

[GK]

The simulation models of many of the OPs do not include noise. So do a check on this.

Also the zener reference for the constant current source might not include noise. This could be a problem in the 1/f noise region.

The servo amplifier looks a little odd with the divider before the amplifier. I would have an divider after the amplifier, to reduce that noise contribution. The shown configuration might cause quite some noise at the lower frequency limit.

The servo amp noise isn't a consideration when there is a 2M2 resistor coupling its output. But as I said in the opening post, this was just a starter sim. I've since refined the servo to a two (dual) op amp design, which was brings another benefit not yet brought up.

That will help with the motorboating of the loop at the bottom end of the frequency scale

Huh? There is no motorboating. The dominant (by a mile) frequency compensating pole for the servo loop is set by the servo integrator time constant. There is plenty of phase margin as shown in the loop gain bode plots.
 

[GK]

Slick.

Have you been following any of Phil Hobbs's work?  This looks like something he would be quite fond of...

No, never heard of him. I'd have to Google.

[MK]

The simulation models of many of the OPs do not include noise. So do a check on this.

Also the zener reference for the constant current source might not include noise. This could be a problem in the 1/f noise region.

The servo amplifier looks a little odd with the divider before the amplifier. I would have an divider after the amplifier, to reduce that noise contribution. The shown configuration might cause quite some noise at the lower frequency limit.

The servo amp noise isn't a consideration when there is a 2M2 resistor coupling its output. But as I said in the opening post, this was just a starter sim. I've since refined the servo to a two (dual) op amp design, which was brings another benefit not yet brought up.

That will help with the motorboating of the loop at the bottom end of the frequency scale

Huh? There is no motorboating. The dominant (by a mile) frequency compensating pole for the servo loop is set by the servo time constant. There is plenty of phase margin as shown in the loop gain bode plots.

at approx 15mHz (milliHz) you have 180 degree phase shift and approx 40db gain...

[GK]

The simulation models of many of the OPs do not include noise. So do a check on this.

Also the zener reference for the constant current source might not include noise. This could be a problem in the 1/f noise region.

The servo amplifier looks a little odd with the divider before the amplifier. I would have an divider after the amplifier, to reduce that noise contribution. The shown configuration might cause quite some noise at the lower frequency limit.

The servo amp noise isn't a consideration when there is a 2M2 resistor coupling its output. But as I said in the opening post, this was just a starter sim. I've since refined the servo to a two (dual) op amp design, which was brings another benefit not yet brought up.

That will help with the motorboating of the loop at the bottom end of the frequency scale

Huh? There is no motorboating. The dominant (by a mile) frequency compensating pole for the servo loop is set by the servo time constant. There is plenty of phase margin as shown in the loop gain bode plots.

at approx 15mHz (milliHz) you have 180 degree phase shift and approx 40db gain...

Those numbers don't correspond to anything I have posted so you aren't making a great deal of sense.


EDIT: I now see that you are erroneously trying to infer servo loop stability from the closed loop gain and phase plot of the amplifier.

[Kleinstein]

Noise from the servo loop will be important only near the low frequency limit, this is already due to the filtering function of the 2.2M resistor and the input capacitor. For the LT1022 used in the plan the 1/f cross over to the 2M resistor is more at 1-2 Hz. Even worse is the noise of the reference in the second version of the DC loop: it will go through to the 2 M resistor and thus likely dominate the noise below about 10 Hz.

But it really depends on the application where the lower frequency limit is. It is actually better to have the lower limit not set by the 1µF and 2.2 M, but from a later stage. So for very low frequency performance a larger input cap could help a little.

At 14 mA each the BF862 take quite some power and thus causes self heating. This can cause noise from thermal fluctuations and also slightly increased noise from the higher temperature alone. Often it is better to use a lower current per FET, especially for low frequency performance.

[GK]

2M2 generates ~190nV noise. The LT1022/LT1056 has less than 100nV noise at 1Hz (as low as the plot in the DS goes), so the crossover would be around 0.1-0.2Hz. But as I stated already, I don't intend to use this particularly noisy op-amp in the servo. The noise of the servo reference isn't necessarily worse as it's divided by 10 in the inverting stage. The LT1634 was used for the simplified sim just because it's available in LTspice, the main purpose of which was to verify the servo and amplifier loop stability. In real life just a simple R-C filter would render noise even from the crappiest Vref negligible.

I'm not running the FETs self-biased at Idss (~14mA), they are running at ~5mA each (only a 1.29:1 noise penalty [ratio^0.25]). At ~3V Vds that's only 15mW dissipation per JFET. Hardly a heating issue.

[acbern]

Should the gate resistor/coil combination not be in series rather than parallel?

[GK]

No. 150-200nH SMD inductors have been proven by others to stabilize large-multiple parallel BF862. They start to be iffy without at a count of four or beyond. The consequential series resonance still looks scary to me so I put 100R damping resistors in parallel just to be extra safe.

A whopping 100 ohms of resistance in series with each gate would worsen the overall >1 kHz noise performance by about 3dB.

[GK]

Will etch tomorrow...............

[Kleinstein]

There are quite a few 100 nF filtering caps to GND in quite a small form factor. I don't think using class 2 MLCC here is a good idea as they can be piezo electric and thus act as a microphone.

For some of them using just 10 nF and than NP0 version might be good enough other should be better film type.

[GK]

?? They are all 1206 and 100nF in 1206 is readily available in NPO/COG.

[GK]

Board done, parts won't arrive until late next week.

[GK]

Well it works, with a minor tweak. Somewhere along the way with the simulations I made a few oversights with the servo constants. Firstly, when modifying the servo topology from the first basic sim I erred with the loop gain scaling by 20dB making the unity loop gain frequency of the servo one decade higher that what it should have been. Secondly I did not re-investigate the servo loop gain and phase margins after adding the BJT cascodes to the JFET input stage to mitigate JFET Miller-effect capacitance. Cascoding the JFET input stage quite largely increases input stage transconductance, which pushes the unity loop gain frequency of the servo loop out proportionally. As it turns out, due to the sum of these oversights, the servo loop with the 1uF integrator capacitor wasn't close to stable.

For adequate phase margin in this topology the unity loop gain frequency of the servo really needs to be not higher than one third the input frequency pole formed by the 1uF input coupling capacitor and the 2M2 resistor; which is thus currently at 0.072Hz. Increasing the servo integrator capacitor from 1uF to 1000uF got the unity loop gain frequency down to ~0.02 Hz where it should be and the amplifier was then stable. I don't like a servo with a 1000uF capacitor. That large it has to be electrolytic which will no doubt be leaky and therefore contribute very low frequency drift all on its own accord. So the design will require a revision, but fudging in the 1000uF for now is a quick way the get the amplifier operational to evaluate its noise performance and other parameters.

Here it is (the tall skinny electrolytic in the middle is the 1000uF. It was the smallest 1000uF I had at hand):



I used my home brew noise measurement test set to measure the amplifiers noise:



Due to mains hum pickup and other interference of the bare amplifier PCB sitting on the bench top there are limits to which I can evaluate the noise performance prior to installing the amplifier into a shielded steel enclosure, so for now I used audio A-weighting filtering, primarily to get rid (mostly) of the 50Hz and HF crud coming from the local AM broadcast transmitter.

This scope shot shows the A-weighted noise at the output of the amplifier (the amplifier having its input shorted) amplified by 80dB (10,000 Av) (actually only by 60dB, but the DSO channel input coupling was set to 10:1 while the input connection was 1:1).



The noise measures 42 uV rms on my test set. The A-weighting filter has an equivalent noise bandwidth of 13.5 kHz. So the equivalent output noise, expressed in a 1Hz bandwidth =  42 uV / SQRT(13500) =  361 nV rtHz.

The amplifier has a fixed closed loop gain of 60dB (1000 Av), so the actual input-referred noise is 0.361 nV rtHz, which is getting quite close to the theoretical target. It can only be improved with a proper shielded enclosure. The noise on the scope has an obvious 100 Hz component (rectified mains) - most likely contributed by the crappy bench supply currently providing the +/-15V.

 

[Kleinstein]

Congratulations.  Less than 0.5 nV /Sqrtz(Hz) sounds really good.

For the servo loop, you might get a lower frequency, if the divider after the integrator is made larger. This would need a good DC stability and DC Level adjustment, as range for automatic adjustments gets smaller. Something like 10 µF and a little larger are available as film type caps.

If needed one could reduce the DC gain of the JFET + cascode stage, with just a resistor to GND.

[GK]

OK, some quick additional measurements for this morning and this will then be it for a couple of days. My noise test set has switchable first order bandpass filters with center frequencies ranging 10 Hz to 20 kHz in 1-2-5 steps. The Q of each filter is pi which (convenient for calculations) returns an equivalent noise bandwidth in each case of half the center frequency. These filter are for "spot frequency" noise measurements and characterizing 1/f noise. Fortunately you do not need bandpass filters with a 1 Hz bandpass to do this accurately! M and C in Low-Noise Electronic System Design show mathematically that in a system characterized entirely by 1/f noise the additional measurement error of a one-third-of-fc bandwidth bandpass filter over a 1 Hz one to be only 0.2%.

Here are my results:

Spot freq.            input-referred noise
 
500                     1.1 nV
1k                        0.45 nV
2k                        0.29 nV
5k                        0.26 nV
10k                      0.27 nV
20k                      0.25 nV

I didn't bother going below 500 because the results at 500 Hz (and 1 kHz for that matter) are already heavily contaminated and artificially raised by 50/100 Hz mains pickup.

In addition to improving the servo amp design I am thinking  about revising the lower bandwidth corner to be a decade higher (from ~0.1 Hz to 1 Hz) as at the moment after any overload you can go off and make a coffee while the servo loop stabilises. PSU and Vref noise is typically characterized in a 10 Hz and up bandwidth and and for audio stuff it's 20 Hz and up. 


 

[G0HZU]

Interesting stuff... could you use/adapt this setup to investigate the differences between thick and thin film resistors for current noise at low frequencies (eg below 500Hz)?

[Kleinstein]

For the low frequency range (e.g. < 10 kHz), the usual way to look the noise, is to send the output to an ADC of some kind and than do all the filtering in software. This way you get all the frequencies at the same time.

For voltage refs there is also interest in the really low frequency range (e.g. 0.1 ..10 Hz). But this might need a different system, more like using AC coupling and an AZ OP.

[GK]

In conjunction with the filter bypass position that is one of the things the amplified noise output jack on my test set is for. The manual filters in conjunction with the accompanying wide-band RMS voltmeter serve as a bench standard for reference/calibration. I don't necessarily trust 100% the accuracy of soundcard results without means to perform rudimentary double checks with a suitable bench standard.

For 0.1Hz to 10Hz voltage reference measurements dynamic (output) resistance is typically a fraction of an ohm so current input noise isn't such a consideration and you'd be better off just paralleling a bunch of <=1nV ein bipolar op-amps which can have much lower 1/f corners and superior LF noise performance than anything with a JFET input.

[GK]

Interesting stuff... could you use/adapt this setup to investigate the differences between thick and thin film resistors for current noise at low frequencies (eg below 500Hz)?

You mean excess noise when current flows through the resistor? Yes, I don't see why not. Once I get the shielding sorted and a few other issues one thing I am quite eager to evaluate is the BF862 gate leakage and the resultant input current noise performance of the amplifier. That will determine the source impedance range that the amplifier most ideal/suitable for.

[GK]

OK, I won't be free to play in the workshop with the soldering iron for at least another 24 hours (freaking Christmas stuff intruding!), but I've spent several hours of insomnia re-evaluating the servo scheme and have come to the conclusion that the scheme of the first prototype is crap.

What I was trying to do in the original scheme in servoing the DC potential of the drain of the JFET common source input amplifier independently of the amplifier control loop was to avoid having to directly couple the amplifier op-amp control loop. This permits the amplifier op-amp (via the non-inverting input) to be ground referenced, thus eliminating one potential source of noise injection, as the op-amp input need not be DC-biased.

However as it turns out after a fair bit of further investigation the pole (as essentially seen by the servo control loop) formed by the coupling capacitor to the amplifier op-amp virtual earth in conjunction with the drain impedance is effectively multiplied by the closed loop gain of the amplifier control loop. This effective pole, limiting the phase margin of the servo control loop, and can only be combated by making the servo loop bandwidth ridiculously low (hence the 1000uF integrator cap fudge on prototype #1).

Attached is a basic sim of of the revised overall topology that I am refining now. This is only a basic sim for the purpose of control loop stability analysis and the component values shown are for a 1 Hz lower cutoff and 100k input resistance, however with the new servo topology which is much better (doesn't need to be ridiculously slow) I'll be reverting to the much more desirable original goal of 0.1Hz and 1M.

The servo control loop now works on the output of the amplifier and everything is DC coupled. The non-inverting input of the amplifier op-amp is required to be biased at the DC potential desired at the BJT-cascoded JFET stage collector. The overall topology is technically sound and the servo can be made stable with sensible constants but some minor attention will have to paid to ensuring the bias potential for the amplifier op-amp is reasonably well filtered. The maximum op-amp input pin current must limited also due to the large 60mA bias current of the input stage, but neither of these requirements look like too much hassle. The voltage gain of the BJT-cascoded JFET input stage is so huge the noise of the amplifier op-amp is almost wholly swamped out. Even very large values of current limiting resistors in series with the op-amp inputs fail to have an effect on the noise performance. 
 

[GK]

OK, I won't be free to play in the workshop with the soldering iron for at least another 24 hours (freaking Christmas stuff intruding!)

Well I lied, LOL. I don't have to go out for another 20 minutes still and I managed to fudge these mods onto the prototype and it works absolutely perfectly:



Here is a simplified schematic showing the modifications:



Here is the amplifiers medium-level 10kHz square-wave response. Note that that huge amount of apparent noise on this signal is the 891kHz carrier of the AM radio broadcast transmitter several kilometers away. The bare prototype is still unshielded on the bench and I of course cannot filter this RF interference out and show the true squarewave response simultaneously. 



Now here is where it gets really interesting. I connected a 100k metal film resistor across the input terminals. This scope screen shot below shows the resultant (amplified) output noise through the audio A-weighting filter of my noise test set. It measured 4.7 mV rms. The A-weighting filter has a 13500 Hz equivalent noise bandwidth, so the output noise, in rtHz, = 0.0047/SQRT(13500) = 40.45 uV rms. Divided by the 60dB closed loop gain of the amplifier that works out to 40.45 nV rtHz - for all sakes and purposes exactly the theoretical thermal noise of 100k at room temperature.

[_Wim_]

Very impressive!

[GK]

Thanks. OK, it's getting on to 1am here, but who needs sleep when it's holidays. Attached is the revised schematic and I am almost done modifying the PCB layout.

[PartialDischarge]

What schematic editor are you using?

[GK]

Protel 99SE, schematic printed to a PDF, opened and screen captured to make the PNG image file via MS paint.

 

[blackdog]

Hi,

Another nice diagram drawing program is "sPlan".
You can not convert it to a file for making printed circuit boards.

This is the company were you can buy the software.
http://www.abacom-online.de/uk/html/splan.html

And below two diagrams drawn with this program.
The low noise amplifier is a almost ready design, i still need to test the protection of the input and the output.
It is not as "Low Noise as GK" desing, bus it is usable to measure normal powersupply's and almost all voltage references except the best.

If there is to much 50Hz in the measuring signal, then I can put a second measuring amplifier behind this one.
This amplifier has a additional 20dB gain if it is necessary and also a 50Hz notch filter (~55 to 60dB Notch).

The relativ low noise, wide band amplifier, designed for high gain and flat response.


Some 50 Ohm attenuators



GK,
Nice design, maybe the design need a little bigger value of C13 to make de square wave without overshoot ?


Kind regarts,
Blackdog

[sdouble]

did you pre-select some matched BF862 ?

Thanks. OK, it's getting on to 1am here, but who needs sleep when it's holidays. Attached is the revised schematic and I am almost done modifying the PCB layout.

[T3sl4co1l]

FYI, not really worth matching here -- gm is proportional to Id, and with an 8-20mA spread, any single transistor is never less than half the average (half of 14mA is 7mA).  So the incremental value per transistor isn't bad at all.

Tim

[GK]

GK,
Nice design, maybe the design need a little bigger value of C13 to make de square wave without overshoot ?

Yeah, increasing the value of C13 does reduce the overshoot, but at the cost of closed loop bandwidth. The current level of over shoot actually corresponds well with simulation and is indicative of better than 45 degrees of phase margin, which is still adequate for overall stability. The unity loop gain frequency is currently around 1.5MHz. 33pF yields a ~1MHz ULGF and very little overshoot. Hmm, I might revise the compensation for slightly prettier squarewaves for a small bandwidth penalty.... I'll see.
Incidentally, R36, the 10M resistor shown in parallel with C13, doesn't do anything useful now that the amplifier circuit is directly coupled, so I've now deleted it.
 

[GK]

did you pre-select some matched BF862 ?

Nope.

[Circlotron]

The BF862 looks like a small junction FET and you are using a lot in parallel. I am wondering if there are any single large junction FETs you could look at instead.

What about a power mosfet with it's thousands of paralleled cells? Would one of those have a good noise figure?

[NiHaoMike]

What about a power mosfet with it's thousands of paralleled cells? Would one of those have a good noise figure?

The input capacitance would be very high. Although that would offer a nice way to mount it on a Peltier for even lower noise.

[Kleinstein]

The BF862 is not that small for a JFET. There a few larger ones (larger trans-conductance and low noise), but these are usually really expensive (e.g. > $20). The BF862 is about the best one can get in low noise compared to input capacitance and it is still relatively cheap. However doing some matching / selection might be a good idea.

Power MOSFETs might be low noise, but they have likely quite some 1/f noise and a high input capacitance. So the noise figure might be good only for a very small frequency range.

[Marco]

Even a humble BSS84 can be relatively low noise (limit case 1 nV/rtHz) ... it just has a 50 kHz noise corner.

[T3sl4co1l]

MOSFETs are noisier than JFETs, especially at LF.

I forget what the lowest noise CMOS op-amp is, but most are upwards of 20nV/rtHz, while the better bipolar amps are in the single digits.

Though, MOSFETs have a good history of RF amplifier use.  Many of the "high tech" types do, too: PHEMTs, GaAs FETs and HBTs.  I forget which, but some of them have a 1/f knee in the MHz; all of them are distinguished by very high Gm, very low capacitance, and very low noise (in their intended frequency range), with fT into the 10s of GHz.  A daring few have dared harness them for "DC" use (Phil Hobbs is particularly fond of using bootstrapped combinations for wideband laser diode and high impedance probe amps).

Tim

[sdouble]

MOSFETs are noisier than JFETs, especially at LF.

I forget what the lowest noise CMOS op-amp is, but most are upwards of 20nV/rtHz, while the better bipolar amps are in the single digits.

Though, MOSFETs have a good history of RF amplifier use.  Many of the "high tech" types do, too: PHEMTs, GaAs FETs and HBTs.  I forget which, but some of them have a 1/f knee in the MHz; all of them are distinguished by very high Gm, very low capacitance, and very low noise (in their intended frequency range), with fT into the 10s of GHz.  A daring few have dared harness them for "DC" use (Phil Hobbs is particularly fond of using bootstrapped combinations for wideband laser diode and high impedance probe amps).

Tim

as far as AsGa FET are concerned, we have to face their rather high leakage current. Due to that unfortunate feature, I use them at 50+MHz only.

[ogoun]

Hi Glen from a fellow aussie
I have been toying with a low noise front end design for audio band use for several months now, with no success in using an integrated solution.
The big challenge I am trying to overcome is the input voltage swing.
The design must accommodate up to +/- 60 volts input, while maintaining extremely low noise and distortion performance. Additionally, I am looking to minimise quiescent current draw (this will be battery operated).

The input is from a single ended source, with impedances that range from tens of ohms up to around 7k. This is due to the varying specs of the microphone preamp output signal, for different model mics. The mics in question are professional capacitor mics, such as those made by gras or bksv.

Since I plan to attenuate the signal after the front end, what i am looking to design is a unity (or less) gain imledance converting buffer stage.

Others have solved this problem with a bootstrapped op-amp power supply (shifts the +/- op amp supply rails in sync with the input signal), but this adds significantly to Iq, as the bootstrapper is linear. I tried a switchmode equivalent, but couldnt get it stable, probably because the smps chip's control loop was too slow, or maybe just my crap design

Anyway, I am biting tbe bullet and looking at doing a discrete front end, and was going to try a matched jfet pair in one of the configs from art of electronics, however your design may be adaptible to my needs...

What are your thoughts on this, as your discrete design skills are more polished than mine.

l8r,
pete

[T3sl4co1l]

I don't understand how you desire a "low noise" amplifier, when the source impedance is low (kohms or less) and the desired gain is less than 1...

For gain < 1, the only thing you can do, that's better than a resistor divider, is a resistor in a feedback loop so that the thermal noise is reduced.  (Assuming the amp is quieter, which might not be the case.)  Or the classic: a transformer.

Unless you meant that the two situations are exclusive, i.e., you want low noise only when gain is required.  In which case, the input signal would be much smaller, under 1V, right?

Tim

[ogoun]

hi tim,
problem is, i cant predict what the input impedance will be.. just using a divider would involve the divider's total resistance being greater than 10x worst case source impedance...  thats a noise price i am not prepared to pay.
the design needs to be accurate from tens of microvolts to tens of volts input, with an unpredictable source impedance between zero and around 7k.

The ultimate objective is to get the signal down to a low level, maybe +/- 2.5v, and use a fully differential signal path all the way to a high quality 24 bit adc.

l8r,
pete

[eeFearless]

I used my home brew noise measurement test set to measure the amplifiers noise:

@GK

That home-brew noise measurement test set looks quite interesting.  Where could I learn more about your project?

[Marco]

Since I plan to attenuate the signal after the front end, what i am looking to design is a unity (or less) gain impedance converting buffer stage.

Others have solved this problem with a bootstrapped op-amp power supply (shifts the +/- op amp supply rails in sync with the input signal), but this adds significantly to Iq, as the bootstrapper is linear.

It's not like the mic pre-amp has no quiescent current, the opamp would only add something in the same region. I'd just use something like one of these circuits with a LTC6090 (the differential pair is less sensitive to temperature). It's expensive, but it saves you some headaches.

PS. isn't the mic pre-amp also just an impedance converting buffer?

[Audioguru]

Why does your preamp have the Jfets? The TL072 opamp already has extremely high input impedance Jfets on its inputs.

[Marco]

Why does your preamp have the Jfets? The TL072 opamp already has extremely high input impedance Jfets on its inputs.

The LTC6090 is CMOS, so if he just wanted the input impedance it alone would suffice, but presumably he wants lower noise. The JFET stages have amplification, so the opamps there and the one from the main topic of the thread don't influence noise.

[3roomlab]

would using 2SK879 suggest better SNR at near DC range?
http://www.mouser.com/ProductDetail/Toshiba/2SK879-GRTE85LF/?qs=sGAEpiMZZMvplms98TlKY3rIOtqo%252bKm62v0tHK6313Y5kqoZKMKXnw%3d%3d

[Kleinstein]

The 2SK879 is still a rather small JFET - good for really high impedance sources (e.g. MOhms range, maybe input stage of a capacitive microphone), not a really low noise type for lower impedance sources. You need something line 30 of them in parallel to get something comparable to a BF862.  Good low noise audio range JFETs are 2SK170 / 2SK117 / SK389.

[sdouble]

gm is too small

[sdouble]

do you know the 2SK932 ?
Very close to BF862 in term of overall performances.
3 ranges of IDSS

[phenol]

or the old russian KP903 jfet.

[3roomlab]

The 2SK879 is still a rather small JFET - good for really high impedance sources (e.g. MOhms range, maybe input stage of a capacitive microphone), not a really low noise type for lower impedance sources. You need something line 30 of them in parallel to get something comparable to a BF862.  Good low noise audio range JFETs are 2SK170 / 2SK117 / SK389.

how about this 1?
http://www.mouser.sg/ProductDetail/ON-Semiconductor/2SK3557-7-TB-E/?qs=sGAEpiMZZMvplms98TlKY72UPjEzp3ixViUnpXrpp6o%3d
how do you see if it is relatively "big" or "small"

[GK]

Hi Glen from a fellow aussie
I have been toying with a low noise front end design for audio band use for several months now, with no success in using an integrated solution.
The big challenge I am trying to overcome is the input voltage swing.
The design must accommodate up to +/- 60 volts input, while maintaining extremely low noise and distortion performance. Additionally, I am looking to minimise quiescent current draw (this will be battery operated).

The input is from a single ended source, with impedances that range from tens of ohms up to around 7k. This is due to the varying specs of the microphone preamp output signal, for different model mics. The mics in question are professional capacitor mics, such as those made by gras or bksv.

Since I plan to attenuate the signal after the front end, what i am looking to design is a unity (or less) gain imledance converting buffer stage.

Others have solved this problem with a bootstrapped op-amp power supply (shifts the +/- op amp supply rails in sync with the input signal), but this adds significantly to Iq, as the bootstrapper is linear. I tried a switchmode equivalent, but couldnt get it stable, probably because the smps chip's control loop was too slow, or maybe just my crap design

Anyway, I am biting tbe bullet and looking at doing a discrete front end, and was going to try a matched jfet pair in one of the configs from art of electronics, however your design may be adaptible to my needs...

What are your thoughts on this, as your discrete design skills are more polished than mine.

l8r,
pete

Unfortunately this is a rather high gain (x1000) measurement amplifier for very small signals that isn't readily adapted for unity gain / high-level signals. The current consumption is not low either. For a discrete circuit that might do what you want (buffer those mic preamps that run on +120V or +/-60V supply rails and deliver comparable-level signal output) google "diamond buffer".     

[Kleinstein]

The 2sk3557 is somewhat comparable to the BF862. The good thing is it seems to have specs down to the audio range too - the DS I know are missing specs on LF noise.
Voltage noise of JFETs depends a lot on the trans-conductance. So a high trans-conductance is needed to get a really low noise.

[T3sl4co1l]

All JFETs are pretty much the same, with small tweaks in voltage rating (high voltage JFETs long ago disappeared, so what's left is in the 20-30V range and not much outside of that), and capacitance (junction layout, bond pads?).

The only truly free variable is junction width: bigger means less Rds(on), more Id, more gm, and more C.

Best performance is had when you choose the part with Rds(on) or X_C or 1/gm closest to system impedance (more or less).

Noise mechanisms are poorly documented.  Probably something like trapped impurities in surface or junction layers, or oxide/passivation.  It's not clear if a quiet JFET can be "designed", or if they are always selected.  AoE3 shows that some RF JFETs are quiet and some are not, at LF.  Simply put: you get what you pay for.  If you didn't buy a low noise (at LF) part, you aren't likely to get one.

(BJTs, on the other hand, often have provocative noise performance, even for rather more distantly spec'd types, like switching transistors.  There are few if any "oddball" noise sources, so that the biggest contributors are base resistance (Rbb') and base current noise.  The downside, isn't really a downside, just a matter of different needs for different applications: the impedance range is much lower, kohms to single ohms.  AoE3 plots all of this.)

Tim

[GK]

@GK

That home-brew noise measurement test set looks quite interesting.  Where could I learn more about your project?

I once had an incomplete write up on a webpage, but needs to be re-written into my new site format. I've got the revised PCB for my low noise measurement amplifier etched, drilled and lacquered and once that is done/tested I'll be giving this project a webpage of its own which will include the Gerber files. I'll be using my noise test set in the measurements so this will be as good a reason as any to re-write and web-publish the test set again. I'm currently getting a couple of other incomplete projects out of the way and off the bench, so will probably take a few weeks.
 

[eeFearless]

@GK

That home-brew noise measurement test set looks quite interesting.  Where could I learn more about your project?

I once had an incomplete write up on a webpage, but needs to be re-written into my new site format. I've got the revised PCB for my low noise measurement amplifier etched, drilled and lacquered and once that is done/tested I'll be giving this project a webpage of its own which will include the Gerber files. I'll be using my noise test set in the measurements so this will be as good a reason as any to re-write and web-publish the test set again. I'm currently getting a couple of other incomplete projects out of the way and off the bench, so will probably take a few weeks.

I'm defined looking forward to learning more.  Please keep us posted when you are ready ...

[vindoline]

I too am interested in how you measure and characterize the performance of a low noise amplifier. I'm looking forward to more!

[GK]

The 2SK879 is still a rather small JFET - good for really high impedance sources (e.g. MOhms range, maybe input stage of a capacitive microphone), not a really low noise type for lower impedance sources. You need something line 30 of them in parallel to get something comparable to a BF862.  Good low noise audio range JFETs are 2SK170 / 2SK117 / SK389.

how about this 1?
http://www.mouser.sg/ProductDetail/ON-Semiconductor/2SK3557-7-TB-E/?qs=sGAEpiMZZMvplms98TlKY72UPjEzp3ixViUnpXrpp6o%3d

If the Noise Figure charts in that parts datasheet are to be believed the 1/f noise performance looks very good indeed, at <100 Hz. However the NF versus Rg plot showing essentially a flat ~1dB NF regardless of the value of Rg makes no freaking sense whatsoever.

The 1dB NF plotted/specified (for Rg=1k) computes to an e_n of 2.1nV/rthz. This is at Id=1mA. For comparison the NXP datasheet for the BF862 specifies 0.8nV but the value of Id is neglected. My guess (from measurements) is that the 0.8nV is for Id @ typical Idss (~16mA). 16mA test versus 1mA test = 16/1^0.25 = 2:1 noise test disadvantage for the 2SK3557 (JFET voltage noise is directly related to gm and gm goes by Id^0.25). So in reality the 2SK3557 is likely only marginally more noisy than the BF862, as one should predict from the comparative gm of 35mS (typ) of the 2SK to 45mS (typ) of the BF. Simplified JFET voltage noise can be computed from the equivalent channel resistance which = 0.67/gm.

Dunno how the 2SK compares in terms of input current noise though as (unlike in the NXP datasheet for the BF862) gate leakage current isn't comprehensively charted. The BF682 is a very good performer in this regard. At the Vds and Id I am running them at gate leakage according to the chart in the datasheet is in the order of ~1pA per gate.



 

[ap]

@GK
have you ever measured the amplifier's noise density allone (input shorted)? Connecting a high ohms resistor at the input, as you did, does not say much about the expected extraordinary noise performance. So would be interesting, should be somewhere arround 0.3nV/sqrtHz.

[GK]

@GK
have you ever measured the amplifier's noise density allone (input shorted)? Connecting a high ohms resistor at the input, as you did, does not say much about the expected extraordinary noise performance. So would be interesting, should be somewhere arround 0.3nV/sqrtHz.

Yes. As detailed in reply#30 I measured 0.361nV with the input shorted in an audio A-weighted bandwidth and that was with a lot of rectified mains hum-pickup (the amplifier was unshielded at the time), as shown on the attached scope screen photo.

The test with the 100k resistor (that I posted in a later reply) that returned the theoretical thermal noise of 100k demonstrates the amplifiers negligible current input noise.

[3roomlab]

Slick.

Have you been following any of Phil Hobbs's work?  This looks like something he would be quite fond of...

For anyone wondering what the heck a 150n inductor is for (aside from the explanation given above), it's approximately the inductance of a "100 ohm" ferrite bead.  The 100 ohm resistance, of course, is its resistance.

Cheap insurance to avoid unintentional grounded-gate oscillators.

Also useful for driving power MOSFETs, because the ferrite bead saturates, potentially sharpening the drive waveform, while providing considerable dampening in steady state.

Tim

is there a special reason to get 100ohm impedance on the ferrite? or there is an approximate way/equation to determine a usable range?

[T3sl4co1l]

Yes -- ferrite beads are measured at 100MHz, and 0.15uH is 100 ohms at 100MHz.  So, presumably, the desired damping is about equivalent.

This is an overestimate, because the losses are high over a wider range than a simple L || R network.  The result will be more noise at those extra frequencies (i.e., 10MHz+ vs. 100MHz+).  But this might not be a problem, since we're not talking extreme bandwidth, or very low noise impedance here.

This doesn't work in reverse, because of the overestimation; replacing a FB with an L || R may need a lower break frequency.  Depends where the Z(F) is needed.

FBs always(?) come with a Z or R & X plot, just match up how much you need at what frequencies.

Tim

[awallin]

This paper claims 0.5nV/rt(Hz) with either IF9030 or 2SK369 at the input
http://users.cosylab.com/~msekoranja/tmp/04447683.pdf

do you have a noise spectrum for the parallelled BF862 design?

[3roomlab]

The circuit is not very practical unless you select a matched set of FETs. A seperate source resistor for each FET would help balance the current.

The BF862 looks like a small junction FET and you are using a lot in parallel. I am wondering if there are any single large junction FETs you could look at instead. Something like a Process 58 FET such as  2N5432/3/4. It has a 6nV noise voltage but that is at 100Hz and not the 100KHz noise spec of the BF862. It is not hard to get a low noise figure at 100KHz.

Fortunately there is a fair amount of prior art here already. There isn't much that can match the BF862 in the combined terms of input C and price and the 1/f noise corner of 1kHz or less (better) has been very well established.

One (now defunct) forum I was on a member paralleled 64 of these FETs. There is little to be gained from matching devices.

was there any indication of the performance of that 64 JFET version?

[cat87]

Very interesting design. I too am looking forward to  details regarding the LNA's performance and also some details regarding the  noise measurement  equipment you previously showed. That, together with this LNA can be really handy for quite a lot of experiments.

Is the noise measurement test set, by any chance,  based on R. Cordell's plans?

[GK]

Is the noise measurement test set, by any chance,  based on R. Cordell's plans?

I'm not sure what plans those could be. It's just true-RMS wide-band ac voltmeter based on an LTC1968, calibrated against a REF192. There is a low-noise (1.3nV measured) bipolar-input front-end amplifier extending the meters sensitivity to 1uV full scale and a bunch of switchable bandwidth and frequency-defining filters between the two. There is also a switched-frequency, amplitude-calibrated sinewave generator intended to be used in conjunction with an external attenuator box for making accurate gain measurements of any suitable device under test. The only part borrowed from what Cordell has published is the passive network of the A-weighting filter. I've attached the schematics.

[cat87]

Thanks for posting the schematics.

I was initilly thinking it might have some elements from  Cordell's THD analyzer    It looks like I was way off.

[EmmanuelFaure]

AD8597 is a poor choice for such an AC coupled LNA. Too much current noise, too much bias current. A JFET input amplifier would have been a better choice. Like OPA140, OPA827, LT1792, or a discrete input amplifier based on the common low noise JFET.

[GK]

AD8597 is a poor choice for such an AC coupled LNA. Too much current noise, too much bias current. A JFET input amplifier would have been a better choice. Like OPA140, OPA827, LT1792, or a discrete input amplifier based on the common low noise JFET.

It's specifically intended for low impedance sources (like the signal output of an audio preamplfier or a power amplifier) and any JFET substitute here would be significantly noisier (about five times noisier for the OPA140 and about four times noisier for the OPA827 and LT1792). And for a bipolar op-amp in the ~1nV en class, the AD8597 actually has comparatively low input bias current and current input noise.

[eeFearless]

I'm confused.  I thought the parallel discrete approach is the LNA?  Or, will the parallel discrete approach be replacing the LNA board containing the AD8597?

[GK]

I'm confused.  I thought the parallel discrete approach is the LNA?  Or, will the parallel discrete approach be replacing the LNA board containing the AD8597?

He is talking about the "LNA" of my test set which is a separate project.

[EmmanuelFaure]

It's specifically intended for low impedance sources (like the signal output of an audio preamplfier or a power amplifier) and any JFET substitute here would be significantly noisier (about five times noisier for the OPA140 and about four times noisier for the OPA827 and LT1792). And for a bipolar op-amp in the ~1nV en class, the AD8597 actually has comparatively low input bias current and current input noise.

Not "noisier" but "the voltage noise from the datasheet is lower", nuance. There's also a current noise, and there's also noise from the input filter.

If its purpose is audio noise analysis, i.e. > 20Hz, so ok. But at low frequencies the performance of this schematic is not great. Calculations and equivalent noise diagram attached, I got 100nV/sqHz @ 1Hz and, it's true, about 1nV/sqHz at the asymptote.

Another nasty mechanism : With such a bipolar op amp the input bias current is about 100nA. Cf the datasheet on page 8 "Input Bias Current vs. VCM", it can be calculated the bias current TC is about 1nA/°C. When the input of your amp is short circuited, or when you connect a low impedance source, the non-inverting input of the op amp sees the impedance of your RC filter, about 5kOhms at 1Hz (28µF // 100k). Let's say there's a die temperature fluctuation at 1Hz with an 0.01°C amplitude, and there you have a new "noise" source contributing for 50nV/sqHz.

For very low noise AC-coupled application, bipolar amps are not the way to go. The design by Levinzon posted by awallin, JFET based, does better than this.

[GK]

It's specifically intended for low impedance sources (like the signal output of an audio preamplfier or a power amplifier) and any JFET substitute here would be significantly noisier (about five times noisier for the OPA140 and about four times noisier for the OPA827 and LT1792). And for a bipolar op-amp in the ~1nV en class, the AD8597 actually has comparatively low input bias current and current input noise.

Not "noisier" but "the voltage noise from the datasheet is lower", nuance. There's also a current noise, and there's also noise from the input filter.

If its purpose is audio noise analysis, i.e. > 20Hz, so ok. But at low frequencies the performance of this schematic is not great. Calculations and equivalent noise diagram attached, I got 100nV/sqHz @ 1Hz and, it's true, about 1nV/sqHz at the asymptote.

Another nasty mechanism : With such a bipolar op amp the input bias current is about 100nA. Cf the datasheet on page 8 "Input Bias Current vs. VCM", it can be calculated the bias current TC is about 1nA/°C. When the input of your amp is short circuited, or when you connect a low impedance source, the non-inverting input of the op amp sees the impedance of your RC filter, with is about 5kOhms at 1Hz (28µF // 100k). Let's say there's a die temperature fluctuation at 1Hz with an 0.01°C amplitude, and there you have a new "noise" source contributing for 50nV/sqHz.

For very low noise AC-coupled application, bipolar amps are not the way to go. The design by Levinzon posted by awallin, JFET based, does better than this.

 

Yes, noisier. Do you even understand the given application? The amplifier is specifically a front-end for an RMS ac voltmeter which isn't designed to respond to signals as low as 1 Hz and in the operational bandwidth with the intended low-impedance sources voltage input noise (which is much higher for JFET substitutes) dominates.

A snapshot from the project write-up I previously had on the web:



I deliberately set the high-pass input pole frequency low enough so that LF noise is adequately low in the operational bandwidth whilst setting time is not annoyingly long. That predicted/computed/measured/verified 1.3nV rt-hz performance would not be matched by a significant margin by any substitute JFET op-amp.

[EmmanuelFaure]

 

[vindoline]

It's just true-RMS wide-band ac voltmeter based on an LTC1968, calibrated against a REF192. There is a low-noise (1.3nV measured) bipolar-input front-end amplifier extending the meters sensitivity to 1uV full scale and a bunch of switchable bandwidth and frequency-defining filters between the two. There is also a switched-frequency, amplitude-calibrated sinewave generator intended to be used in conjunction with an external attenuator box for making accurate gain measurements of any suitable device under test. The only part borrowed from what Cordell has published is the passive network of the A-weighting filter. I've attached the schematics.

Glen, thank you for posting your beautifully prepared design documents. As an amateur, your clearly laid out drawings make it much easier to follow and learn. I look forward to seeing more on your test setup.

[eeFearless]

Glen, thank you for posting your beautifully prepared design documents. As an amateur, your clearly laid out drawings make it much easier to follow and learn. I look forward to seeing more on your test setup.

Yes ... very instructive ... thank you ...

[3roomlab]

i am curious about this parrallel noise thingy, so i went for a walk in google.

this article caught my attention, but it has too much math for my brains.
http://leachlegacy.ece.gatech.edu/papers/Parallel.pdf

under point 1.4 in the PDF it describes a "sweet" spot number of parrallel beyond which more BJT/JFET = more noise and not less. i am just wondering, for those who are good with maths, what would likely the approx max number for BF862 be?

[eeFearless]

this article caught my attention, but it has too much math for my brains.
http://leachlegacy.ece.gatech.edu/papers/Parallel.pdf

under point 1.4 in the PDF it describes a "sweet" spot number of parrallel beyond which more BJT/JFET = more noise and not less. i am just wondering, for those who are good with maths, what would likely the approx max number for BF862 be?

That paper is discussing finding the optimum N, where the total collector current is constrained to be constant. So, I don't believe it is relevant in this design, where the designer is accepting the incremental increase in current for each amp in parallel.

The answer to your question of solving for N will depend on what values you constrain the aggregate bias currents.

[nfmax]

MOSFETs are noisier than JFETs, especially at LF.

I forget what the lowest noise CMOS op-amp is, but most are upwards of 20nV/rtHz, while the better bipolar amps are in the single digits.

Though, MOSFETs have a good history of RF amplifier use.  Many of the "high tech" types do, too: PHEMTs, GaAs FETs and HBTs.  I forget which, but some of them have a 1/f knee in the MHz; all of them are distinguished by very high Gm, very low capacitance, and very low noise (in their intended frequency range), with fT into the 10s of GHz.  A daring few have dared harness them for "DC" use (Phil Hobbs is particularly fond of using bootstrapped combinations for wideband laser diode and high impedance probe amps).

Tim

We have used Eudyna FHX35LG HEMT's in broadband applications with frequencies down to a few kHz, though we are less concerned with noise down there. They seem to work well.

[3roomlab]

I'm not running the FETs self-biased at Idss (~14mA), they are running at ~5mA each (only a 1.29:1 noise penalty [ratio^0.25]). At ~3V Vds that's only 15mW dissipation per JFET. Hardly a heating issue.

could anyone enlighten me about what is noise penalty? (vs Idss current?)
i had a go at LTspice, but i dont have the BF862 model :/
it appears to work in simulation 1nV -> 5uV (0.01Hz). but i dont think it will be low noise

[GK]

JFET voltage input noise goes approximately by the fourth root of Id (<Id = >noise). If the FET has, say 5nV noise at 10mA Id, then at 1mA Id it will have 5nV*((10mA/1mA)^0.25) = 8.9nV.
AFAIK this is an approximation/general rule assuming that the FET is an ideal square law device. I don't know how well it typically continues to hold for values of Id decades below Idss.

 

 

[3roomlab]

i spent some time understanding more about JFET simulation, and i ended up with this model. what are the odds that 4 stages of this coupled 1 after another will actually produce x100,000 gain?

[T3sl4co1l]

I would be deeply concerned about s12 turning such a chain into an oscillator.

Tim

[GK]

Well, in my mission to tidy up / complete all of my unfinished projects, I have finally gotten around to knocking up a shielded steel enclosure for the final iteration of this little amplifier. Did it totally eliminate the pickup of 50Hz mains hum and radiated 100Hz rectified mains from my beefy bench supply and other equipment? Nope! But with a lengthy power lead and some careful orientation of the amplifier (on a chair in the middle of the lab) I managed to practically get the 50/100 Hz pickup below the broadband noise floor, but I'm sure if the amplifiers output was examined on a spectrum analyser the 50/100Hz would still stand out like dogs balls.

I now measure (audio A-weighting filter bandwidth) an input-referred voltage noise for the amplifier of 270pV SQRT/Hz.

To recap, the finished amplifiers bandwidth is 0.1Hz to ~1MHz and the gain is fixed at 60dB (x1000 Av).

I should have a web page for this project written up in a week or so, including the PCB Gerber files and further performance measurements. 

[necessaryevil]

Very interesting. I'm wondering about the measurements and the pcb design. Are you going to try to run it on batteries?

[GK]

Are you going to try to run it on batteries?

Probably not as I can generally do without it. I did contemplate a small box with a small 12V gell cell and a well shielded and filtered SMPS to generate the +/-15V. At this power level the switching frequency could be very high to keep radiated noise out of the amplifiers pass band. But this doesn't currently fit into my priority list.

One thing to note is that the BF862 is now unfortunately obsolete and stocks from the major suppliers at least seem to have dried up. The are still a number of good candidates active though. My pick for a substitute would be 2SK3557. The gm appears to be a little bit less, so the overall noise will be a little higher, but the low frequency performance is much better with a 1/f corner of 100Hz or so. The BF862's from NXP typically cornered in the 1-2kHz range.   

For the potential experimenter I designed the amplifier to be flexible in the total drain current setting. I'm running my BF862s conservatively at 5mA each, but the design can easily dissipate three times this with smaller value resistors used in the current source. The heat is dissipated over a generously large area by many devices.
 

[T3sl4co1l]

There's a new JFET from On Semi that's apparently slightly better than BF862.  I forget the number offhand, but give it a search.

Tim

[CopperCone]

Having to position it in themiddle of the lab sounds annoying. Have you considered using thicker steel or iron for the enclosure? Or adding a seperate mu metal shield? I talked to someone about the whole hydrogen tempering of mu metal and he said its nice but not necessary. Might help

What gauge did you use btw? I am interested.

[CopperCone]

Also i think with a switching supply you can still get modulation of the switching frequency showing up in your pass band. And you have a large area so you might get modulated rfi rectification causing problems with a switcher.

You probobly want to power your lab power supply with a low capacitance isolation trasformer, verify home grounding and use shielded cables, including the cable between the lna and psu and psu and isolation transformer

[Cerebus]

Having to position it in themiddle of the lab sounds annoying. Have you considered using thicker steel or iron for the enclosure? Or adding a seperate mu metal shield? I talked to someone about the whole hydrogen tempering of mu metal and he said its nice but not necessary. Might help

What gauge did you use btw? I am interested.

Skin depth at 50Hz is about 1 cm, that's going to be one heavy enclosure...

[T3sl4co1l]

Having to position it in themiddle of the lab sounds annoying. Have you considered using thicker steel or iron for the enclosure? Or adding a seperate mu metal shield? I talked to someone about the whole hydrogen tempering of mu metal and he said its nice but not necessary. Might help

What gauge did you use btw? I am interested.

Skin depth at 50Hz is about 1 cm, that's going to be one heavy enclosure...

What is?  Mild steel is around 1mm.  Did you leave off permeability?

Induction in cables is a far more likely culprit; at these levels, even electrostatic coupling into poorly screened cables is significant.  (Braid + foil shielded cable is best.  Unfortunately, no common coax is really suited to deal with magnetic induction below 10s of kHz, where your best option is avoidance.)

Tim

[GK]

I considered making a double screened enclosure (a steel box within a steel box), but at the end of the day overly heroic efforts to screen the amplifier itself are pointless as you still have to deal with the interconnecting cable and the DUT itself. The amplifier and the DUT just have to be positioned away from sources of mains hum.

The sheet steel is 0.75mm.

[BrianHG]

What can I use such an insanely low noise amplifier for?

[GK]

Measuring stuffs.

[TiN]

are pointless as you still have to deal with the interconnecting cable and the DUT itself.

Typically for very low noise requirements the DUT in own shielded can will be placed inside the larger shielded box, together with the LNA.
In serious facilities this extends to making shielded rooms with metal walls, essentially putting test equipment, operator and related stuff into same shielded Faraday cage. 

[GK]

I finally have, at least, an initial webpage uploaded for this project: 

http://www.glensstuff.com/ulnma/ulnma.htm

I won't get around to finishing the page off with a brief write up and performance measurements this weekend, but for now the PCB Gerber files, schematic and PCB top overlay diagrams are all there.

[eu7bz]

Hello!
What is the current consumption of +15 volts and -15 volts?
Thank!

[Mrt12]

Hi Guys,
can someone explain a bit how this amplifier circuit with those paralleled JFETs work?
I would like to make a very low noise amplifier as well, for phase noise measurements.
As some of you probably know, Wenzel has published a low noise amplifier as well, exactly for this purpose (see: http://www.techlib.com/files/lowamp.pdf) and the circuit shown here in the initial post seems to be somewhat similar.
But I don't understand how it works at the moment, any hints?

[Gerhard_dk4xp]

1. All FETs get the same input signal.
2. All FETs generate noise that has nothing in common to the noise of their neighbours.
    I.E. These noise sources are not correlated.
3. If you sum up the outputs of all FETs, the amplified input signal adds linearly.
4. A noise peak from one FET may happen when there is a noise valley from a
    different FET, so the noise does not add linearly but less. Partly, it cancels.
5. After some math ado: the noise adds up with the square root of the N FETs.
6. So, from 4 FETs in parallel you get half the noise voltage, relative to the output signal.

Some of the early publications on this are the PMI / AD MAT-02, MAT-03, MAT-04 data sheets
and the data sheet of the LT1028.

I also got into that via Wenzel's design. The pic is V2, OMG, there is a date code .
V1 was still more Wenzel-ish, but I wanted MORE!
The board has the ring mixer in the top left corner, but could be used as a general
purpose preamp. Everything was switched cold with relays: gain, input, frequency corners...

For phase noise measurements, there is no point to try to improve on Wenzel.
There comes enough noise from the ohmic resistance in the diode ring. An AD797 is enough.

[Gerhard_dk4xp]

I have buit in the mean time a lot of these massively paralleled JFET amplifiers.
Virtually all of them that I have checked shared one misfeature: Somewhere,
they show negative input impedance. If you don't have the right cable /
inductive source at the input, that may have no consequences.
But the vector network analyzer on the table is cruel and shows the shortcomings.
Bootstrapping seems to help to some extend, and also making the feedback loop
ultra fast.

You may think that the sources are near ground potential. After all, there is only
a 1 Ohm or so resistor from sources to ground. But that's not true. The feedback
makes the sources follow the gate AC.

In the view of the transistor, the drain is low impedance (looks into a cascode emitter
or mild load resistance) while the source follows the gate closely. Look, Ma, I'm a
follower!  And it oscillates like followers like to do.

Note that you cannot see that in the bode plot of the feedback loop. It is only the
FET that oscillates. The loop only creates the preconditions. And if it is slow,
the source voltage looks capactively loaded.

The usual, and the only easy way to remove the negative input impedance is a
gate stopper resistor. But you definitely do not want that in a low noise amplifier.

First pic is one of my massively par amplifiers. The added BUF634 is meant
to minimize the feedback delay, but it is still much worse than a VCVS in LTspice. 
The amplifier uses the new FETs from ON semi, individually cascoded with a
large pinch off JFET.

I'd say the new ON semi FETs are on par with the BF862, not better. Maybe a little
bit lower 1/f corner, but no reason to stop using BF862 as long as you have them.

The other pic uses 2 Interfet IF3602 FET pairs. The TO-5 coolers are just there
to provide thermal mass. 30 Hz 1/f, 300 pV/rt Hz per FET. Available from Mouser
for €55 each or so. The data sheet values seem quite optimistic; I need a lot more
current to get the 300 pV per transistor. The 4 of them could be measured at
180 pV/rt Hz. The FZT851 is the cascode; it is bootstrapped from the source.

While the normal feedback removes the gate-source capacitance, the bootstrapped
cascode also removes the gate-drain capacitance. We talk of several hundred pF
for each of these huge FETs. Minimizing capacitance has a very good influence on stability.

Everything is nice & well behaved until 1 MHz, where it all collapses. When I
damp everything down to, say, 250 KHz, it is probably unconditionally stable.
But I insist in 1 MHz bandwidth. 

I have removed the bias loop on this one. The input capacitor in these amplifiers
must be huge to effectively short the noise of the bias resistor throught the DUT.
The DUT must be low-resistance, or such a low noise amplifier would be futile
from start. The bias loop must be much slower than the input RC or it would interact.

A TL431 minus a diode drop was about right for temperature compensation.
The blue 10-turn-pot sets the OP. In the upper right of the board is a window
comparator that checks the operating point. When we are far off, as when we
just connected the preamp to a large DC voltage, the bias resistor is reduced
via a MAX393 analog switch so that we don't have to wait forever.

[Mrt12]

1. All FETs get the same input signal.
2. All FETs generate noise that has nothing in common to the noise of their neighbours.
    I.E. These noise sources are not correlated.
3. If you sum up the outputs of all FETs, the amplified input signal adds linearly.
4. A noise peak from one FET may happen when there is a noise valley from a
    different FET, so the noise does not add linearly but less. Partly, it cancels.
5. After some math ado: the noise adds up with the square root of the N FETs.
6. So, from 4 FETs in parallel you get half the noise voltage, relative to the output signal.

Some of the early publications on this are the PMI / AD MAT-02, MAT-03, MAT-04 data sheets
and the data sheet of the LT1028.

I also got into that via Wenzel's design. The pic is V2, OMG, there is a date code .
V1 was still more Wenzel-ish, but I wanted MORE!
The board has the ring mixer in the top left corner, but could be used as a general
purpose preamp. Everything was switched cold with relays: gain, input, frequency corners...

For phase noise measurements, there is no point to try to improve on Wenzel.
There comes enough noise from the ohmic resistance in the diode ring. An AD797 is enough.

Hi Gerhard,
I already know you are one of the low noise experts here, I have already read your posts ;-)
Thanks for the hints with the data sheets. I will check these out.

Maybe my question was not clear: for me it is obvious, that the noise of the transistors is uncorrelated and thus, when paralleling them, it is somewhat averaged out because it adds geometrically. This point was clear to me. But it is still not clear how the circuit consisting of the JFET and OpAmp works. How is the gain adjusted, etc. pp. I do want to make my own design, and not just copy the Wenzel circuit without completely understanding what it does ;-)

[TERRA Operative]

Apologies for the thread bump, but I am interested in attempting to build this amp, except for the lack of availability on the BF862 JFET's.
Can anyone point me in the direction of a suitable replacement?

[TERRA Operative]

To answer my own question, I'm going to try 2SK3557 in place of the BF862 parts.
I have made my own layout from the schematics with almost all SMD parts, sized to fit in a few common enclosures I can get here in Japan. Picture of what I have so far attached below.


I have some more questions though if anyone can answer.

What do the trimpots RV1 and RV2 do? It looks like RV2 is to balance the balanced output, but I'm not sure about RV1, I just want to make sure that I twiddle them properly when I power it up.

Also, the capacitors on the input, output and power jacks, I assume they are probably around 0.1uF, except the disk ceramics that look to be 22nF, with the ground of the input jack connected directly to the chassis?

[Kleinstein]

In the last schematics from this post RV1 sets the exact gain. They are both not really critical.

2SK3557 looks like a reasonable replacement for the BF862. It is higher input capacitance and a lower 1/f noise cross over. So not as good for the higher frequencies but likely better for low frequencies.
The capacitor values are given in the plan. The capacitor in series with the input should be more like 1 µF (it sets the low frequency limit) and should be a low loss type, so likely PP film  type.

The circuit needs reasonable well matched FETs to really used all fets equally.

This type of FET amplifier may need some extra capacitance or RC series connection at the input to ensure stability under all circumstances / source impedance. Something on the order of 50 pF + 100 ohms in series. A simulation could give a better guess. 

[TERRA Operative]

Thanks for the info!

For the capacitors, I don't mean the input 1uF cap, but the capacitors soldered point to point style directly on the input, output and power jacks.
I assume they are not critical in any way, so I assume 0.1uF would work ok?

[Kleinstein]

The capacitors directly at the power jacks should be not critical and 100 nF sound like reasonable.

For the caps at the output - these must be much smaller if a fast response is needed. So more like 100 pF, maybe 1 nF.
One could also consider to wind the input wires through a ferrite ring as a common mode filter.
I don't see a cap at the input - here one may have some 10-100pF that could also help against possible negative input impedance.

[TERRA Operative]

Great, thanks.

One more question about a detail that I noticed in the schematic.
If you look where I highlighted in the attached image below, it seems one diode in package D3 is shorted ground to ground. Does this look correct? It looks like it will affect the signal on one half of the waveform compared to the other?

I also attached a 3D render of my version, sized to fit a Takachi brand enclosure, almost all SMD with no wiring or flyleads required. I think it should work ok. 

[awallin]

If you look where I highlighted in the attached image below, it seems one diode in package D3 is shorted ground to ground. Does this look correct? It looks like it will affect the signal on one half of the waveform compared to the other?

looks like a diode clamp that clips the input voltage to a maximum of either +2 or -2 times a diode forward drop.

do you (or someone else?) have kicad sources for this somewhere? looks like a fun project
previously I made an op-amp version with ADA4898 roughly based on the 'lono' (http://www.hoffmann-hochfrequenz.de/downloads/lono.pdf) ...

[TERRA Operative]

Yeah, a voltage clamp is what I thought, but what's up with that ground between one side of the diode arrays won't that make the clamped voltages lopsided so-to-speak?


I have the diptrace layout I drew up that I can supply once I have it tweaked nice, and here's the webpage of the original design: http://www.glensstuff.com/ulnma/ulnma.htm

[GK]

The clamp isn't symmetrical about ground because the JFET gate potential sits at a few hundred mV negative and needs headroom for the possibility of lower transconductance JFETs or running a lower Id.
The diode of that pair with both A and K tied to ground simply isn't used.

When you first apply power don't be alarmed that the output is railed out and that the lower two LEDs aren't initially glowing. That's normal because the JFETs are saturated and grounding the emitters of the cascodes until the servo loop has stabilized the quiescent DC operating point. It takes 30 or 40 or 60 seconds or so. Sorry I don't have a BOM. Don't go changing any resistive dividers or time constants anywhere.

[Kleinstein]

The board layout looks like it has a few points that are not ideal: the input JFETs are quite a bit spread out and relatively close to the power transistors from the power supply section. The power supply section is a possible source of variable heat and should thus be more separated, possibly even using THT power transistors.
The board looks like there is a ground plane - for good precision one should have a defined ground path for the signal. So R42 should be closely linked to ground of the input terminal. With only 1 Ohms trace resistance can also become an issue.

I don't see the input capacitor C1 - ideally this should be a low loss type like PP. NP0 caps are not yet that practical at 1 µF. So even if most of the board is SMD, I would consider space for a relatively bulk PP film type.

There are a few points with the circuit:

I don't think one really needs the trimmer for the output balance - just 2 good resistors should be good enough.
I would more think about a trimmer or optional parallel resistors to adjust the temperature drift, possibly even with the option to go close to zero. There are a few point where one could do a TC adjustment,  e.g. via the exact JFET current. It may need coarse adjustment at the current source for the amplifier: the current source currently has quite a bit of negative TC, so the current going down with temperature. It may take a diode (or even 2) in series to R22/24/26/28 to compensate.

It is also odd to have kind of parallel current source and separate cascode transistors and still directly couple them. With more like 3 or 4 more separate current paths one could get better current sharing and better see errors (e.g. no well matched transistors). So each of the cascodes (Q5,Q10,Q15) could get it's own current source. They would be combined though 3 extra resistor (e.g. 100 Ohms range) before R35.

There is no series element for protection at the input. Connecting to a DC source give quite some current spike, that might damage the protection and possible the DUT. This is kind of a tricky topic, as the protection can introduce noise. So the common way is to have a series resistor that can be bridged with a switch. After the DUT is connected.

[GK]

The power supply section is a possible source of variable heat and should thus be more separated, possibly even using THT power transistors.

The "power supply" is just a pair of so-called capacitance multipliers. The pass transistors are essentially only dropping a potential of one Vbe each. The power dissipation of these two beefy SOT-223 pass transistors isn't even 80mW combined. The majority (by design) of the heat is dissipated in the current source, which is deliberately composed of many series/parallel parts to spread the heat dissipation over a wide area.

I don't think one really needs the trimmer for the output balance - just 2 good resistors should be good enough.
I would more think about a trimmer or optional parallel resistors to adjust the temperature drift, possibly even with the option to go close to zero. There are a few point where one could do a TC adjustment,  e.g. via the exact JFET current. It may need coarse adjustment at the current source for the amplifier: the current source currently has quite a bit of negative TC, so the current going down with temperature. It may take a diode (or even 2) in series to R22/24/26/28 to compensate.

That trimpot allows me to easily trim the common-mode rejection between the LNA and the differential input of my Tek plug-in to much better than what you'd get even with 0.1% resistors. And the temperature coefficient of these resistors is an order of magnitude less of a problem. It's just a "nice" feature to have in certain situations, but most of time the output is most conveniently used single ended.

It is also odd to have kind of parallel current source and separate cascode transistors and still directly couple them. With more like 3 or 4 more separate current paths one could get better current sharing and better see errors (e.g. no well matched transistors). So each of the cascodes (Q5,Q10,Q15) could get it's own current source. They would be combined though 3 extra resistor (e.g. 100 Ohms range) before R35.

It's not odd and your suggested additional complication would be rather pointless as the current "sharing" between the individual cascodes has absolutely nothing to do with the matching between Q5, Q10 and Q15 - except only for differences in hfe, which are totally negligible.   

There is no series element for protection at the input. Connecting to a DC source give quite some current spike, that might damage the protection and possible the DUT. This is kind of a tricky topic, as the protection can introduce noise. So the common way is to have a series resistor that can be bridged with a switch. After the DUT is connected.

This part actually has some sense, but it will take a quite high voltage source to zap a MMBD-7000 through a 1uF cap. For standard DC potentials of around +/- 15V or less, there is not problem at all by a safe margin. For this reason, I did not complicate the design with additional protection circuitry. If you want to measure the output noise of a 400V DC source, then you will need to employ additional precautions.
 

[Gerhard_dk4xp]

I made an op-amp version with ADA4898 roughly based on the 'lono'

You can get the Altium files for the current, still unbuilt version. (only small cleanups
over the version with the large input Cs and their protection circuit)
Requests for improvement could be considered for abt. 4 weeks.
The JFET version has higher priority.

BTW. That's how the previous version of the lono looks like when you remove the
wet tantalum for a test and forget about it when trying to measure the noise
of a Lithium battery.  Good parts recovered, the relays are impossible to remove.

The test was why does the equiv. input noise rise above 500 KHz. It's the layout.
Input voltage was distributed to the 20 opamps with a U-shaped trace.
That was not good enough. Laying it out as a mesh held the noise flat
to 1 MHz.

Cheers, Gerhard

[TERRA Operative]

The clamp isn't symmetrical about ground because the JFET gate potential sits at a few hundred mV negative and needs headroom for the possibility of lower transconductance JFETs or running a lower Id.
The diode of that pair with both A and K tied to ground simply isn't used.

Ah ha, I thought there must have been a reason for it but I couldn't think of why, makes sense now. I learned a new thing today.

When you first apply power don't be alarmed that the output is railed out and that the lower two LEDs aren't initially glowing. That's normal because the JFETs are saturated and grounding the emitters of the cascodes until the servo loop has stabilized the quiescent DC operating point. It takes 30 or 40 or 60 seconds or so. Sorry I don't have a BOM. Don't go changing any resistive dividers or time constants anywhere.

I figured it all out from the schematics. I'm using all 1% 1206 50ppm resistors and haven't changed any values.
I did put the capacitors you mounted point-to-point on the input, output and power jacks, directly on the PCB right next to the PCB mounted jacks I used.
Can you list what values you used, just so I can be in the ballpark?

The board layout looks like it has a few points that are not ideal: the input JFETs are quite a bit spread out and relatively close to the power transistors from the power supply section. The power supply section is a possible source of variable heat and should thus be more separated, possibly even using THT power transistors.
The board looks like there is a ground plane - for good precision one should have a defined ground path for the signal. So R42 should be closely linked to ground of the input terminal. With only 1 Ohms trace resistance can also become an issue.

I don't see the input capacitor C1 - ideally this should be a low loss type like PP. NP0 caps are not yet that practical at 1 µF. So even if most of the board is SMD, I would consider space for a relatively bulk PP film type.

I'll take a look at those points and make some adjustments to the layout. I can probably scrunch up the fets etc a bit that will give me space to move them further from the power supply. Maybe I could break the ground plane between the fets and power supply too, to provide a bit of a barrier to heat conduction as well?
I wonder if a copper heat spreader on top of the fets to help equalise heat between them would make any difference?

As for C1 (and C9), I used an SMD film capacitor, a Wima SMD-PET, 1uF 63 VDC/40 VAC part, but I might bump C1 up to a 250 VDC/160 VAC part to be on the safe side.
The datasheet for this part is linked here, let me know if you think this part is no good.
https://www.wima.de/wp-content/uploads/media/e_WIMA_SMD_PET.pdf

There is no series element for protection at the input. Connecting to a DC source give quite some current spike, that might damage the protection and possible the DUT. This is kind of a tricky topic, as the protection can introduce noise. So the common way is to have a series resistor that can be bridged with a switch. After the DUT is connected.

Would a couple of ohms do it? I won't be testing anything over 100V, my highest voltage PSU that I want to test output ripple on kicks out about 65V maximum.

[GK]

The clamp isn't symmetrical about ground because the JFET gate potential sits at a few hundred mV negative and needs headroom for the possibility of lower transconductance JFETs or running a lower Id.
The diode of that pair with both A and K tied to ground simply isn't used.

Ah ha, I thought there must have been a reason for it but I couldn't think of why, makes sense now. I learned a new thing today.

When you first apply power don't be alarmed that the output is railed out and that the lower two LEDs aren't initially glowing. That's normal because the JFETs are saturated and grounding the emitters of the cascodes until the servo loop has stabilized the quiescent DC operating point. It takes 30 or 40 or 60 seconds or so. Sorry I don't have a BOM. Don't go changing any resistive dividers or time constants anywhere.

I figured it all out from the schematics. I'm using all 1% 1206 50ppm resistors and haven't changed any values.
I did put the capacitors you mounted point-to-point on the input, output and power jacks, directly on the PCB right next to the PCB mounted jacks I used.
Can you list what values you used, just so I can be in the ballpark?

The board layout looks like it has a few points that are not ideal: the input JFETs are quite a bit spread out and relatively close to the power transistors from the power supply section. The power supply section is a possible source of variable heat and should thus be more separated, possibly even using THT power transistors.
The board looks like there is a ground plane - for good precision one should have a defined ground path for the signal. So R42 should be closely linked to ground of the input terminal. With only 1 Ohms trace resistance can also become an issue.

I don't see the input capacitor C1 - ideally this should be a low loss type like PP. NP0 caps are not yet that practical at 1 µF. So even if most of the board is SMD, I would consider space for a relatively bulk PP film type.

I'll take a look at those points and make some adjustments to the layout. I can probably scrunch up the fets etc a bit that will give me space to move them further from the power supply. Maybe I could break the ground plane between the fets and power supply too, to provide a bit of a barrier to heat conduction as well?
I wonder if a copper heat spreader on top of the fets to help equalise heat between them would make any difference?

As for C1 (and C9), I used an SMD film capacitor, a Wima SMD-PET, 1uF 63 VDC/40 VAC part, but I might bump C1 up to a 250 VDC/160 VAC part to be on the safe side.
The datasheet for this part is linked here, let me know if you think this part is no good.
https://www.wima.de/wp-content/uploads/media/e_WIMA_SMD_PET.pdf

There is no series element for protection at the input. Connecting to a DC source give quite some current spike, that might damage the protection and possible the DUT. This is kind of a tricky topic, as the protection can introduce noise. So the common way is to have a series resistor that can be bridged with a switch. After the DUT is connected.

Would a couple of ohms do it? I won't be testing anything over 100V, my highest voltage PSU that I want to test output ripple on kicks out about 65V maximum.

The point-to-point capacitors are just a measure of RFI protection, nothing critical. Just don't use something which will kill bandwidth or add unnecessary input capacitance.

This amplifier uses low-capacitance RF JFETs happy to oscillate at UHF and there is 12 of them in parallel for a huge net input stage transconductance and gain. Don't start tearing up/splitting your ground plane and substituting with point-point spaghetti star earthing thinking this will in any worthwhile way yield better gain accuracy or stability or whatever.

With the BFs my example of this amplifier measured 270pV rt/Hz (input referred) in an A-weighted audio bandwidth. That's equivalent to the thermal noise of about 5 ohms, so you can't put much resistance in series with the input without ruining the ultimate noise performance.
 
BTW, this kind of amplifier is a massive overkill for measuring the output ripple of any typical lab power supply.

[Kleinstein]

RF design likes a ground plane, while the 1 Ohms resistor in the FB calls for a controlled ground path. Chances are one could have both - keep the ground plane for most of the circuit. This also help with an even temperature. Just get R42 close to the input ground, so there is no other current path interfering.

With the SK3557 the input capacitance will be larger. So the tendency for oscillation (and maximum speed) will be likely lower.

Thermal coupling between the FETs is not that critical. It is more the par with the LEDs and transistors for the current sources that should be coupled to the FETs. Thus the idea to have 4 transistors so they can be on different sides. I am still not sure about the overall temperature effect. The current sources will show a significant negative TC. So to get a low overall TC the FETs would need to operate at a relatively high current so that there higher temperature would also cause higher current. So Chances are diode(s) to compensate the TC of the current source could be a good idea.

Splitting the current sources would in deed not help with current sharing, it would only make errors visible. Probably just the resistance of the inductors at the input could be enough to see an imbalance.

[Sylvi]

Hi

I have not read the entire post so maybe my question has been answered:

What is the intended application for this circuit?

[TERRA Operative]

One application is increasing the amplitude of small signals by a known amount to make measurement and display easier, then you divide your results by the known gain of the amp and you have your actual signal.

BTW, this kind of amplifier is a massive overkill for measuring the output ripple of any typical lab power supply.

Yeah, it's just one of the uses I'll put it to. But when it comes to test & measurement, overkill is always more fun.

[TERRA Operative]

Alrighty, I've had a bit of a bump around with the layout.
I scrunched the FET's up a bit and moved them further away from the power supply section, moved R43 right near the input jack and fattened up the traces too, uprated C1 to a 250VDC film cap, and tweaked a few other bits and pieces around the place too.

Hopefully that looks good enough to use now?

[awallin]

What is the intended application for this circuit?

if you want to verify the performance [1] of a low-noise part like a good voltage-regulator [2] - then the voltage regulator spec of 2 nV/sqrt(Hz) is just around twice the noise of a 50-ohm termination resistor - so you need an amp like this in front of your spectrum-analyzer/scope/DMM.

the applications are limited by the need for a low source impedance. any sensor or source with a large output impedance will be much noisier than the LNA..

[1] https://www.analog.com/media/en/technical-documentation/application-notes/an83f.pdf
[2] https://www.analog.com/media/en/technical-documentation/data-sheets/3042fb.pdf

[Kleinstein]

The ground plane on the bottom side look horribly fragmented. This is no longer a working ground plane.

The supply is supposed to be at some +-15 V with already good regulation (except for the filter caps the PSRR is not expected to be very good).
With a +-24 V supply chances are the heat production could be a little high in some cases. I would more prefer a lower supply - not sure how low it can be, but it may work with some +-12 V and maybe with +12 V and only -5 V.

For the input capacitor, the question is not if 40 V or 200 V polyester. The question is more if a polyester cap is good enough: due to the DA the initial settling can take quite a while. With a PP cap the settling could be faster.

[TERRA Operative]

The original design didn't have a ground plane on the back at all, is it better to have none rather than one that is a bit cut up? I have vias everywhere stitching the top to bottom ground planes so there aren't any 'tails' that might act as an antenna as such (pending any I missed). Maybe a 4 Layer board would give better results?

Good catch on the 24V, that's a typo on my part. I was playing with some 24V SMPS modules for another project and had that number on the brain. It's been corrected to 15V now.

For the 1uF capacitor, would the couple tenths of a percent difference make much difference? I assumed it would have been small enough to not be too bad (I'm certainly no expert though...)
How about a PPS capacitor like this? PPS seems to have a similar dielectric absorption to polypropylene.
https://www.wima.de/wp-content/uploads/media/e_WIMA_SMD_PPS.pdf

[Sylvi]

Hi

I actually wanted to hear from GK since he is the one that started this thread and presumably he is the one with the need for this amplifier?

I know any basic building block with gain can be used for a wide variety of purposes.

What is GK's purpose for it?

[Kleinstein]

I don't think one would need a 4 layer board. Some vias to connect / patch the ground plane should be enough. One may a reduce the fragmentation if needed.

The expected effect of a MKS type or similar capacitor is that after a larger voltage jump, one would see some low  DC / very low frequency drift over quite some time of maybe 1-10 minutes - more than the normal RC time constant. This may be acceptable, as warm up would take longer anyway. Fast moving a probe around can be tricky anyway due to the large capacitance.

For the PPS capacitor the loss factor looks good. However I remember somewhat conflicting results on DA in PPS. DA is not is not fully characterized by a single number, but is also frequency dependent. AFAIK PPS is good at some frequencies and not so good at others.
In theory also some NP0 caps can have very low loss. However I don't know the large ones and 1 µF would need something like 10 x 100 nF in parallel. Also not all NP0 are equal.

It could still be worth to have the option to use PPS if MKS is giving to much DA effect after a jump.

It really depends on the usage, but other similar amplifiers often include some series resistor at the input to limit the current when charging the capacitor.  So something like 5 K in parallel with a switch to turn of the extra protection. A 1 µF capacitor could be too much for some circuits to measure (the typical LTZ1000 reference circuit would no like connecting this amplifier).

As the shown amplifier is relatively fast, it may be suitable to use with a scope. The LF performance depends on the FETs. The use for LF noise (e.g. voltage references) may be limited, not really bad, but still with some 1/f noise.

[TERRA Operative]

I don't think one would need a 4 layer board. Some vias to connect / patch the ground plane should be enough. One may a reduce the fragmentation if needed.

The expected effect of a MKS type or similar capacitor is that after a larger voltage jump, one would see some low  DC / very low frequency drift over quite some time of maybe 1-10 minutes - more than the normal RC time constant. This may be acceptable, as warm up would take longer anyway. Fast moving a probe around can be tricky anyway due to the large capacitance.

For the PPS capacitor the loss factor looks good. However I remember somewhat conflicting results on DA in PPS. DA is not is not fully characterized by a single number, but is also frequency dependent. AFAIK PPS is good at some frequencies and not so good at others.
In theory also some NP0 caps can have very low loss. However I don't know the large ones and 1 µF would need something like 10 x 100 nF in parallel. Also not all NP0 are equal.

It could still be worth to have the option to use PPS if MKS is giving to much DA effect after a jump.

It really depends on the usage, but other similar amplifiers often include some series resistor at the input to limit the current when charging the capacitor.  So something like 5 K in parallel with a switch to turn of the extra protection. A 1 µF capacitor could be too much for some circuits to measure (the typical LTZ1000 reference circuit would no like connecting this amplifier).

Cool, I have a bunch of vias around, I'll be a little more liberal with them, and have a go at tweaking the layout to try to minimise the fragmentation.

I was just thinking designing in to have options would be the way to go with the capacitor too. A dual footprint so I can mix and match and see what works best for my use case.

I'll add the resistor and switch too. At the very least I can just not solder them in if I don't end up needing them, but at least the option is there if it is needed. Better to have it and not need it than the other way around.