Who cares bout jitter on the bclk, as long as worst case it meets setup and hold timing everything is fine (Digital is nice like that).
In an R2R or similar simple minded DAC it is jitter on the LRClk that makes it to the output, but that signal is fairly slow so it is clearly going to be mainly additive jitter from the divider chain here assuming a suitable VCXO (Phase noise drops by 6dB with every divider stage).
In a delta sigma design (Most of which are not in fact 1 bit in any meaningful sense) it is the modulator clock that is critical and this is actually harder because it is much faster, 12Mhz or so typically against 48KHz or so for the LRclk.
All of this is standard stuff and the equations are well defined for any given performance target, the debate is not one of engineering but of the human physiology and what the targets for system performance should be (A FAR more interesting question, and one warranting actual research).
The time domain is getting some play recently as there is some evidence that the ear may have a distinct set of hardware that detects transients and this may actually have better temporal resolution that the ~20KHz bandwidth tone detection capability would imply, the jury is out, we will see as some more experiments are done.
Regards, Dan.