Do you have a timing diagram or state diagram, or even a word description of what this circuit does?
When I simulate it, it appears that in some states the flip-flops set and then reset themselves.... assuming a gate delay this creates a very poor quality oscillator. Is that your intent?
For outputs you should consider a different label, perhaps "OUT1" and "OUT2". A* and B* traditionally would refer to inverted versions of your A and B signals respectively.
Hi,
for a project, i need some simple logic which i'm trying to minimize. There are only two inputs, A and B and two outputs, A* and B*. Stage 1 in the screenshot are basically 4 R-S Flip Flops (2 74HC00) if that helps and stage2/output is a single 74HC08. I've done some theoretical logic minimization in college but can't seem to find a way to use only two, or possibly one IC.
Can anybody help?