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Offline daywalkerdhaTopic starter

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« on: May 10, 2013, 08:01:16 pm »
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« Last Edit: October 30, 2022, 01:59:13 pm by daywalkerdha »
 

Offline mikes

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Re: Minimizing Logic Gates
« Reply #1 on: May 10, 2013, 08:17:07 pm »
Rather than making us figure out what it does, why don't you describe what you want it to do? Is speed critical?

You could use an 8 pin PIC microprocessor (12F508?) to mimic any (?) 2 in 2 out logic circuit. Just not sure if it would be fast enough.
 

Offline TerminalJack505

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Re: Minimizing Logic Gates
« Reply #2 on: May 10, 2013, 08:22:56 pm »
For discrete logic, using multiplexers is usually the best way to implement truth tables.

The books The Art of Electronics and Practical Electronics for Inventors show how.  I'm sure there are plenty of examples on the web too.

Attached are a couple of examples.
 

Offline ddavidebor

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Re: Minimizing Logic Gates
« Reply #3 on: May 10, 2013, 08:39:55 pm »
you can use a 3 bit multiplexer.

you only need to do your equation in the form where you have all the variable in all the term like
abc+abc+abc+abc+abc+abc+abc+abc (obviusly some are negated)

next you have your multiplexer that has 8 input that correspond to binary

abc
000
001
010
011
100
101
110
111

so when you see zero it's the variable negated , when you see 1 is normal

just short to vcc the term you need and to gnd the other

David - Professional Engineer - Medical Devices and Tablet Computers at Smartbox AT
Side businesses: Altium Industry Expert writer, http://fermium.ltd.uk (Scientific Equiment), http://chinesecleavers.co.uk (Cutlery),
 

Offline ddavidebor

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Minimizing Logic Gates
« Reply #4 on: May 10, 2013, 09:16:22 pm »
Go for the mux, you'll need only one chip and super simple pcb design
David - Professional Engineer - Medical Devices and Tablet Computers at Smartbox AT
Side businesses: Altium Industry Expert writer, http://fermium.ltd.uk (Scientific Equiment), http://chinesecleavers.co.uk (Cutlery),
 

Offline nctnico

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Re: Minimizing Logic Gates
« Reply #5 on: May 10, 2013, 10:24:59 pm »
Or use a GAL16V8. Back in the old days I used these for all kinds of odd logic handling. Just write a few simple logic equations and done (let the software deal with optimisation). Even stuff like single push-button on/off is possible. If the customers wants it different then its just a matter of reprogramming.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline MasterOfNone

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Re: Minimizing Logic Gates
« Reply #6 on: May 10, 2013, 10:45:33 pm »
There you go then, I can’t seem to get it simpler that this ;)
 

Offline electronupdate

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Re: Minimizing Logic Gates
« Reply #7 on: May 10, 2013, 11:07:19 pm »
Do you have a timing diagram or state diagram, or even a word description of what this circuit does?

When I simulate it, it appears that in some states the flip-flops set and then reset themselves.... assuming a gate delay this creates a very poor quality oscillator.  Is that your intent?


For outputs you should consider a different label, perhaps "OUT1" and "OUT2".  A* and B* traditionally would refer to inverted versions of your A and B signals respectively.



Hi,

for a project, i need some simple logic which i'm trying to minimize. There are only two inputs, A and B and two outputs, A* and B*. Stage 1 in the screenshot are basically 4 R-S Flip Flops (2 74HC00) if that helps and stage2/output is a single 74HC08. I've done some theoretical logic minimization in college but can't seem to find a way to use only two, or possibly one IC.

Can anybody help?
 

Online amyk

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Re: Minimizing Logic Gates
« Reply #8 on: May 11, 2013, 12:00:46 pm »
My best guess is that it's a phase detector of some sort...

If your simulator's gate delays are all the same then a flip-flop can be made to oscillate. In the real world that's a race condition and it'll probably settle at one state or another randomly.
 

Offline FJV

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Re: Minimizing Logic Gates
« Reply #9 on: May 11, 2013, 02:57:58 pm »
You can do this by using a Karnaugh map / diagram.

A quick search would get you started.

 

Offline codeboy2k

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Re: Minimizing Logic Gates
« Reply #10 on: May 11, 2013, 05:54:10 pm »
Or use a GAL16V8. Back in the old days I used these for all kinds of odd logic handling. Just write a few simple logic equations and done (let the software deal with optimisation). Even stuff like single push-button on/off is possible. If the customers wants it different then its just a matter of reprogramming.

This.  The GALs have long been forgotten in favor of their FPGA big brothers. The little GALs need some love too :)

Is anyone still making them? can you still buy them?? sometimes you don't need a full CPLD , the GALs and PALs can still be useful, but I think no one makes them now.



 

Offline nctnico

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Re: Minimizing Logic Gates
« Reply #11 on: May 11, 2013, 06:26:18 pm »
There are still lots of small CPLDs similar to the old GALs out there from Lattice, Xilinx, etc.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline codeboy2k

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Re: Minimizing Logic Gates
« Reply #12 on: May 12, 2013, 12:53:31 am »
There are still lots of small CPLDs similar to the old GALs out there from Lattice, Xilinx, etc.

Yes, I'm familiar with the MACHXO2 from Lattice, used it in a design once.  But it's still more dense than a GAL.  I have not used the new ICE series from them. Costs are always coming down... if I found a point in a design where I needed just a small logic device, but all I could find was a small CPLD from Lattice, for example, then I would rethink the design to remove even more components and put more into the CPLD



 


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