Mosfet and gate driver turn on/off times

[mbless]

I'm working on a high-power pulsed system and need help understanding the relationship between the turn on & off times of the mosfet and gate driver. Right now I'm considering the DMNH4006SPSQ mosfet and the LM5134 gate driver. The mosfet will be switching a load of up to 100A with variable voltage at 1kHz and 1us pulses (0.1% duty cycle) maximum. The mosfet can handle up to 180A pulsed drain current, so that should be fine.

I'll have a maximum of 1us pulse width, but what I'd like to know is how short of a pulse width I can achieve. The mosfet input capacitance is 2.3nF, so the driver says the output rise and fall time is around 7 and 4ns, respectively. Does that mean the mosfet will turn on and off that fast, or simply that the gate line will change that fast and then the mosfet has to react to that? The mosfet has rise and fall times of 9.3 and 8.1ns with on and off delays of 7.7 and 18.1ns.

Thanks for any advice and help on understanding this!

[Siwastaja]

"input capacitance" is practically a worthless parameter - it applies to very low gate voltages changes near 0V. But the actual gate capacitance is highly nonlinear: when you actually probe the gate voltage, you'll see it will first charge rather quickly, suggesting lower capacitance (actually the "input capacitance" value), but as soon as the MOSFET starts to conduct even a tiny little bit, the gate charging slows down often by almost an order of magnitude. This is because now the Drain-Source is starting to conduct, and the gate is seeing the drain capacitance as well.

After the FET is in near full conduction (switching is mostly done), gate charging speed goes up again; the last few volts here are to ensure the FET is 100% fully switched, with as low Rds(on) as needed by the application.

The datasheet, luckily, gives you the right parameter: it's the Total Gate Charge (Qg(tot)).

Gate driver rise/fall times are also typically specified for smaller loads than the actual mosfet.

You'd need to look at the equivalent driver resistance (seems to be around 0.5 ohm for LM5134), add the external gate resistance and the FETs parasitic gate resistance. Then combine this information with your gate driver supply voltage and the Qg(tot) of your FET, and you'll be close.

For stability, to prevent unwanted oscillations, you may need to add a tiny bit of extra gate resistance, which slows the gate down.

[Rog520]

The best way to determine switching times is to actually measure them in your circuit. But you can do a simple (rough) approximation using Rg (which would be the sum of the output resistance of the driver, the input resistance of the FET, and the external gate resistor (if any)) and Ciss. So, for your example, given a total Rg of 3.5 ohms and Ciss of 2280pF, you'd have a Tg of about 8ns (Tg = Ciss x Rg). In reality the actual turn on and turn off times will vary somewhat based on other factors like the Vgs, the Id, and the propagation delays of the driver. If you want to get more detailed and more accurate (and more complicated!) you can divide the turn on and turn off periods each into several intervals (each interval having its own calculation) and then sum them up. Keep in mind that any additional external gate resistance will tend to make the FET more stable but it will also contribute to increased turn on time (and turn off time unless you bypass the gate resistor with a diode).

Also, it probably goes without saying, but anything you do to slow switching time will increase switching losses.

[T3sl4co1l]

All I have to add to Siwastaja's response: you can calculate an equivalent gate capacitance, Cg(eff) = Qg(tot) / Vg(on).  Qg(tot) is about 50nC at 10V, so Cg(eff) = 5nF, quite a lot more than the Ciss(Vds=25V) value.

Speaking of, the other reason Ciss is useless: it's measured at elevated Vds.  In the VDMOS process (which includes almost every power transistor in current production), Cgs is essentially constant, while Cdg and Cds vary with Vds.  See Fig. 10.  (Ciss = Cdg + Cgs, in case you were wondering.)

Other limits to switching speed: source inductance (particularly between gate driver and MOSFET package), and the driver's internal limits of rise/fall time, propagation delay and minimum high/low pulse width.

I'm not aware of any commercial, in-stock gate drivers that are especially fast (typically 20ns into 1nF)*.  If you need ass-kicking speed, you may find a discrete solution can do better.

*There are IXYS RF parts in flat packs that can do better, but good luck finding them for sale.

Tim

[Rog520]

Speaking of, the other reason Ciss is useless: it's measured at elevated Vds.  In the VDMOS process (which includes almost every power transistor in current production), Cgs is essentially constant, while Cdg and Cds vary with Vds.  See Fig. 10.  (Ciss = Cdg + Cgs, in case you were wondering.)

While admittedly not all that useful in a standalone sense, Ciss (which is the same as Cg) is used as a baseline in more accurate calculations which factor in Vgs, Vds, and Id, where the turn on and turn off transitions are divided into intervals and then summed.

[T3sl4co1l]

While admittedly not all that useful in a standalone sense, Ciss (which is the same as Cg) is used as a baseline in more accurate calculations which factor in Vgs, Vds, and Id, where the turn on and turn off transitions are divided into intervals and then summed.

Referring to the gate charge figure, the bottom segment is steep, corresponding to Ciss at Vds=Vdd.  The flat portion is the Miller plateau, where Vds falls and Cdg is charged (Vgs changes very little, so nearly all the charge delivered during this stage goes into just Cdg).  The final segment is less steep, because Ciss is large when Vds is small.

As you vary Vds, the slope of the first segment changes, and the width of the Miller plateau changes.  The slope of the last segment does not change, because Vds is always zero there.

Suppose you set up the transistor in a constant-Vds fixture (assuming lots of peak current capacity, and adequate damping to prevent oscillation), the Miller plateau goes away (Vds isn't changing) and the slope is constant, depending only on whatever Vds was set.

In any of these configurations, the only case that "Ciss" tells you, is the initial slope in the gate charge curve, and the slope in the constant-Vds fixture only when Vds is as given.

It's one of those, "so yeah, it's a thing, technically", kinds of things.  But yeah, not really all that useful.

On the upside -- since Crss is so much smaller on modern parts (especially RF and GaN), it does at least give you a more honest measure of average gate capacitance, whereas in the old days, when Crss was a sizable fraction of the total, you could expect Ceff about four times (or more) higher!

Tim

[mbless]

Thanks for all of the input! I found this app note from Vishay which has explains mosfet gate charge and derives some transient equations based on Ciss (Cgs+Cgd). Are the equations to be taken with a grain of salt then? They do substitute Ciss for Qgd after the Miller plateau citing Cgd changes with Vds.

The other thing I don't understand is in Fig. 2 they show the peak drain current is reached at the beginning of the Miller plateau but Vds doesn't reach a minimum until the end of the plateau. If I have a simple resistor the mosfet is switching to ground and Vds hasn't changed, how is the current through the resistor already at max value? It seems to me that peak drain current isn't reached until Vds is 0.

[Rog520]

Thanks for all of the input! I found this app note from Vishay which has explains mosfet gate charge and derives some transient equations based on Ciss (Cgs+Cgd). Are the equations to be taken with a grain of salt then? They do substitute Ciss for Qgd after the Miller plateau citing Cgd changes with Vds.

The other thing I don't understand is in Fig. 2 they show the peak drain current is reached at the beginning of the Miller plateau but Vds doesn't reach a minimum until the end of the plateau. If I have a simple resistor the mosfet is switching to ground and Vds hasn't changed, how is the current through the resistor already at max value? It seems to me that peak drain current isn't reached until Vds is 0.

The procedure outlined in the Vishay app note is pretty much the standard way to calculate turn on/off times, although there's a variation that doesn't bother with using Qgd in the t3 interval. Either way, it's an approximation, and only actual in-circuit measurement will take all factors into account to give you the best accuracy.

Cgd is essentially at Vds max (say, 25v) at the start of the t3 interval. As the interval progresses, Cgd is discharging through the gate (and so through gate resistance Rg), during which time Vds will fall, eventually reaching Id x Rds.

[T3sl4co1l]

Cgd varies during t3, so the value used is the average / effective capacitance for Vds from Vsupply to Vds(sat).  This is calculated by taking \$Q_{gd} = \int^{V_{supply}}_{V_{ds(sat)}} C_{gd} dV\$.  Better to just use the gate charge figures in the datasheet, or measure it yourself (which is worthwhile so you know how it's measured, and get to see real spreads in parameters that aren't even measured during test!).

t4 is erroneous, because as said, Ciss is not the datasheet parameter, but the Vds=Vds(sat) value which you have to find in the graph.

Tim