MOSFET may briefly exceed SOA - is this acceptable?

[tom66]

I am working on a linear power supply design using two IRFP150N MOSFETs as the pass regulators.

In a short circuit transient, as the MOSFET gate is discharged, the peak current is 40A and the D-S voltage is about 55V. The peak power is 800W (the peak voltage and current occur at different times.) Within 5us the current returns to the normal limit. The energy dissipated in this transient doesn't exceed 10mJ.

I saw the avalanche energy property has the MOSFET rated at 400mJ, so it looks like it should survive this event... but I am not sure if this applies for non-avalanche breakdown...

[T3sl4co1l]

Where's the 10us SOA?  It's going to be nearly square, isn't it?

Tim

[Smokey]

The thermal constants of a device are like a bunch of RC lowpass filters.  Some datasheets even list the thermal constants in terms of RC values.  That should give you a good idea if your pulse duration will overheat the die.

[rs20]

The thermal constants of a device are like a bunch of RC lowpass filters.  Some datasheets even list the thermal constants in terms of RC values.  That should give you a good idea if your pulse duration will overheat the die.

These thermal RC values are not relevant to avalanche breakdown -- as explained by the reference in reply #2, avalanche breakdown occurs in a different part of the die.
EDIT: Ignore me, I'm just not paying attention. The RC lowpass filters are perfectly applicable.

[Smokey]

Sure, but was the OP necessarily talking about an avalanche event?  It sounded like he was just talking about a high power transient that was in excess of the DC SOA.  In that case the die temp change would still follow the thermal RC pattern.

[rs20]

Sure, but was the OP necessarily talking about an avalanche event?  It sounded like he was just talking about a high power transient that was in excess of the DC SOA.  In that case the die temp change would still follow the thermal RC pattern.

Whoops, seems like I can't read :-) I stand thoroughly corrected.

[Smokey]

Heh!  You had me re-reading the above posts a couple times trying to figure out what I was missing

[salbayeng]

I'm a bit confused, the datasheet has different curves on the SOA for different length events, and your values are under the 100us curve so you are OK (by a factor of 20?) , oh and actually these are at 175C. 

I also see you have compared your pulse energy with the avalanche energy, I had never thought to do that, and it would seem an interesting approach, given that thermal heating is more benign than avalanche heating (the latter is limited by localised hotspots and thermal runaway).
I would adapt your method however: you note a 10mJ energy pulse  , so if we were to assume the transistor was already hot at the time of the transient, then the repetitive avalanche energy would be a better benchmark,  which is 16mJ.  So if the device can survive being hammered with 16mJ , your 10mJ transient is'nt going to bother it.

In general, You need to be a little careful about the "single pulse" data,  You can't operate to the edge of this SOA once every day and call it a "single pulse"  Realistically you might get 200 "single shots" before failure. I read a research paper on this recently,  its a problem of thermo-mechanical cycling and short-cycle fatigue, the metallisation literally cracks up, but the stresses in the silicon actually shift the devices operating parameters (e.g. V_th, V_br and I_l ) . And they were able to measure the "premature aging" of the stressed devices vs control specimens.

OK with a bit more reading I can see the data sheet is a bit confusing, it lists 42A as the continous rating,  but clearly 42A x .038ohms is only 63Watt , so the 42A is a "design to" rating ,  Confusingly it mentions 140A as the pulsed repetitive rating,  yet the SOA shows 140A as "single pulse".

The other thing to watch (particularly when you have some of the low R_on SMD packages ) is the fuse rating of the bond wires, (typically 100-120Amps).  The IRFP150N is in TO247 so fuse rating around 150A?

Gate drive: look at T_d(off) , page 2  this is 3.6ohm for 90ns total off time , if you want a  5uS turnoff then the effective gate driver resistance/impedance needs to be less than 70ohms.

[tom66]

Thanks for all the information. So it looks like I should be OK with this.

A few notes, this is a linear power supply design, 0-40V output, 0-5A load range, CC/CV control loop. There is a tap-changer before the MOSFET which selects lower taps on the transformer as the output voltage decreases to reduce power losses in the pass FETs. The worst case DC dissipation will be about 47 watt per transistor, the heatsink will also be air cooled.

The gate of the FET will be driven by a high-speed high-voltage op-amp (0-65V swing); the limiting factor is the control loop speed and the slew rate of the driving op-amp. When entering constant-current limit, the constant-voltage error amplifier overshoots slightly, which leads to a little bit of "slop" in the error voltage. This delays the turn-off of the FET driving into short circuit. I was hoping to stay with TL072s rather than use a faster op-amp.

One of the design decisions I've made is to minimise the output capacitance as much as possible to give the PSU a good response to short circuit.

[dannyf]

The gate of the FET will be driven by a high-speed high-voltage op-amp

Unless (extremely) carefully implemented, that sounds like a recipe for disaster.

[tom66]

The gate of the FET will be driven by a high-speed high-voltage op-amp

Unless (extremely) carefully implemented, that sounds like a recipe for disaster.

High speed being relative, it's the LTC6090 which is a 12MHz device.
So far, it works in simulations. Obviously, it needs to be shown to work for real, as well.

[David Hess]

Warning: excessive rambling below.

The gate of the FET will be driven by a high-speed high-voltage op-amp (0-65V swing); the limiting factor is the control loop speed and the slew rate of the driving op-amp.

Large gate capacitance (it might be easier to think of it as gate charge) will cause slew rate limiting slowing recovery time.  You can improve the performance by buffering the operational amplifier output with a simple discrete current amplifier.  Unloading the error amplifier output also improves settling times by preventing thermally induced errors but that is seldom important in power supplies.

When entering constant-current limit, the constant-voltage error amplifier overshoots slightly, which leads to a little bit of "slop" in the error voltage. This delays the turn-off of the FET driving into short circuit. I was hoping to stay with TL072s rather than use a faster op-amp.

There are two interrelated problems here.  If the operational amplifier is fast enough, then it will require external frequency compensation to remain stable which usually takes the form of an integrating capacitor.  When the voltage or current loop is open, the integrating capacitor will charge up which significantly increases the recovery time because the operational amplifier will have to discharge it once the loop is closed again switching between modes.  So using a faster amplifier is self defeating if more frequency compensation is needed to make it stable.

Solutions to this include actively or passively clamping the integration capacitor (sometimes this is called anti-windup) and minimizing the integration capacitance.  The later can be accomplished by adding phase lead to the feedback network.  In simple designs, the solution is not to use an amplifier which is faster than necessary.

Incidentally, I like using LT1007/OP-27 type operational amplifiers in these sorts of applications for low noise and good load regulation but their speed requires careful attention.  In a general purpose bench supply they probably cause more problems than they solve and something like an LT1001 would be better.  Some amplifiers like the LT1097 and OP-97 are especially useful because of their support for overcompensation.  Very few applications need anything better than a 301/741/324 though.  I only mention the 301 because it used to be uniquely useful for high side current sense.

One of the design decisions I've made is to minimize the output capacitance as much as possible to give the PSU a good response to short circuit.

This is one of those traits which distinguishes good power supplies from bad power supplies.  Excessive output capacitance is a crutch which causes more problems than it solves.

[nctnico]

I am working on a linear power supply design using two IRFP150N MOSFETs as the pass regulators.

In a short circuit transient, as the MOSFET gate is discharged, the peak current is 40A and the D-S voltage is about 55V. The peak power is 800W (the peak voltage and current occur at different times.) Within 5us the current returns to the normal limit. The energy dissipated in this transient doesn't exceed 10mJ.

I saw the avalanche energy property has the MOSFET rated at 400mJ, so it looks like it should survive this event... but I am not sure if this applies for non-avalanche breakdown...

The avalanche data is for the diode parallel to the MOSFET in case of overvoltage (clamping) situations. That doesn't apply to your situation. You have to stick with the SOA characteristics of the device. That shows that it would be OK for a single MOSFET to handle 40A at 55V for 5us.

[salbayeng]

David Hess has a lot of good points there.
With power supplies less (gain) is more.

MOSFETS can be cantakerous when driven in linear  mode, you might get lucky!
If your gate resistance is too low, and source inductance too high it is very easy to accidentally build a 100W radio transmitter, a ferrite bead on the source lead usually stops this.
A current amplifier after the opamp need only be a pair of complementary emitter followers, you buy these in a T0-23-6 package, or just use BC337/BC327.
As a starting point, when you put in the local feedback on the opamp, connect the feedback  R to the emitters, and the C to the bases , this will decouple the capacitive load the opamp sees.
Don't forget the 12v zener across G-S on the MOSFET.