On power supply sequencing

[Alex Eisenhut]

This is more or less new to me. I know that there seems to be more supply rails than ICs on PCBs these days, and now I want to figure out how to sequence all these guys properly, or how other people do it.

1) In general is there some sort of algorithmic way to figure it out? So far all I've done is draw a tree to show the distribution from the main input to each rail.
2) Then there's the temporal relationship between the various rails.

In a mixed signal system, suppose there are some ADCs talking to a FPGA through some level translators. The ADCs need some analog VCCs and a digital VCC. There isn't any specific power-up diagram in the datasheet of the ADC I'm looking at but there are some interesting dependencies in the abs max ratings.

I don't even know what my question is anymore.

I mean I've looked at how other people do it (the sincerest form of flattery they call it), for example the 150-0320305-revd.pdf

www.linear.com/docs/45263

anyhoo page 2. See the nice clouds on the left and the sequence on the right? I've got something twice as large to work on.

I have yet to see any CAD package address power sequencing the same way they address signal integrity or FPGA pin assignment. Is there such a thing, and if not, who wants to start a business with me?

[georges80]

The last complex digital design I did late last year had a large Marvell SOC that had multiple supply rails (about 8 of them) and the data sheet explained the sequencing requirements with min/max timing of the various domains.

There were about 7 switching regulator supplies on the board and another 5 or so LDOs. By choosing switchers that had soft start control signals and specified power up timing specs I was able to set them up to provide the appropriate sequencing along with the use of LDOs in some key locations.

This was a pure digital design with the only 'analog' signals being dealt with by some audio codecs so still essentially digital.

I don't know of any tools and can't imagine how they would integrate in since a lot of the specs are dependent on the chips you are using and in our case some of the chips are proprietary (ASICs) and wouldn't be supported by a 3rd part tool vendor anyway.

Seems to me it is part of the design process and isn't really that hard to do.

cheers,
george.

[Alex Eisenhut]

Seems to me it is part of the design process and isn't really that hard to do.

cheers,
george.

Sure, if the datasheet for the one device has a sequence to follow. What if it's an ad hoc bunch of parts?
Some regulators have SS, some don't , some have power good output flags, some don't.
Some of them are interdependent, some aren't. etc.

[georges80]

... and that's your job as a designer to select appropriate switchers/regulators to achieve the necessary power sequencing. If the datasheet of IC xyz doesn't specify power sequencing requirements, then likely it isn't important (if it was then it SHOULD be documented) and if you are worried then contact the manufacturer for clarification.

The Marvell SOC (568 pin bga) I had to use is one of the first parts that had specific sequencing requirements versus the other parts on the board (ASICs, HDMI encoders, USB hubs, gige etc).

cheers,
george.