Oscillating Op Amp Amplifier

[Charles Creations]

Hi Everyone,

I am having issues with an Op Amp circuit oscillating. It is perfectly stable when the digital potentiometer is set to low gain (its a 10K dig. pot. with 8 bit resolution, low = less then 75/256). Once the gain rises above 100/256 the first stage goes into periodic oscillation. I have attached screen shots below.

What gets me, is that the digital pot. is in the second stage but its the first stage that starts oscillating. I have three identical SMD circuits of this design, and all oscillate in the identical way. So I am certain its a design issue and not a connection issue. The other odd thing is that the oscillation has a relatively small amplitude. This may be because of its high frequency and the op amp just can't oscillate full scale at that frequency.

Details:

OpAmp - TLC2274
Vcc - 5V with some ripple shown in the attacments
Transducer - Ultrasonic transducer is picking up echos
Oscillation Frequency - around 240KHz

Explanation of Attachments:

"Amplifier" This is the schematic of the design.
"Amplifier1" This is a screen shot of a signal starting an oscillation. The blue trace is measured at point S1R1 on the schematic above. The yellow trace is measured at Vcc (note some ripple).
"Amplifier2" This is a screen shot of a different signal starting an oscillation. Same trace as above.
"Amplifier3" This shows a signal ending an oscillation. I purposefully made a large echo shown center of screen to show the stopping of oscillation.

[T3sl4co1l]

This might be a bit easier to view on the forum.  I didn't bother to fix the JPEG artifacts though...

Tim

[Charles Creations]

This might be a bit easier to view on the forum.  I didn't bother to fix the JPEG artifacts though...

Tim

Thank you for formatting that.

[T3sl4co1l]

Does the transducer by any chance happen to have an impedance vs. frequency curve?

TLC2274, isn't that one of the shitty earlyish CMOS amps that does bizarre things with respect to input common mode voltage?  Maybe not.. circuit seems normal and curves don't seem to suggest anything.  But they don't happen to show much with respect to V_IC, so I don't know...

(I'm partial to TLV2372 myself, which seems to do well for any common mode voltage.  RRIO.  Input offset shifts slightly for V_IC > Vdd-1.5, that's about it.  Comparable specs (Vos, Iout, GBW..) otherwise, though noisier.)

Digital pots are a *really* bad thing to put in a feedback loop.  You're dumping capacitance from -in straight to GND.  No problem getting instability going.  As for measuring it on the proceeding output terminal... the output impedance is a long shot away from the ideal op-amp at higher frequencies.

Op-amps aren't really the best choice here, anyway.  You need to burn so much GBW, for so little actual bandwidth.  That said, performance is usually okay against supply current and cost, so no one really cares...

What's the frequency and bandwidth of that sensor?  40kHz?  250kHz?  40kHz with a gain of ~50 requires GBW > 2MHz, so these amps are operating nearly open loop (not that distortion matters much, but you'll at least have less gain than you were expecting).  You'll run into slew rate limiting pretty easily, too.

I would just as well do the whole thing with a couple of BJTs, maybe a JFET for low noise front end and/or variable gain (assuming your digital pot doesn't need to be calibrated or anything).  Tuned amplifiers wouldn't be the most convenient (you'd need maybe 1-10mH chokes with < 30 ohm DCR), but would be the way to go, in principle.

Tim

[f5r5e5d]

100 pF series with 1K into a virtual gnd?  - that's ~1.6 MHz high pass corner? - not at all commensurate with op amp GBW and feedback R

with largely capacitive reactance to AC gnd in the feedback lower leg you do need local feedback C across op amp -in and output or much, much lower feedback R

[kjs]

you have a tremendous amount of gain in that circuit (quick calc ~150dB) and above a certain setting the feedback from output to input may be just enough to make it oscillate. Ground and supply routing as well as decoupling are for sure critical there.

[smjcuk]

AN148 for the win: http://cds.linear.com/docs/en/application-note/an148fa.pdf

Tripped over this a few weeks ago due to a similar problem. Very helpful.

[w2aew]

Is what kind of bypassing do you have on the 2.5V reference that each stage is referenced to?  With that kind of gain, any coupling to that reference node can potentially be a source for positive feedback...

[Kevin.D]

I think this might be the digital pot's parasitic  capacitance to gnd (or it has insufficient BW ) and causes phase lag at the inv term of the second opamp. Try adding a cap (Cf)  start from ~5pF first and increase, placed from this Opamp output to it's inv input (so you bypass both r52 and digipot with it) to see if it helps  .
If it's this then because you cant really have an optimal size for a compensation cap here (since you will be adjusting the gain ratio's but this cap will be fixed so it will be under compensated at lower gains or over  compensated at higher gain setting.) to size I would  turn gain to max and size cap until you just about get clean response (no ringing) at the output of this amp when you wiggle the input ( input a fast rising pulse signal into just this stage and observe response).
Hope this helps .

[Charles Creations]

Thank you for all the answers. I will address them one at a time:

Does the transducer by any chance happen to have an impedance vs. frequency curve?

See the attached "CurrentVSFrequency." Such a curve is not available on the datasheet (See: http://www.mouser.com/Search/ProductDetail.aspx?R=255-400PT160-ROXvirtualkey12800000virtualkey255-400PT160-ROX). The curve I plotted in the attachment was for a constant drive voltage (30V) and measuring the RMS current supplied. The circuit was a N-Channel FET on the low side of the transducer, pulling it to ground, and on the high side the transducer was attached to the 30V rail with a 1K resistor to pull the lower leg back up from ground when the FET turns off. As such, the resistor's current drain is significant, but this was just a test setup.

What's the frequency and bandwidth of that sensor?  40kHz?  250kHz?  40kHz with a gain of ~50 requires GBW > 2MHz, so these amps are operating nearly open loop (not that distortion matters much, but you'll at least have less gain than you were expecting).  You'll run into slew rate limiting pretty easily, too.

I would just as well do the whole thing with a couple of BJTs, maybe a JFET for low noise front end and/or variable gain (assuming your digital pot doesn't need to be calibrated or anything).  Tuned amplifiers wouldn't be the most convenient (you'd need maybe 1-10mH chokes with < 30 ohm DCR), but would be the way to go, in principle.

Tim

The frequency is 40kHz, and my gain is about 35 for each stage with the 47k resistor.

100 pF series with 1K into a virtual gnd?  - that's ~1.6 MHz high pass corner? - not at all commensurate with op amp GBW and feedback R

with largely capacitive reactance to AC gnd in the feedback lower leg you do need local feedback C across op amp -in and output or much, much lower feedback R

The interesting thing is that this circuit worked perfect in a breadboard test. If anything, I would have expected the breadboard to perform worse, but in the end, it needs to work in its SMD version.

you have a tremendous amount of gain in that circuit (quick calc ~150dB) and above a certain setting the feedback from output to input may be just enough to make it oscillate. Ground and supply routing as well as decoupling are for sure critical there.

Yes, the gain is very high because the incoming signals are very weak, and these op amps are near their limit. However, how could this circuit perform worse in the SMD version then the breadboard prototype when the SMD version has much better parasitic properties?

Is what kind of bypassing do you have on the 2.5V reference that each stage is referenced to?  With that kind of gain, any coupling to that reference node can potentially be a source for positive feedback...

That is a great point. There is limited decoupling because my 2.5V reference can't tolerate too much capacitance on its output. Its a LT1009. Perhaps, I should buffer it.

I think this might be the digital pot's parasitic  capacitance to gnd (or it has insufficient BW ) and causes phase lag at the inv term of the second opamp. Try adding a cap (Cf)  start from ~5pF first and increase, placed from this Opamp output to it's inv input (so you bypass both r52 and digipot with it) to see if it helps  .
If it's this then because you cant really have an optimal size for a compensation cap here (since you will be adjusting the gain ratio's but this cap will be fixed so it will be under compensated at lower gains or over  compensated at higher gain setting.) to size I would  turn gain to max and size cap until you just about get clean response (no ringing) at the output of this amp when you wiggle the input ( input a fast rising pulse signal into just this stage and observe response).
Hope this helps .

Awesome suggestion. I will post my results when I try this.

[f5r5e5d]

with largely capacitive reactance to AC gnd in the feedback lower leg you do need local feedback C across op amp -in and output or much, much lower feedback R

The interesting thing is that this circuit worked perfect in a breadboard test. If anything, I would have expected the breadboard to perform worse, but in the end, it needs to work in its SMD version.

if you used a solderless breadboard with 5 pin spring strip contacts then you had a few pF built in parasitic C between -in and output in a dual or quad op amp package (and every other adjacent pin pair)

even in smt its often possible to patch in a component or a gimmick: https://www.google.com/#q=gimmick+capacitor+twisted+wire&spell=1

[Charles Creations]

So I tried out a few fixes, and I have a winner.

I added a 22pF capacitor across the feedback resistor (R34 in the first post diagram). This stabilized the oscillation all the way up to the max setting on the digital pot. However, it did decrease the bandwidth a bit, so I am still working on fixes for that.

Is what kind of bypassing do you have on the 2.5V reference that each stage is referenced to?  With that kind of gain, any coupling to that reference node can potentially be a source for positive feedback...

In regards to this comment above, could I use the input capacitance (about 8pF for the TLC2274) to form a low pass filter for my bias voltage (Vref)? Basically, I would just add a series resistor of around 1k that attaches to the non-inverting input. The cut-off frequency is too high for 1k (around 19MHz), so maybe a larger resistor.

The biggest problem with decoupling the reference voltage is that the LT1009 looses stability with any significant capacitance on its output, but maybe a series resistor with the capacitor would move that pole further out to avoid the stability issues.

A useful resource for solving these problems has been "Op Amps for Everyone" by TI:
http://www.ti.com/ww/cn/uprogram/share/operation_080625.pdf

Aside from power consumption, what are the disadvantages of decreasing the size of my resistors? I would maintain the same ratio for the correct gain, but lower resistor values would decrease the impedance and help out with stray capacitance destabilizing the op amp at high gain.

Any advice on whether I should remove the ground plain under the op amp to reduce capacitance? I realize the ground plane is a benefit for noise issues, but when stability is key and the board will be contained within a EMI shielding, is it worth removing the ground plane?

[T3sl4co1l]

Ground plane is always a good idea.  Probably not too much difference at these frequencies and impedances, really.

The only place you'd pull back ground plane is around the -in nodes, to reduce parasitic capacitance.  An inner copper ground might give you another pF on the node, which is significant for 100MHz+ amps, but won't make a difference here (as you note, the pins are already ~8pF -- though they don't say what that's relative to, be it pin-to-pin, pin-to-ground, or some combination inbetween).

Capacitance on -in isn't necessarily fatal, anyway; I've used it before (or an R+C to ground) to improve RFI hardness, or peaking the frequency response (not so much reducing the phase margin, as optimizing it).

Regarding the VREF node, you can use a series resistor to decouple the op-amp output from the (now able to be much larger) bypass cap.  This ruins DC correctness, but if you don't need much or any DC current, that's fine; if you do need it, then you can move the feedback path to the bypass cap as well.  Now you need a series R in the feedback path, and a bypass cap from output to -in, to compensate it.  The Rout-Cbyp and Rfb-Cfb time constants need to be more-or-less complementary, otherwise you get a big spike in the output impedance, or instability in the amp.

Tim