Hello
I want to possibly make this a commercial product ... so I can't really source out older mosfets. I was recommended the BUK956R1-E100 but it's no longer manufactured. The fets will be in thei linear region for the most part, so they need balancing, but as I said, it cannot be done using the micro controller ... I.e sensing current through each one and providing a different gate drive voltage. I was recommended to put a gate resistor, a source resistor and a NPN transistor at the gate to actively balance the fets, something similar to this:
Does this work with the newer mosfets you mentioned? otherwise can you recommend mosfets that can be purchased in bulk and still work fine with this method? or if there's a better method which works with the newer mosfets?
That kinda thing could work but not with the configuration and values shown above. The idea is that the gate bjt's
amplify the effect of the balancing source resistor. There is no amplification provided here with the values
shown (Av ~ Rc/Re) so these bjt's are ineffective, also they would be more suitable if configured in a
differential configuration (that is sharing a common emitter resistor like in a LTP) rather than individual
common emitter amps as shown above which limit's the min size of Re and thus voltage gain and would also amplify
supply noise (if it had any voltage gain in the first place).
Even then I would say considering the extra components this method requires the alternative method of providing an
opamp (quad op's are inexpensive) to drive each MOSFET individually is preferred , It's not that much different in
cost/space and would also have a better performance since we are multiplying available drive current rather than
dividing it.
The two factors to consider which contribute to MOSFET imbalance are
1/ initial Vgs(th) spread due to manufacture process
2/ reducing Vgs(th) due to neg temp co.
Max initial Vgs(t) variation would be the deciding factor in minimum dc voltage gain required if trying to use
diff amps to balance FETS .
A small die is harder to cool but ends having lower on resistance, so thats why is good for switching and bad for linear.
I don't think smaller die gives lower resistance, I'd say the opposite (think of a big mosfet as an array of small ones). It's just the advance in technology makes it possible mosfets with the same Rds, but smaller.
I think bigger dies increase chances to have local defects and non-uniform area which I believe contributes to Spirito effect (due to single local hot-spotting). But I can't really support my point of view.
So, how big linear fets avoid this problem? AFAIK they deliberately made cell array very non-uniform (with different Vgs(th)) so to avoid a single hot spot. Instead there are multiple small hot spots evenly spread all over the die which is safe because the whole heats evenly. I think I read about this in an IXYS datasheet.
Whats impressive about these IXYS MOSFETS is that they achieved it whilst still keeping a relativley high gfs
(because lower gfs MOSFETS are more thermally stable anyway) . I also read that article about how IXYS achieved
it and 'by variation in cell density' I think they meant they reduced the cell density (or make the vgs(t) of
cells higher) at certain places on the die that are susceptible to overheating and thermal runaway (like at the
edges of the die or maybe near the pin connections where current density is highest) these are natural hot spots
and failure points I would guess. Since large gfs values aren't really required for a current sink though there
are plenty of cheaper alternatives you can use in your Eload. Also some of these IXYS mosfets have very large
Cgd (Crss) values particularly when operating at very low Vds, this makes them unsuitable for Eloads which have
to operate right down to 0V input.
Regards
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