PCB 2 layer plane design

[DanielS]

That's why you cannot control return current on a doublesided board. The thickness of the material makes it so that you need traces that are 3mm or more wide to get the effect.

That sounds like more than enough to allow routing like signals together (e.g., differential pairs), and orders of magnitude sufficient to, say, build a dirty digital circuit on one side of the board, and a quiet analog circuit on the opposite side (say 10 * 3mm away).  Without cutting the ground plane.

That depends a lot on the nature of the noises you are dealing with and whether or not your analog stuff is sensitive to its characteristics. A large ASIC or FPGA generating 20mV of ground bounce due to combined IO and internal switching is a plane-wide wideband noise source; it will induce both common-mode and differential-mode noise in analog circuitry which are nearly impossible to get rid of without splitting the plane. (It can be done with via-stitching but you need RF engineering to make sure your stitch pattern will block all the frequencies you want to get rid of... and all that stitching adds so much impedance discontinuity to the ground plane, you might just as well gap it and spare yourself the RF math.)

[T3sl4co1l]

You mean, using the top side for VCC and the bottom for GND (or whatever)?  Where would signals go?

I normally route two-layer boards as full ground pour, stitched, with signals routed on the top where possible, and supplies on the bottom (invariably, some of both becomes necessary, but that's fine).

I'd kind of like to do a two layer, plane-pair type layout some time, but I can't convince myself that it's worth even trying.  As soon as you run just one trace, at all, anywhere, you have to stitch the same-layer plane by popping vias to the opposite side and making jumpers.  Repeat periodically along a bus, and then further, for each bus.  Then do it again for the opposite layer.  If nothing else, I'm sure you'd waste enough space routing it, that for the area savings versus stackup cost, it'll be cheaper to do it in 4 layers!  (Which is really just to say: that's what kind of layout a multilayer stackup is best at.)

Anyway, the lack of VCC plane is almost never a problem; indeed, it may even be an advantage, since the lengthy traces will filter ripple easier, as you are right to be concerned about.  It's another good reason to use the stitched ground method, I suppose: there's no paired conductor to form a transmission line, it's just ground all the way.  (Save for parasitic waveguide modes between stitch points, but those will all be low impedance, fairly lossy, and extremely high frequency.)  There may be ground bounce, but as seen by a local subcircuit, it will manifest as normal mode noise.

If you wanted to use a PLCC or TQFP packaged FPGA at high speeds, on a two layer board, you might have some problems packing in enough bypass caps and vias around the periphery, but for sure, the problem doesn't even exist in denser packages (BGAs) -- because you must use multilayer boards for those!

Tim

[tggzzz]

All of that is either wrong or too black-and-white. Having said that, breaks in a plane do significantly reduce its effectiveness - which can be beneficial in the right circumstances. See any discussion of mixed analogue/digital PCB design.

I would not call gapping a plane to isolate analog circuitry from switching noises "reducing its effectiveness" since the plane's effectiveness is not going to degrade much unless you put those split-planes and slots in the path of high-speed signals.

Er, that's precisely one reason when you would have a split plane, the other being if there is high currents that you don't want near sensitive analogue (or digital) electronics. In those circumstances you don't want a single ground plane.

Maybe I'm missing what you are trying to say.

Currents don't just flow at random through planes. The faster the edge rate the more they couple into the plane. If you take a single trace positioned above a reference plane and terminated with a load into the plane at far end and you track the return current flow you will see the electrons run pretty much in a straight line from termination point back to source for DC current. Increase the frequency and they will start to follow the shape of the source path. Even though there is a solid slab of copper, they will run in the path shaped by the sender.

Valid. Your points aren't related to my limited statements.

[pyrohaz]

Thank you all for your comments, they've been awfully insightful, albeit some over my head!

I've got an application specific question here, I'm designing the PCB for a simple parallel driven TFT display. My Byteclock will be ~2MHz and I've got round to laying out my board. I have the exact trace lengths and I'm wondering if this will cause any major problems with regards to data integrity.

(All in mm)
Data 0 - 25.918
Data 1 - 27.310
Data 2 - 28.787
Data 3 - 28.791
Data 4 - 25.460
Data 5 - 22.128
Data 6 - 18.797
Data 7 - 15.466
Clk      - 29.871

Each of the traces has one via included to go from top side to bottom side of the board.

[tggzzz]

My Byteclock will be ~2MHz

But what's the edge rate or rise/fall transition time?

See http://www.ganssle.com/video/episode1.html for a graphic illustration of why the rise/falltime is more important than the repetition interval.

[pyrohaz]

My Byteclock will be ~2MHz

But what's the edge rate or rise/fall transition time?

See http://www.ganssle.com/video/episode1.html for a graphic illustration of why the rise/falltime is more important than the repetition interval.

Thank you very much for that video, it was actually really good and cleared up a lot of my questions. One thing I do have to ask is why no development boards, or any of the ST products actually have termination? The STM32F4 discovery board for example has a codec on board with a bit clock of upto 192k*24 =  ~4.6MHz with the "fastest" defined rise time from the STM32F4 (defined at 100MHz IIRC) yet there is no form of termination or anything that has been explained in that video.  The board does however work and must work enough for them to sell the thousands of them that they have.

Sorry about my whole frequency relation thing with respect to signal integrity, I'm trying to get my head around why ST rate their rise times in relation to frequency.

[DanielS]

One thing I do have to ask is why no development boards, or any of the ST products actually have termination? The STM32F4 discovery board for example has a codec on board with a bit clock of upto 192k*24 =  ~4.6MHz with the "fastest" defined rise time from the STM32F4 (defined at 100MHz IIRC) yet there is no form of termination or anything that has been explained in that video.  The board does however work and must work enough for them to sell the thousands of them that they have.

As long as any oscillations from lack of termination have time to settle before the IC's clock-to-input setup window and remains stable through its input hold window, the stuff in-between can be almost any garbage within reason.

On short traces and relatively low transition rates, the signal will have time to settle even without termination and whatever ripple might be left from high frequency harmonics or edge noise will be too little to affect the outcome.

[tggzzz]

One thing I do have to ask is why no development boards, or any of the ST products actually have termination? The STM32F4 discovery board for example has a codec on board with a bit clock of upto 192k*24 =  ~4.6MHz with the "fastest" defined rise time from the STM32F4 (defined at 100MHz IIRC) yet there is no form of termination or anything that has been explained in that video.  The board does however work and must work enough for them to sell the thousands of them that they have.

As long as any oscillations from lack of termination have time to settle before the IC's clock-to-input setup window and remains stable through its input hold window, the stuff in-between can be almost any garbage within reason.

Provided any out-of-tolerance voltages do not cause scr latchup - which depends on the the input protection designed in by the manufacturer.

Provided ringing is not interpreted as a double transition - problematical if driving a counter, or if using "traditional hardware" i/o techniques where setup and hold times are closer to the limits than if  "bit banging" a clock separately from data.

On short traces and relatively low transition rates, the signal will have time to settle even without termination and whatever ripple might be left from high frequency harmonics or edge noise will be too little to affect the outcome.

You ought to define "short". If the track (or stub) length is <1/6 the distance the transition occupies (~6"/ns), the rule-of-thumb is that there won't be a problem. That translates to 5" for a 5ns transition.

I've seen reports of RPi some output transitions being <2ns, but have not investigated myself.

[DanielS]

Provided any out-of-tolerance voltages do not cause scr latchup - which depends on the the input protection designed in by the manufacturer.

That would be covered by the "within reason" part.

Provided ringing is not interpreted as a double transition - problematical if driving a counter, or if using "traditional hardware" i/o techniques where setup and hold times are closer to the limits than if  "bit banging" a clock separately from data.

What I wrote was only about the data signals. If you are going to "bit bang" a clock, you obviously need to make sure it is clean and meets the destination's timing requirements. In the case of the post I was replying to though, I doubt you would want to bit-bang a 5+Mbps stream to/from a DAC/ADC.

You ought to define "short". If the track (or stub) length is <1/6 the distance the transition occupies (~6"/ns), the rule-of-thumb is that there won't be a problem. That translates to 5" for a 5ns transition.

I go with 1/100th of the fundamental as my thumb-rule: even if the only termination on the data lines is the 8-10 ohms source drivers into 100-110 ohms traces, the signal should settle well within 5% long before the setup window no matter how sharp the transitions are.

Obviously, having 20-30 end-to-end reflections before the signal settles would not be acceptable on clocks.

[tggzzz]

Provided any out-of-tolerance voltages do not cause scr latchup - which depends on the the input protection designed in by the manufacturer.

That would be covered by the "within reason" part.

That meaning of "within reason" may have been evident to you; I very much doubt it was for the OP.

My information was for the OP, not you.

[tggzzz]

My Byteclock will be ~2MHz

But what's the edge rate or rise/fall transition time?

See http://www.ganssle.com/video/episode1.html for a graphic illustration of why the rise/falltime is more important than the repetition interval.

Thank you very much for that video, it was actually really good and cleared up a lot of my questions. One thing I do have to ask is why no development boards, or any of the ST products actually have termination? The STM32F4 discovery board for example has a codec on board with a bit clock of upto 192k*24 =  ~4.6MHz with the "fastest" defined rise time from the STM32F4 (defined at 100MHz IIRC) yet there is no form of termination or anything that has been explained in that video.  The board does however work and must work enough for them to sell the thousands of them that they have.

There are several possible reasons.

If the terminations are not needed on their PCB then clearly they can save money. Understanding when/were they are.aren't needed is beyond the scope of this thread, but see the other points about "1/6", and read Howard Johnson's book or blog http://www.edn.com/electronics-blogs/4238443/Signal-Integrity

Many large ICs, especially those receiving/driving high speed signals defined by a specific standard (e.g. LVDS) have the terminations on-chip - which is very good electrically. Some general-purpose ICs (e.g. FPGAs) contain I/O blocks where the voltages, currents and terminations are defined by configuration.

Sometimes the relevant termination cannot be defined by the PCB manufacturer, since it is determined by whatever the PCB is connected to. Usually that's not a problem for drivers on the PCB but can be a problem for receivers on the PCB (since resistors can't be added to the PCB).

Sorry about my whole frequency relation thing with respect to signal integrity, I'm trying to get my head around why ST rate their rise times in relation to frequency.

Well, there is the time<->frequency duality thing of course, but based on your comment ans without reading the ST document, yes it is unusual. Analogue and RF people tend to think in terms of frequency rather than time.