I will give my observations, not that they are right or anything. Taken with a grain of salt.
It is important to have the high current loop done well, as LT mentions.
R12 return to GND terminal should be dedicated, having it's own pour or trace. Right now, R12 currents add noise to C3 and all the right-side GND pour there.
I would move everything up and have a dedicated pour connecting R12 right to the GND terminal and C4, C5, and all other GND pour isolated with a slice. Like a fork or "Y".
Pin 3 CHARGE should be tied to VCC? Usually run that like pin 1, 4 (jut out) instead of directly between pads so the PCB house does not mistake for a copper bridge.
I do not see thermal reliefs on the PCB top (red) but do for the bottom layer. It will be very hard soldering the transformer, caps etc. to get enough heat there.
I suggest a (flyback) HV output capacitor on the board, even a little one. Otherwise it will be a very noisy wire connecting to HV OUT and interfere with other hardware. Where are your output caps and bleeder resistor?
The MOSFET drain connection is med. voltage (<100V) very noisy so I would have no pour under the transformer to the feedback via, just need a thin trace connecting to the transformer. Best to keep the gate trace a bit further away from it (drain) instead of alongside.
The transformer emits electrical noise from it's windings and you have nothing to shield the IC. The underbelly of the transformer can "see" your IC and traces.
Under the transformer I would have a GND pour to shield the E-field from the transformer windings from radiating onto the IC.
I put an LED on something like this so I know it's running and hazardous, for safety.
The 56uF 25V caps are spec'd as polymer types, but you have a boxed footprint. 100uF seemed more popular and LS=2.5-3.5mm check sizing.
I think the
IRF540 (100V 28A 7.7m) is oversized and you could save a lot of room there.
PHT6NQ10T (100V 3A 90mR) is SOT-223 part LT gives as an example.