Author Topic: Poor load regulation on SEPIC  (Read 1678 times)

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Offline MenxiuTopic starter

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Poor load regulation on SEPIC
« on: April 26, 2018, 04:50:22 pm »
As I'm writing my report, I've reached a stump, where i can't fully explain why the load regulation on my converter is so low. From my understanding, part of the reason is because i'm running it off a breadboard, so there are parasitic capacitance and inductance causing increased ripple on the output voltage. The breadboard also increases resistance because of the tracks and at high load current, there are power losses are more significant. ( Am i right? )

As you can see from the calculations done, I have designed it so my prototype can handle up to 500mA.
Is the reason behind poor load regulation solely because of the breadboard? Or could it be because of the compensation design?

Also, I don't fully understand how the current mode sensing works in this operation. The datasheet explanation seems a bit vague. I understand that the current sense resistor is placed there, so the switch current will induce a voltage across it and the voltage is brought to a comparator and amplified. How does Vc come into play? and what is beyond that?
https://imgur.com/a/Ez9SOB7 

Thanks in advance.

EDIT: 500mA.
« Last Edit: April 28, 2018, 04:14:50 pm by Menxiu »
 

Offline T3sl4co1l

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Re: Poor load regulation on SEPIC
« Reply #1 on: April 26, 2018, 07:51:59 pm »
Did you think that poor little Cs would actually handle the 2.35A RMS predicted to flow through it? :-DD

...In case you were unaware, no... real components are not at all ideal, and electrolytics are probably a poor choice in this circuit.  Try much larger electrolytics (470uF or more?) which may have usefully low ESR, or ceramics. :-+

Tim
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Bringing a project to life?  Send me a message!
 
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Offline strawberry

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Re: Poor load regulation on SEPIC
« Reply #2 on: April 26, 2018, 10:04:25 pm »
I used 6x 10uF 1206 ceramic for 10A load
it's recommended for not-coupled inductor to use both electrolytic and ceramic

In regulation   Vc = Vref = V ( current shunt ) * 20 ( Av )
Vc is compensation
 
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Offline MenxiuTopic starter

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Re: Poor load regulation on SEPIC
« Reply #3 on: April 26, 2018, 10:17:34 pm »
Hm, i read a guide from TI on designing SEPIC . In their calculations, they estimated about 2Amps as well, but they chose a 10uF ceramic capacitor.  I can't get my hands on any ceramic caps, but is a larger electrolytic like you suggested an alternative?

That explains why the cap was getting real hot.  |O
Anything else i should be aware of? besides the large ESRs i have in my circuit due to electrolytic caps, cause those, i won't be able to change. unfortunately.


Thank you :)
« Last Edit: April 26, 2018, 10:19:09 pm by Menxiu »
 

Offline MenxiuTopic starter

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Re: Poor load regulation on SEPIC
« Reply #4 on: April 26, 2018, 11:48:16 pm »
An update on the issue. I realised that the issue comes from my input power supply. It was rated at 2A max output. That probably explains why beyond 0.5A output load current, the drop off was so significant.
I have then recalculated for the inductors and output cap.



Now my question is, given my calculation of the inductors requires atleast 52uH , how am i maintaining the 12Vout in my prototype? Is my inductor not saturating?
 

Offline T3sl4co1l

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Re: Poor load regulation on SEPIC
« Reply #5 on: April 27, 2018, 10:16:28 am »
Mind you're still losing a lot of voltage drop in the capacitors, so that will reduce you capacity to begin with.

Smaller inductors reduces maximum output as you'll be firmly in DCM (~"150%" ripple).  The high ripple also exacerbates cap loss.

You'll still get 12V somewhere, but you didn't mention what load you're getting it at...

Tim
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Offline MenxiuTopic starter

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Re: Poor load regulation on SEPIC
« Reply #6 on: April 27, 2018, 03:34:02 pm »
ahh, okay. I'm getting 12Vout at load currents from 100mA to 400mA. Then at 500mA, the voltage drops a little bit.
 

Offline MenxiuTopic starter

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Re: Poor load regulation on SEPIC
« Reply #7 on: April 28, 2018, 03:51:32 pm »
Hi,
So i've come across another issue. Say, i want Vout=1.7V. I calculated that the inductance needed would be 120uH, and output capacitance of 15uF. (For a 500mA load current)
As you can see from the pictures(taken from simulation with ideal components), green representing 100mA load current and blue 500mA. The inductor current ripple is insanely high.

But what i've noticed is when i increase the output capacitor to 200uF, the current on the inductor is much much lower and stable.
« Last Edit: April 28, 2018, 04:15:36 pm by Menxiu »
 

Offline Siwastaja

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Re: Poor load regulation on SEPIC
« Reply #8 on: April 28, 2018, 04:06:39 pm »
Look at the actual capacitor datasheets. Electrolytic cap datasheets list maximum ripple current through them; if it's exceeded, the lifetime will drop. If it's exceeded severely, the lifetime can be as short as minutes. And, of course, the efficiency will be horrible due to all the resistive heating.

For an elcap of that size, the rating would be typically something around 50-100mA only!

Most elcaps are only specified at 120Hz. They are, typically, even higher in ESR and ESL than those that have ratings at 100kHz.

If you really want an elcap with safe ripple current of 2A, it's going to be huge.

If you only need 10uF, just don't use electrolytics, as 10uF is easily achievable with ceramics.

 

Offline MenxiuTopic starter

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Re: Poor load regulation on SEPIC
« Reply #9 on: April 28, 2018, 04:14:02 pm »
Sorry for the confusion, these are results from simulation in LTspice. I'm trying to figure out why does the current in the inductor behave this way.
 

Offline T3sl4co1l

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Re: Poor load regulation on SEPIC
« Reply #10 on: April 28, 2018, 06:44:09 pm »
Calculations for bypass capacitance are almost always not exact value, but minimum value.

You can use more, and should, for a variety of reasons.  To deal with ESR, in this case, you must!

The purpose is to have an impedance low enough, so that, when Iripple is applied to it, Vripple meets your spec.  Obviously, if the capacitor's impedance is higher, Vripple will blow your spec, and this is true whether the impedance is capacitive (just the reactance calculated) or complex (if resistive, the ESR adds directly!).

It can be a bonus, too, to have more than the minimum capacitance.  It gives more time for the control circuit to respond to errors.  If the controller can only respond so quickly, then it won't be able to regulate output voltage under variations in line and load -- again, where regulation is defined by a spec, like variation from the intended output.  Just like Vripple. :)  Minding, of course, this means the compensation values need to be suited to the capacitance as well!

Tim
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Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
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Offline mariush

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Re: Poor load regulation on SEPIC
« Reply #11 on: April 28, 2018, 06:57:41 pm »
Maybe try some polymer capacitors - if you can't buy them locally maybe recover (desolder) some from a broken motherboard or video card. 100-270uF 16v capacitors should be easy to find on such things.
 
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Offline MenxiuTopic starter

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Re: Poor load regulation on SEPIC
« Reply #12 on: April 28, 2018, 07:03:22 pm »
I will be getting ceramic capacitors by tomorrow, I plan to replace the coupling capacitor and place another one in parallel with the electrolytic cap for output capacitors.

Right now, i'm struggling to understand, why is using a smaller inductor giving me a more stable voltage output than using one as suggested by calculation. Is this because eventhough it saturates and operates in DCM, with the large output capacitance, the smoothing is enough to stabilize it?

What exactly is the role of the inductor here?
« Last Edit: April 28, 2018, 07:11:57 pm by Menxiu »
 


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