Author Topic: Poor mans analog multiplier  (Read 16359 times)

0 Members and 1 Guest are viewing this topic.

Offline GKTopic starter

  • Super Contributor
  • ***
  • Posts: 2607
  • Country: au
Poor mans analog multiplier
« on: September 19, 2014, 12:46:40 pm »
I've got a design on the bench that requires eight linear, DC-coupled and stable analog multipliers. That many AD633's starts to get expensive. Many people have tried to use a Gilbert Cell MC1496 for this role with only very average results.

Well after a little head scratching, here is my solution to the problem, using three MC1496's to essentially replicate the internal topology of the AD633 and similar multipliers.

IC1 and IC2 form the exponential voltage converter that kills 3 birds with one stone:
1) DC biases the twin differential transistor pair of IC3
2) Temperature compensates the gain of the twin differential transistor pair of IC3
3) Linearises the twin differential transistor pair of IC3

I quickly built the circuit on breadboard this evening and it appears to work exceptionally well. Without any offset trimming whatsoever the DC offset error at the output is under 10mV! Better than some samples of my AD633's!

I've done some measurements and the individual transistors inside the MC1496 are remarkably well matched. Only 2 transistors inside IC1 are actually utilized in the circuit, but I wouldn't bother substituting the package with a dual NPN transistor. You won't find a dual with better device matching than those two transistors inside the MC1496 for anywhere near the same price - mine measured a better than 50uV Vbe match.








« Last Edit: September 19, 2014, 12:49:18 pm by GK »
Bzzzzt. No longer care, over this forum shit.........ZZzzzzzzzzzzzzzzz
 
The following users thanked this post: Brutte, mikerj, ch_scr

Offline GKTopic starter

  • Super Contributor
  • ***
  • Posts: 2607
  • Country: au
Re: Poor mans analog multiplier
« Reply #1 on: September 19, 2014, 01:52:42 pm »
BTW, here is the circuit that is replicated:




See application note:

http://www.analog.com/static/imported-files/tutorials/MT-079.pdf
Bzzzzt. No longer care, over this forum shit.........ZZzzzzzzzzzzzzzzz
 

Offline moffy

  • Super Contributor
  • ***
  • Posts: 1734
  • Country: au
Re: Poor mans analog multiplier
« Reply #2 on: September 20, 2014, 12:07:38 am »
Can you provide any harmonic distortion/FFT graphs, figures? Would be interesting.
 

Offline GKTopic starter

  • Super Contributor
  • ***
  • Posts: 2607
  • Country: au
Re: Poor mans analog multiplier
« Reply #3 on: September 20, 2014, 06:47:01 am »
I think an FFT in SPICE would be useless as the transistors in the virtual world are all perfectly matched, and the linearity of the multiplier depends very much upon the matching of the transistors.

I think the best way to simply and effectively asses the static transfer linearity in the real world would be to set one input to full scale and then sweep the other the full range in accurately measured discrete steps and tabulating the results. Then the inputs can be swapped and the test repeated.

I'll get around to that maybe in several days.


   

 
Bzzzzt. No longer care, over this forum shit.........ZZzzzzzzzzzzzzzzz
 

Offline moffy

  • Super Contributor
  • ***
  • Posts: 1734
  • Country: au
Re: Poor mans analog multiplier
« Reply #4 on: September 23, 2014, 11:46:50 pm »
That would be interesting. When I mentioned FFT I was meaning on a realtime signal not a simulation. Sorry for the confusion. But I would also be interested in the BW performance. THD will get worse with frequency. But then that is a whole new method of testing which requires good oscillators and a spectrum analyser. I know I don't have that.
It was neat the way you used the MC1496 as a matched npn pair. Nice!
 

Offline Odysseus

  • Regular Contributor
  • *
  • Posts: 147
  • Country: us
Re: Poor mans analog multiplier
« Reply #5 on: September 24, 2014, 07:18:49 am »
I think an FFT in SPICE would be useless as the transistors in the virtual world are all perfectly matched, and the linearity of the multiplier depends very much upon the matching of the transistors.

I think the best way to simply and effectively asses the static transfer linearity in the real world would be to set one input to full scale and then sweep the other the full range in accurately measured discrete steps and tabulating the results. Then the inputs can be swapped and the test repeated.

I'll get around to that maybe in several days.

In general, you can model the output of a non-ideal multiplier as a linear combination of the input voltages raised to various degrees, i.e.:
out = a0 + a1*x + a2*y + a3*x*y + a4*x^2 + a5*y*^2 + a6*x^2*y + ....
In the above case, a0 would represent DC offset, a1 represents x feed through, a2 is y feed through, a3 is the main gain coefficient.  Ideally only a3 would be non-zero.  Any way, if you take a bunch on measurements, you can perform a linear regression to find the best coefficients to explain your data.

I actually built an analog multiplier using just SMD matched pair transistors for a school project.  I think you'll enjoy reading the documentation I produced for it. 
 

Offline GKTopic starter

  • Super Contributor
  • ***
  • Posts: 2607
  • Country: au
Re: Poor mans analog multiplier
« Reply #6 on: September 24, 2014, 08:47:52 am »
That would be interesting. When I mentioned FFT I was meaning on a realtime signal not a simulation. Sorry for the confusion. But I would also be interested in the BW performance. THD will get worse with frequency. But then that is a whole new method of testing which requires good oscillators and a spectrum analyser. I know I don't have that.
It was neat the way you used the MC1496 as a matched npn pair. Nice!


In most precision DC applications bandwidth will be mostly a function of the op-amp type selected to convert the differential current outputs of the Gilbert Cell(s) to a ground-referenced signal voltage. For linear RF applications this stage could be omitted and the output signal picked off in a single-ended fashion from the Gilbert Cell with a signal coupling capacitor. With the moderately high fT of the MC1496 transistors I think it should be a reasonably good performer throughout the HF band, particularity so if the bias currents are increased.

I can measure THD+N to 1ppm or better between 10Hz and 50kHz only - several orders of magnitude better than the expected multiplier linearity. Before doing any serious measurements I'd have to get a prototype with offset error trims soldered up, rather than the current thing cobbled together on breadboard.   
« Last Edit: September 24, 2014, 09:42:31 am by GK »
Bzzzzt. No longer care, over this forum shit.........ZZzzzzzzzzzzzzzzz
 

Offline GKTopic starter

  • Super Contributor
  • ***
  • Posts: 2607
  • Country: au
Re: Poor mans analog multiplier
« Reply #7 on: September 24, 2014, 09:28:57 am »
I actually built an analog multiplier using just SMD matched pair transistors for a school project.  I think you'll enjoy reading the documentation I produced for it.


That looks interesting. BTW, the most effective way to test for feed-through and to individually asses the separate x and y input offset error terms independently of the output offset error term is with the aid of a low frequency signal generator.

For example, ground the x input and apply a 100 Hz full scale peak-peak sinewave to the y input and examine the resultant signal at the output. If, for example, your sinewave test signal is 10V peak-peak and the amplitude of the ac component of the resultant output signal is 64mV p-p, then (assuming a scaling factor of unity) the x input offset error is 0.064/10 = 6.4mV. If the output sine is in phase with the input signal, then the error is +6.4mV; if the output sine is out of phase then the error is -6.4mV.

You can eliminate this LF feed-through from the y input by trimming the x input offset for a zero null in the ac signal component at the output. Then you can simply asses and trim out the y input offset error and x input feed through using a repeat of the same procedure but with the input connections reversed. Note than only once you have accurately trimmed out both the x and y offset errors and feed-through can you ground both inputs to accurately measure the output offset error term in isolation (in cases that the output offset error term isn't very large in comparison to the product of the untrimmed input offset errors).

« Last Edit: September 24, 2014, 09:43:53 am by GK »
Bzzzzt. No longer care, over this forum shit.........ZZzzzzzzzzzzzzzzz
 

Online macboy

  • Super Contributor
  • ***
  • Posts: 2254
  • Country: ca
Re: Poor mans analog multiplier
« Reply #8 on: September 24, 2014, 03:02:27 pm »
I think an FFT in SPICE would be useless as the transistors in the virtual world are all perfectly matched, and the linearity of the multiplier depends very much upon the matching of the transistors.

I think the best way to simply and effectively asses the static transfer linearity in the real world would be to set one input to full scale and then sweep the other the full range in accurately measured discrete steps and tabulating the results. Then the inputs can be swapped and the test repeated.

I'll get around to that maybe in several days.
You can modify the transistor models in order to simulate non-matched devices. Use the undocumented "ako" directive. The following three spice directives create 3 different low-gain (~12) versions of the 2n3055:
.model 2N3055a ako: 2N3055 bf={12+gauss(2)}
.model 2N3055b ako: 2N3055 bf={12+gauss(2)}
.model 2N3055c ako: 2N3055 bf={12+gauss(2)}

Then make NPN transistors of type 2N3055a/b/c, and they will all be slightly different gain. I use the above to test current sharing in a power supply with multiple output devices.
 

Offline GKTopic starter

  • Super Contributor
  • ***
  • Posts: 2607
  • Country: au
Re: Poor mans analog multiplier
« Reply #9 on: September 24, 2014, 11:54:56 pm »
Sure, but that will still be a crude approximation as far as Fourier analysis is concerned.
Bzzzzt. No longer care, over this forum shit.........ZZzzzzzzzzzzzzzzz
 

Offline Honk

  • Newbie
  • Posts: 4
  • Country: se
Re: Poor mans analog multiplier
« Reply #10 on: March 14, 2018, 08:50:16 pm »
Hello GK
I'm admiring your Poor Mans Analog Multiplier and could use this as simple Wattage calculator.
But I have a few questions if you don't mind?

1) Can this Circuit multiply Two DC voltage inputs to a multiplied DC voltage output?
2) Could you post a sharper image of the schematic as some of the values is very hard to read?
It's numbers 5 and 6 that looks precisely the same even when magnified.

I know this is an old topic yet very interesting.
« Last Edit: March 15, 2018, 08:50:09 am by Honk »
 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7733
  • Country: ca
Re: Poor mans analog multiplier
« Reply #11 on: March 15, 2018, 02:59:08 am »
I wonder how good 2 of these in parallel will work as DAC-DC controlled volume controls for line level audio.
 

Offline tecman

  • Frequent Contributor
  • **
  • Posts: 444
  • Country: us
Re: Poor mans analog multiplier
« Reply #12 on: March 15, 2018, 06:26:56 pm »
Temperature drift can be a killer.  Thermally bonding devices can help, but never as good as a monolythic solution.

paul
 

Offline aladan

  • Newbie
  • Posts: 1
  • Country: au
Re: Poor mans analog multiplier
« Reply #13 on: February 17, 2019, 07:42:00 am »
Hi Glenn/others,

Using MC1496s as this circuit does is great for cost-effectiveness, but unfortunately the LT1634-5 voltage reference costs as much the three MC1496s put together!

Is there a convenient alternative?  For my needs I could live with a little less precision and some slightly sloppy outcomes.

I plan to build two of these in one device - could I somehow share the one LT1634-5 between the two of them?  I can't see how I might do that, since it's not just a simple reference voltage, but instead is integral in the circuit.

I am only a relative newbie, and I confess I don't have a full appreciation for the subtleties of exactly how this circuit works.  I am hoping someone might be able to at least point me in the right direction to experiment and learn more.

Thank you,
Adrian
 

Offline RoGeorge

  • Super Contributor
  • ***
  • Posts: 6202
  • Country: ro
Re: Poor mans analog multiplier
« Reply #14 on: February 17, 2019, 10:19:31 am »
Either a Gilbert Cell, or maybe a RoGeorge Cell   :)
https://hackaday.io/project/7542-rogeorge-cell



Block diagram



Schematic diagram


1031182-2
Vin (blue) and Vout (magenta)

The blue trace is the input signal, and the magenta trace is the output of the four quadrant multiplier (here, the Vout is the Vin variable multiplied and animated between +1 and -1)

Later edit:

Replaced the pics from the now discontinued tinypic.com with pics hosted locally.
« Last Edit: July 24, 2020, 08:15:30 am by RoGeorge »
 

Offline mikerj

  • Super Contributor
  • ***
  • Posts: 3240
  • Country: gb
Re: Poor mans analog multiplier
« Reply #15 on: February 17, 2019, 11:03:21 am »
Either a Gilbert Cell, or maybe a RoGeorge Cell   :)

Not really equivalent; you have made a multiplying DAC rather than an analog multiplier.
 

Offline RoGeorge

  • Super Contributor
  • ***
  • Posts: 6202
  • Country: ro
Re: Poor mans analog multiplier
« Reply #16 on: July 24, 2020, 08:30:37 am »
Not really equivalent; you have made a multiplying DAC rather than an analog multiplier.

Sorry for necroposting, I was in the process of replacing a few pics from the discontinued tinypic.com and noticed that back then I didn't reply to your comment.

Indeed, it is not the same as an analog multiplier, it is rather an Analog x Digital multiplier.

It has the advantage that it can multiply negative voltages, too, and it can multiply with either positive or negative digital values, and it's based on an idea I never seen in other multiplying DACs.


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf